JPS593781B2 - data inspection equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for inspecting data that is composed of a plurality of bits, and in which the same logic signal must continue from an arbitrary bit to the least significant or most significant bit.

In digital electronic devices and the like, if the input is an analog signal, it must be converted into a digital signal and then input.

An analog-to-digital signal conversion circuit is used for this.
FIG. 1 shows a simplified analog-to-digital signal conversion circuit, and this type of circuit is widely used in the field because it has a simple structure and can be constructed at low cost. This circuit will be explained below. For convenience of explanation, this circuit is shown for the case where an analog signal is digitized into five levels, but the number of levels is not limited and various levels can be realized. N is an input terminal for inputting an analog signal, and R is a voltage dividing resistor. The connection point of each resistor R is made to be input to an analog-to-digital converter ADC. This analog-to-digital converter ADC drives the corresponding light emitting diode connected to the output side to turn on or off depending on whether each connection point of the resistor R reaches the gate threshold level, and converts the analog input signal. This converter ADC is commercially available. T1, T2, T3, T4, and T5 are phototransistors provided corresponding to the respective light emitting diodes L1, L2, L32, L4, and L5, which become conductive when the corresponding light emitting diodes are turned on, and become nonconductive when the corresponding light emitting diodes are turned off. The emitters of each phototransistor T1, T2, T32, T4, and T5 are grounded, and the collector resistor Rc
The collectors of each phototransistor T1, T2, T3, T4, T5 are connected to the control power supply Vcc via the input terminals 1, 12, 13, 13 of the digital electronic device CON.
14,I,. Now, when an analog signal of a predetermined level 131 is applied to the input terminal 1N, the light emitting diodes Ll, L2, and L3 emit light, which causes the input terminals 11, 12, and 13 of the electronic device CON to be logically 1
A signal of 1 "1" is applied, and a signal of "0" is logically applied to the other input terminals 14 and 5.Similarly, when an analog signal of level 114!v is applied to the input terminal 1N, the light emitting diode Ll, L2, L3, L4 emit light, and the electronic device CON
A signal of 1 "1" is logically added to the input terminals 11, 12, 13, and 14, and a signal of 1905 is logically added to the other input terminal 15.
The same applies to levels 1, 2, and 5. Such an analog-to-digital converter ADC
When the data is inputted to the electronic device CON, the same logic signal continues from an arbitrary bit to the least significant bit or the most significant bit.

That is, when the level of the analog input signal is 131V, each bit from input terminal 13, which is bit 3, to input terminal 11, which is the least significant bit, is logically W.
1ll, and the signals applied to the input terminals 14 and 15 indicating other bits are logically 101 signals. In other words, it becomes 110001111, and in the case of level 4 it is 1!
0111 "It becomes 1. Similarly, if the level is 0, W
5OOOOOO - 1 for level 1!00001 - 11000111 for level 2, 51 for level 5
It becomes 1111111. Therefore, for example, 1101
If the logic state of each bit of a piece of data is different from that of the adjacent bit, such as 0111, the data becomes an error. Such erroneous data occurs due to various factors such as failure of each component and disturbance. The present invention has a simple configuration, and can be used to detect errors in the data described above, that is, data that is composed of multiple bits and in which the same logic signal must continue from any bit to the lowest or highest bit. The object of the present invention is to obtain a data inspection device that can reliably inspect the following data.

In order to achieve the above object, the present invention is characterized by a shift register that temporarily stores input multiple bits of data to be inspected and is capable of serial output and parallel output, and a shift register that sequentially applies shift pulses to this shift register. a 1-bit temporary memory circuit whose memory contents are sequentially updated by logic signals of each bit sequentially output in series from the shift register upon application of the shift pulse; an OR circuit that inputs parallel output data, determines whether or not the logic signals of all bits of the input data are the same logic signals as a predetermined signal, and outputs a signal corresponding to the determination result; The present invention provides a data detection device comprising a temporary storage circuit that stores a predetermined logic signal and a determination result output circuit that outputs an abnormal signal when the OR circuit makes a negative determination.

An embodiment of the present invention shown in FIG. 2 will be described below.

SR is a shift register, and this shift register SR
has the ability to input, output, and output data in parallel. PIl, PI2, ......, Pl
Reference numeral 5 denotes a parallel input terminal for data, a signal of the least significant bit of the data is applied to the terminal PI1, and a signal of the most significant bit of the data is applied to the terminal P15. POl
, PO2, . . . , PO5 are parallel data output terminals, SO is a data serial output terminal, DS is a data set signal input terminal, and RS is a reset signal input terminal. M1, M2, . . . , M5 are temporary storage elements, which are connected in series. AN
Dl, AND2, . . . , AND5 are AND circuits. When a reset signal is applied to terminal RS, all temporary storage elements M1, M, . . . , M5 are reset. Terminals Pl, P2,...
..., when data is input to P5 and a set signal is applied to terminal DS, AND circuits ANDl, AND2, ...
......, the gate of AND5 opens, and the input data is temporarily stored in the memory elements Ml, M2, ......, M5.
is temporarily stored. These temporary storage elements Ml, M2,...
......, M5 transfers its memory contents to terminals POl, P
Output to O2, ......, PO5. terminal S
When one shift pulse is applied to P, temporary storage element M5
The storage contents of temporary storage element M4 are transferred to temporary storage element 2, the storage contents of temporary storage element M4 are transferred to temporary storage element M3, and the storage contents of temporary storage element M2 are transferred to temporary storage element M1 in the same manner. Then, the storage contents of the temporary storage element M1 are outputted from the terminal SO. Furthermore, when a shift pulse is applied to terminal SP,
The memory content of each temporary memory element is moved to a lower temporary memory element, and the memory content of the temporary memory element M is outputted from the terminal SO. In this way, when a shift pulse is sequentially applied to terminal SP five times, all input data is transferred to terminal SO.
is output from. Terminals POl, PO2,...
..., PO5 always stores the corresponding temporary storage elements M,,M2,
......, Outputs the memory contents of M5. Therefore, by applying a shift pulse to terminal SP,
If the data is shifted, the shifted data is output. Note that when the data is shifted, the logical w0WI signal is sequentially written into the uppermost temporary storage element M5. Such a shift register SR is not special at all and is commercially available. DSI,D
SI is a data set signal input terminal and a reset signal input terminal for inputting a data set signal and a reset signal to this device.

This device is provided, for example, in the electronic device shown in Fig. 1, and therefore, in order to operate the electronic device CON into a predetermined state, these signals are used from a timing signal generation circuit provided inside this device. do. Note that these signals are
It may be created separately from that of the electronic device CON. The dove is a temporary memory circuit, for example a flip-flop circuit can be used.

This temporary storage circuit 锇 inputs the signal from the serial output terminal SO of the shift register SR, temporarily stores it, and outputs it. The stored contents are updated by a signal output from the terminal SO every time the data in the shift register SR is shifted. The reset signal to the reset signal input terminal RSI is applied to the terminal RS of the shift register SR, and is also applied to the temporary storage circuit M via the NOT circuit N. Make sure to input it to the glue set terminal. 0R1 is the terminal POl, PO2 which is the parallel output of the shift register SR.
, ......, is an OR circuit that inputs all the signals from PO5, and is a temporary storage element Ml, M2, ...
..., M5, since at least one of them stores the signal 1111 logically, W? 11 signals are output, and the temporary storage elements Ml, M2,
......, all of M5 are logically 10? l
Only by remembering the signal of 10!
’ signal is output.

The output of the OR circuit 0R1 is outputted to the abnormal signal output terminal E via an AND circuit AND6 serving as a determination result output circuit. The gate of this AND circuit AND6 controls the opening and closing of the output of the temporary storage circuit N2 by a signal obtained through the NOT circuit N2. That is, the temporary memory circuit M
. By storing a signal of logically 101, the gate of the AND circuit AND6 is closed, and the output of the OR circuit 0R1 is output to the terminal E for the first time. SPC is a shift pulse generation circuit, and is composed of a delay circuit D, monostable multipipulators 0S1 and 0S2, an OR circuit 0R2, an AND circuit AND7, and a pulse oscillation section 0SC.

This circuit SPC inputs the data set signal to the terminal DSI, and applies this signal as the first shift signal to the terminal SP of the shift register SR through the delay circuit D and the monostable multivibrator 0S, and through the OR circuit 0R2. do. The data set signal applied to terminal DSI is simultaneously applied to terminal DS of shift register SR. Delay circuit D connects terminals DS and S of shift register SR.
This is to avoid applying signals to terminals P at the same time, and to ensure that input data to shift register SR is stored in shift register SR before applying a signal to terminal SP. The pulse oscillator 0SC repeatedly generates a pulse signal at regular time intervals, and its output is applied to the terminal SP of the shift register SR via an AND circuit AND7 and an OR circuit 0R2. The monostable multivibrator 0S2 receives a shift pulse signal applied to the terminal SP of the shift register SR via the delay circuit D, the monostable multivibrator 0S1 and the OR circuit 0R2, and from the pulse oscillator 0SC via the AND circuit AND7 and the OR circuit 0R. Terminal S of shift register SR
This is to avoid temporal duplication of the shift pulse signal applied to P, and this monostable multivibrator 0
S2 is configured to operate at the falling edge of the output of the monostable multivibrator 0S1, and its output is input to the AND circuit AND7. Note that the metastable time of the monostable multivibrator 0S2 is set to a sufficient time necessary to serially output the data stored in the shift register SR. CW is a down counter that can be preset, and ST is a setter that sets a set value to be input to this counter CW. This counter CW has a data set signal applied to the terminal DSI applied to the set terminal S. By doing so, the value set in the setting device ST is set. Then, the OR circuit 0R is applied to the subtraction terminal SB of the counter CW.
2 output will be input. A signal from the count end signal terminal UP of the counter CW is input to the AND circuit AND7 via the NOT circuit N3. In the case of the embodiment, the shift register SR is shown for inputting 5-bit data, so the setting value of the setting device ST is !
151. That is, the terminal S of the shift register SR
Five shift pulses are added to P, and shift register SR
When the memory contents have finished outputting serial output to the outside, the terminal UP
The gate of the AND circuit AND7 is closed by the signal from the terminal SP, and thereafter, the application of the signal to the terminal SP of the shift register SR is interrupted. Furthermore, the output signal of the AND circuit AND6 is also applied to the AND circuit AND7 via the NOT circuit N4. This is because if an abnormal signal is generated, the subsequent shift operation of the shift register SR is stopped. Figures 3 and 4 are diagrams showing the operation of each part. Figure 3 shows the case when normal data is input as the data to be inspected, and Figure 4 shows the case when abnormal data is input as the data to be inspected. shows.

In these figures, RSI represents a reset signal applied to terminal RSI, and DSI represents a data set signal applied to terminal DSI. Ml, M2, M3, M4, M5 are the memory contents of temporary storage elements Ml, M2, M3, M4, M5,
MO is the memory content of the temporary memory circuit pigeon, D is the output of the delay circuit D, 0S1 and 0S2 are the monostable multivibrator 0S1
, 0S2 output, 0SC is the output of pulse oscillator 0SC,
AND6 indicates the output of the AND circuit AND6. The operation will be described below with reference to these figures.

First, the operation when normal data, as an example, data 110011111, is tested will be described with reference to FIG. 3. The relevant data 1900111?1 is input to the shift register SR. At time t1, terminal RST
When the reset signal is applied, this causes the temporary storage element M
1, M2, .
......, all the memory contents of M5 are logically WlO
ll, and the temporary memory circuit M. The memory contents of are negation circuit N
1 logically becomes 91111. When a data set signal is applied to the terminal DSI at time T2, the shift register SR outputs its parallel input terminals Pll, Pl2, .
. . . , temporarily stores data 11001111 applied to P5 as data to be inspected. That is, here each of the temporary storage elements Ml, M2, M3, M4, M5 corresponds logically! 11111i1 Suga 1,. iW1-
Store the signal of the controller FO-101. At the same time, counter C
Is there a set value for W? 151 is preset. After a delay time T1 of delay circuit D from time T2, the fall of the output signal of delay circuit D is detected, and monostable multivibrator 0S1 outputs a pulse signal at time T3. This signal passes through the OR circuit 0R2, is applied to the terminal SP of the shift register SR, and shifts the stored contents by one bit. At the same time, the contents of counter CW are decremented by 1, and its stored contents are Ql4
It becomes ゛. At this point, temporary storage elements Ml and M2 logically store the signal Wllll, and temporary storage elements M3 and M4
, M5 logically stores 1101 signals. Furthermore, a temporary memory circuit M. logically stores a signal of 1 "1".As a result, the OR circuit 0R stores the temporary storage elements Ml, M2,
・・・・・・・・・Since all the memory contents of M5 are not logically 10q1, a signal of 15111 is logically output, but the output of the negation circuit N2 is logically FlOlV
Therefore, the gate of the AND circuit AND6 is closed, and the abnormality signal of 1e1wI is not logically output to the abnormality output terminal E. Is the output of the AND circuit AND6 logically 110?
', the output of the NOT circuit N4 is logically 15
115, and since the counter CW does not output a count end signal, the output of the NOT circuit N3 is logically 1.
It becomes 1111. Furthermore, monostable multivibrator 0S
The output of 2 detects the fall of the output of the monostable multivibrator 0S1, and as a result, the output of 2 logically changes to 1 from the time t/3.
111 signal is output. As a result, the AND circuit AN
The gate of D7 opens. Therefore, when the pulse oscillator 0SC generates a pulse signal at time T4, this signal passes through the AND circuit AND7 and the OR circuit 0R2 and is applied to the terminal SP of the shift register SR. Then, the contents of the shift register SR are further shifted by one pit.
At this point, the memory content of the temporary storage element M is logically 1
1111, and other temporary storage elements M,, M3, M4,
The memory content of M5 logically changes to WWOll, and the memory content of counter CW changes to 1131, but there is no other change. At time T3, when the pulse oscillator 0SC outputs a pulse signal, the temporary storage elements Ml, M2,...
..., all the memory contents of M5 are logically 101,
The output of OR circuit 0R1 is logical! 10-Counter CW
The content of changes to 12t1. Temporary memory circuit M. The memory content of is logically unchanged from 170V1, and the AND circuit AN
The gate of D6 remains closed. At time T6, when the pulse oscillator 0SC outputs a pulse signal, the storage contents of the shift register SR are shifted, but there is no change in the storage contents, and all temporary storage elements Ml, M2, . . .
......, M5 logically stores a signal of 1?0V1. At this point, the temporary memory circuit M. Since the stored content is logically 101, the gate of the AND circuit AND6 is opened. Temporary memory elements Ml, M2,...
..., are all the memory contents of M5 logical? 10?1
Therefore, the output of the OR circuit 0R1 becomes 101 logically. Therefore, the AND circuit AND6 logically outputs 91' to the abnormal signal output terminal E, indicating that there is no abnormality in the data.
1 signal is output. At this point, the content of the counter CW becomes 111. At time T7, when the pulse oscillator 0SC outputs a pulse signal, the contents of the shift register SR are shifted, but the contents do not change, but the contents of the counter CW become 1101, and the terminal UP of the counter CW
Logically! 5111 count end signal is generated,
The gate of the AND circuit AND7 is closed to prevent the subsequent pulse signal from the pulse oscillator 0SC from passing through. Furthermore, T
At time 8, the output of the monostable multivibrator 0S2 logically becomes 1101', and the data inspection ends. Thereafter, when other data is appropriate, the shift register SR
, and the data is checked using the same operation. Next, the operation when inspecting abnormal data, eg, data 11010111, will be described with reference to FIG. 4.

First, data 1W01011 in shift register SR? l
Enter. At time t1, each part is set, at time T2, data is set in shift register SR, at time T2, the contents of shift register SR are shifted by 1 bit, and at time T2, data is set in shift register SR.
The operation is the same as described above until an additional 1 bit shift is made at time point 4. However, the data to be inspected is 11010111W
Therefore, in the storage contents of the shift register SR at time T4, only the temporary storage element M2 is logically VllVW.
The signals of 1101 are stored logically for the others. At time T5, when a pulse signal is generated from the pulse oscillator 0SC, the contents of the shift register SR are shifted by 1 bit, the temporary storage circuit 马 logically stores the "O" signal, and the gate of the AND circuit AND6 is opened. At this point, the memory content of the temporary storage element M1 is logically ``1111'', and the others are logically q1 ``5'', so the OR circuit 0R
1 logically outputs a signal of 11111. Therefore, a signal of 1111 is logically outputted to the abnormality signal output terminal E, indicating that the data to be inspected is abnormal.
As a result, the AND circuit AND7 is closed, and thereafter, the application of the shift pulse signal from the pulse oscillator 0SC to the shift register SR is stopped, and the subsequent operation is stopped. The abnormal signal from the abnormal signal output terminal E is effectively used to stop the operation of various electronic devices, or to start execution of a predetermined process. From the above explanation, it is clear that other data can also be reliably checked for errors.

In the above embodiments, a case has been described in which a parallel input type shift register SR is used, but it may also be a serial input type shift register.

That is, there is no limitation on the input form as long as it has parallel output and serial output functions. Further, the shift pulse generating circuit SPC may also be a clock oscillator, a timing signal generating circuit, etc., which is included in an electronic device in which the present device is incorporated or connected to the present device. Further, in the above embodiment, for convenience of explanation, the data to be inspected is 5 bits, but the present invention is not limited to the number of bits of the data. As is clear from the above description, according to the present invention, it is possible to check whether there is an error in data that is composed of multiple bits and in which the same logic signal must continue from an arbitrary bit to the lowest or highest bit. It is possible to reliably test whether or not the Also,
Since it is configured by effectively utilizing the function of the shift register, it has the effect of simplifying the device configuration.

[Brief explanation of the drawing]

Fig. 1 is a block wiring diagram of an electronic device having an analog-digital circuit to explain the present invention, Fig. 2 is a block wiring diagram showing an embodiment of the present invention, and Fig. 3 is a block wiring diagram for inspecting normal data. FIG. 4 is a time chart showing the operation when inspecting abnormal data.

Claims (1)

[Claims] 1 Temporarily stores the input multiple bits of data to be inspected,
A shift register capable of serial output and parallel output, a shift pulse generation circuit that sequentially applies shift pulses to this shift register, and storage contents using signals of each bit that are sequentially output in series from the shift register upon application of the shift pulses. inputs a 1-bit temporary memory circuit that is sequentially updated and parallel output data of the shift register, and determines whether the logic state of all bits of the input data is the same logic state as a predetermined state. and an OR circuit that outputs a signal corresponding to the determination result, and a determination result output circuit that stores a predetermined logic signal in the temporary storage circuit and outputs an abnormal signal when the determination of the OR circuit is negative. A data inspection device comprising: