JPS5937870B2 - Semiconductor nonvolatile memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor non-volatile memory device, and particularly to a semiconductor non-volatile memory device, which has a trap region for trapping charges, and has a memory function by changing the threshold depending on the presence or absence of charges accumulated therein and the polarity of the charges. The present invention relates to a semiconductor nonvolatile memory device of a fixed type.

To make the explanation easier to understand, a case will be explained in which the trap region for trapping charges is composed of a conductive floating gate.

FIG. 1 is a cross-sectional view for explaining the general structure of a conventional semiconductor nonvolatile memory device having a floating gate.

In this device, a source region 2 and a drain region 3 are provided on the surface of a P-type semiconductor substrate 1, and a conductive floating gate 5 is provided on a channel portion between them with an insulating layer 4 interposed therebetween. A conductive control gate T is provided thereon with an insulating layer 6 interposed therebetween. The floating gate 5 is electrically floating and insulated from other conductive materials. Writing and erasing of information in this memory device is performed by injecting charge into the floating gate 5.

The injection is performed when avalanche breakdown occurs at the junction between the semiconductor substrate 1 and the drain region 3, and the hot carriers generated at that time overcome the energy barrier of the insulating layer 4 and are captured by the floating gate 5. It will be done. At this time, by applying a positive voltage to the control gate T, electrons among the hot carriers are captured by the floating gate 5, and by applying a negative voltage, holes are captured by the floating gate 5. A major drawback of this floating gate type memory device is that the voltage applied to the drain region 3 required for writing and erasing is higher than the standard power supply voltage when configuring the system as an IC. The point is that it requires a power source.

Therefore, conventional methods for lowering the voltage required for programming and erasing include increasing the concentration in the channel region in order to lower the breakdown voltage of the junction between the semiconductor substrate 1 and the drain region 3, and increasing the concentration in the floating gate 5. In order to increase the effectiveness of the control gate 7 during charge injection, it has been proposed to thin the insulating layer 6 between the floating gates 5 of the control gate 7. However, when the voltage required for programming and erasing is lowered using the method described above, even the voltage applied to the drain region 3 during reading generates a small amount of hot carriers, which are injected into the floating gate 5, so that the threshold voltage decreases. fluctuations occur. Such a phenomenon is a serious drawback in nonvolatile storage devices. The present invention aims to reduce the voltage required for writing and erasing in a semiconductor non-volatile memory device having a trap region for trapping charges, and also to reduce fluctuations in threshold voltage due to hot carriers being injected into the trap region during reading. The purpose is to provide a new structure that has never existed before. According to the present invention, the object is to provide a trap region for trapping charges on a channel portion between a source region and a drain region provided on the surface of a semiconductor substrate via an insulating layer, and to provide a PN trap region in the vicinity of the trap region. Provided is a semiconductor nonvolatile memory device, characterized in that a semiconductor region having a junction is provided via an insulating layer, and the insulating layer under the semiconductor region is thinned in the vicinity of the PN junction surface and thickened in other parts. This is achieved by

It is desirable that the junction surface of the above-mentioned PN junction be parallel to the direction connecting the semiconductor region and the trap region. An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a sectional view for explaining the structure of an improved nonvolatile memory device that is the premise of the present invention.

In this device, charges are placed on a channel portion between an n-type source region 12 and a drain region 13 provided on the surface of a p-type semiconductor substrate 11 via an insulating layer 14 made of a silicon oxide film with a thickness of about 400 Å. A floating gate 15 is provided as a trap area for trapping. In this example, this electrically floating floating gate 15 is made of polysilicon. Then, a polysilicon film is formed on the floating gate 15 via an insulating layer 16 made of a polysilicon nitride film with a thickness of about 100 A, which is obtained by nitriding the floating gate 15 made of, for example, polysilicon using a well-known technique. A semiconductor region 17 is provided. In particular, this semiconductor region 17 is a P+ layer 17PI::. A Pn junction 18 is formed with the n+ layer 17n, which is an n-type impurity region. The junction surface is parallel to the direction connecting the semiconductor region 17 and the floating gate 15, which is a trap region.

Furthermore, the P+ layer 17P and the n+ layer 17n are each doped with impurities so that the sheet resistance is 100Ω/or less, and the avalanche breakdown voltage at the Pn junction is extremely low, 6V or less. There is. Next, the operation of the nonvolatile memory device of this example will be explained.

In the case of writing (electron injection into the floating gate 15), a negative potential is applied to the p+ layer 17P of the semiconductor region 17. By keeping the n+ layer 17n at the ground potential, avalanche breakdown occurs at the Pn junction 18 between the P+ layer 17P and the n+ layer 17n, generating a large number of hot electrons and hot holes.

At this time, the semiconductor substrate 11 source region 12, drain region 13
By setting the voltage to the ground potential or a positive potential, a force directed toward the floating gate 15 is applied to the hot electrons, and the hot electrons are injected into the floating gate 15. Hot holes are absorbed into P+ region 17P. Erasing (semiconductor region 1 in case of hole injection into floating gate 15)
By applying a positive potential to the n+ layer 17n of No. 7 and keeping the P+ layer 17P at the ground potential, the P+ layer 17P and the n+ layer 17n
Avalanche breakdown occurs at the Pn junction 18 between the two, generating a large number of hot electrons and hot holes.

At this time, by keeping the region 12, the drain region 13, and the semiconductor substrate 11 at a ground potential or a negative voltage, a force directed toward the floating gate 15 is applied to the hot holes, and the hot holes are injected into the floating gate 15. The hot electrons are then absorbed by the n+ region 17n. In the case of reading, the P+ layer 17P and the n+
Layer 17n is held at ground potential.

Further, the source region 12 and the semiconductor substrate 11 are grounded, and a read voltage is applied to the drain region 13. When electrons are injected into the floating gate 15, no drain current flows because no channel is formed on the substrate surface. When holes are injected into the floating gate 15, a drain current flows because a channel is formed on the substrate surface. In this way, the state of the cell is read by turning on and off the drain current. According to the structure described above, the PN junction 18 of the semiconductor region 17 is grounded during reading, and the voltage applied to the drain region 13VC for reading does not affect this junction.

Therefore, the voltage required for writing and erasing, PN junction 18
No matter how much the withstand voltage is lowered, the threshold voltage will not fluctuate due to reading. Furthermore, since hot carriers are injected into the floating galvanizer 5 through the insulating film 16 above the floating gate 15, it is necessary to reduce the thickness of this insulating film 16, but the insulating film 14 below the floating gate 15 must be thin. There's no need to. Therefore, as observed in a semiconductor non-volatile memory device with a conventional structure in which the insulating film 14 under the floating gate 15 is thin, hot carriers are injected into the floating gate from the pinch-off region of the channel after long-time reading. A change in threshold voltage does not occur in a structure like that of FIG. Although the above improved structure required a negative voltage, the semiconductor nonvolatile memory device of the present invention can operate with only a positive voltage.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. A cross-sectional view for explaining the structure of the device of this example is shown in the third figure.
As shown in the figure.

The names of each part in FIG. 3 are exactly the same as in FIG. 2. The difference between this embodiment and the example shown in FIG. 2 is that the semiconductor region 17
The thickness of the insulating layer 16 under the area 16 near the Pn junction surface 18 is
' is made thinner and the other parts are made thicker; by doing so, the voltage required for charge injection is still low, and the capacitance between the semiconductor region 17 and the floating gate 15 is reduced. The above structure can be achieved by, for example, oxidizing the floating gate 15 made of polysilicon to a film thickness of 7.
After forming a polysilicon oxide film 16 with a thickness of about 00X and removing only the portion where the Pn junction 18 of the semiconductor region 17 will be formed later, the removed portion is nitrided to form a polysilicon nitride film 167 with a thickness of about 100A. However, it can be obtained by further forming a semiconductor region 17 made of polysilicon.

Next, the operation of the nonvolatile memory device of this embodiment will be explained.

First, in the case of writing and erasing, &n of the semiconductor region 17
By applying a positive potential to the + layer 17n and keeping the p+ layer 17P at the ground potential, avalanche breakdown occurs between the P+ layer 17P and the n+ layer 17n, generating hot electrons and hot holes. At this time, semiconductor region 1
7 and the floating gate 15 is the insulating film 16.
Since the floating gate 15 is made smaller by increasing its thickness, the potential of the floating gate 15 is mainly determined by the potentials of the source region 12, drain region 13, and semiconductor substrate 11. Therefore, in this embodiment, the source region 12 and drain region 13 are formed so as to overlap the floating gate 15. Therefore, in the case of electron injection into the floating gate 15, the source region 1
2. By keeping any or all of the drain region 13 and the semiconductor substrate 11 at a positive potential, the potential of the floating gate 15 is increased and electrons are injected.

In the case of hole injection into the floating gate 5, the source region 12, the drain region 13, and the semiconductor substrate 11 are
By keeping all of the floating gates at the ground potential, the potential of the floating gate 15 is brought close to the ground potential, and holes are injected. During reading, the P+ layer 17P and the n+ layer 17n are kept at ground potential to prevent avalanche breakdown at the Pn junction 18, the source region 12 and the semiconductor substrate 11 are grounded, and a read voltage is applied to the drain region 13. Apply. As in FIG. 1, the state of the cell is read by turning on and off the drain current. As described above, according to this embodiment, in addition to the effect of the improved example which is the premise of the present invention described above, there is an effect that operation is possible with only a positive voltage. In the above-mentioned embodiment, when the floating gate 15 made of polysilicon is used as the trap region, an additional 1 fC
The case where the conductive region 17 having a Pn junction is provided on the trap region has been described, but in other embodiments, first, for the trap region, a floating gate made of metal such as 1 molybdenum, 2 MNOS (Metal-
Nitride Oxide Semiconduct Or
), the interface between different insulating layers (nitride film and oxide film, etc.), 5
A conceivable example is one in which metal particles are provided at the interface between different or the same type of insulating layers as described above.

The conductive region 17 having a Pn junction may be provided in the vicinity of the trap region via an insulating layer to such an extent that hot carriers generated at the Pn junction can be injected into the trap region. As explained above, according to the present invention, in order to generate hot carriers injected into the trap region at the Pn junction provided in the semiconductor region, the avalanche of the Pn junction is used to reduce the voltage required for writing and erasing. Even if the breakdown voltage is lowered or the insulation layer from the Pn junction to the trap region is made thinner,
During readout, there is no change in the threshold voltage due to charge injection into the trap region by the readout voltage.

In other words, the voltage required for writing and erasing can be lowered, and the threshold voltage does not change. Furthermore, according to the present invention, it is possible to bring about the excellent effect that the device can be operated only with a positive voltage.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining the general structure of a conventional semiconductor nonvolatile memory device having a floating gate. FIG. 2 is a sectional view for explaining an improved semiconductor nonvolatile memory device that is the premise of the present invention. FIG. 3 is a sectional view for explaining an embodiment of the present invention. In the figure, 1,
11: Semiconductor device, 2, 12: Source region, 3, 13:
Drain region, 4, 14, 6, 16, 16': insulating layer,
5, 15: Trap region (floating gate), 1
7: Semiconductor area.

Claims (1)

[Claims] 1. A trap region for trapping charges is provided on a channel portion between a source region and a drain region provided on the surface of a semiconductor substrate via an insulating layer, and a PN layer is provided near the trap region.
1. A semiconductor nonvolatile memory device, characterized in that a semiconductor region having a junction is provided via an insulating layer, and an insulating layer under the semiconductor region is thin in the vicinity of the PN junction surface and thick in other parts. 2. The semiconductor nonvolatile memory device according to claim 1, wherein the semiconductor region having the PN junction is provided above the trap region with an insulating layer interposed therebetween.