JPS5937897B2 - selection gate circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a P-channel edge-gate field effect transistor (hereinafter referred to as P-type MO8T) and an N-channel edge-gate field effect transistor (hereinafter referred to as N-type MO8T).
Complementary insulated gate field effect transistor (hereinafter referred to as C-MO8T) consisting of a parallel connection body with
- Insert transmission gates with a configuration unit between multiple input terminals and a single output terminal in a number corresponding to the number of each input terminal,
A selection gate that selectively outputs one signal from among a plurality of information signals input to each of the input terminals by selectively making any one of these transmission gates conductive. It is related to circuits.

Generally, a transmission gate made of C-MO8T is
It is used to selectively gate a predetermined information signal from one point to another along the transmission path t by simultaneously making each MO8T making up the 8T conductive or nonconductive.

In addition, in order to selectively output one signal from among the plurality of information signals to the output terminal, the selection gate circuit uses a plurality of transmission gates to apply the selected information signal to the input terminal. This is a circuit that selectively turns on transmission gates.

FIG. 1 shows a circuit diagram for explaining a transmission gate constructed of a general C-MO8T.

This transmission gate 1 is P type MO8TP1 and N type MO8TN.
1, and this MO8T is connected in parallel between the input terminal 1 to which the information signal D1 is applied and the output terminal Out.

In addition, in the figure, Gpl is the gate terminal of P-type MO8TP1,
Gnl is the gate terminal of N-type MO8T N1, and the control signal S1 to the gate is applied to the gate terminal Gp1.
The control signal S1 is connected to the inverter Inv at the gate terminal Gn1.
An inverted signal S1 via l is applied.

FIG. 2 is a circuit diagram showing a conventional selection gate circuit using a transmission gate as shown in FIG.

This conventional selection gate circuit is a circuit that can selectively output one signal from among three information signals to an output terminal.

In the figure, the same or corresponding parts as in FIG. 1 are given the same reference numerals.

In addition, the transmission gate 2 is P type MO8TP2 and N type MO8T.
N2, and this MOS T receives the information signal D2.
is connected in parallel between the input terminal (2) to which is applied and the output terminal Out.

Furthermore, the transmission gate 3 is P type MO8TP3 and N type MO8
TN3, and this MOS T receives the information signal D.
It is connected in parallel between the input terminal 3 to which 3 is applied and the output terminal Out.

Also, in the figure, GD3. GD3 is P type MO8TP2.
The gate terminals of P3, GD2 and GD3 are each N-type MO8.
TN2. This is the gate terminal of N3, and the gate terminal Gl)2
A control signal S2 to the gate is applied to the gate, an inverted signal S2 of the control signal S2 via the inverter Inv2 is applied to the gate terminal Gn2, a control signal S3 to the gate is applied to the gate terminal Gp3, and the gate terminal An inverted signal S3 of the control signal S3 via an inverter Inv3 is applied to Gn3.

The operation of the transmission gate 1 shown in FIG.
When the potential is higher than the threshold voltage of 8T, an H level signal is applied to the gate terminal Gp1 of P-type MO8TP1, and the
Since a signal with a low potential level (hereinafter referred to as L level), that is, a potential lower than the threshold voltage of the P-type MO8T, is applied to the gate terminal Gn1 of the O8TN1, the P-type MO8TP and the N Since both MO8TN1 are in the off state, there is no conduction between the input terminal 1 and the output terminal Out.

Therefore, this transmission gate 1 becomes non-conductive, and the information signal D1 applied to the input terminal 1 is not transmitted to the output terminal Out.

Furthermore, when the potential of the control signal S1 is at L level, the P-type MO8
Since an L-level signal is applied to the gate terminal Gp1 of TP1 and an H-level signal is applied to the gate terminal Gn1 of N-type MO8TN1, P-type MO8TP1 and N-type MO8
Since both terminals T are in the on state, conduction is established between the input terminal 1 and the output terminal Out.

Therefore, this transmission gate 1 becomes conductive, and the information signal D1 applied to the input terminal □□ is transmitted to the output terminal Out.

As described above, in the conventional transmission gate, two MO8Ts Pl and N1 of different conductivity types are connected in parallel, and control signals having complementary polarities are applied to each gate.
By simultaneously making the two MO8T conductive or non-conductive, a predetermined information signal D1 is selectively routed from the input terminal 1 to the output terminal Out.

The reason for using the C-MO8 conventional transmission gate as described above is as follows.

In other words, when transmitting an information signal having either an H level or an L level to a load including a capacitance connected to the output terminal, the information signal is either H level or L level depending on the direction of the current flowing through the transmission gate. This is to ensure that one of the MO8Ts always operates as a source grounded, thereby enabling high-speed and highly efficient transmission of information signals.

The operation of the conventional circuit shown in FIG. 2 is to output the information signal D1 to the output terminal O.
When outputting the control signal S1 to the L level signal, as explained in detail in the transmission gate shown in FIG.
Control signal S2. S3 may be set as an H level signal to make the transmission gate 1 conductive and the transmission gate 23 non-conductive.

Similarly, when outputting the information signal D2 to the output terminal Out, the control signal S2 is set to an L level signal, and the control signal S1. S3 may be set as an H level signal to make the transmission gate 2 conductive and the transmission gate 13 non-conductive.

That is, the control signal S1 is an L level signal, the control signal S2. S
3 is an H level signal, the information signal D1 is output to the output terminal Out, the control signal S2 is an L level signal, and the control signal S7. When S3 is an H level signal, the output terminal Out
When the control signal S3 is an L level signal and the control signal S1°S2 is an H level signal, the information signal D3 is output to the output terminal Out.

Therefore, in this selection gate circuit, three information signals DI
, D2, and D3 to selectively output one signal to the output terminal Out.
-123 is used to selectively conduct the transmission gate to which the selected information signal is applied to the input terminal to obtain an output.

Although this conventional circuit has been described for the case where there are three information signals, generally a similar circuit is used to selectively output one signal from several to more than ten information signals. Configure a selection gate circuit that outputs to the terminal.

By the way, one of these multiple information signals can be selected selectively.
A selection gate circuit that outputs two signals to an output terminal is used, for example, in a system using a ROM (Read Only Memory) or a liquid crystal display system.

That is, in a system using a ROM, by applying a signal generated by the ROM as a control signal S to a transmission gate constituting a selection gate circuit, an information signal corresponding to the signal from the ROM is output to the output terminal Out. are doing.

In addition, in a liquid crystal display system, by applying a segment signal for liquid crystal display to a transmission gate as a control signal S, a lighting signal or a turning-off signal for the liquid crystal is transmitted as an information signal according to this signal and output to the output terminal Out. are doing.

As described above, the conventional selection gate circuit shown in FIG.
When incorporated in C, transmission gates 1 to 3 forming the selection gate circuit are made of C-MO8T, so P-type MO8T
Control signals 81-S3 applied to gate terminals Gp1-Gl)3 of P, ~P3 are applied to gate terminals Gn1-S3 of N-type MO8TN1-N3 via inverters Inv1-Inv3.
It was necessary to obtain inverted signals 81 to S3 to be applied to Gn 3, and it was necessary to form inparks Inv1 to Inv3 corresponding to the control signals 81 to S3 in the circuit that constitutes the IC.

Therefore, when a conventional selection gate circuit is incorporated into an IC, it is necessary to form circuits configuring imparks Inv 1 to Inv3 and lines for inverted signals 81 to S3 of control signals 81 to S3. This has the disadvantage that the pattern size becomes large.

Therefore, as the number of control signals S increases with the increase in the number of information signals, this drawback becomes even more noticeable and has become a very serious problem.

The present invention has been made in view of the above-mentioned drawbacks, and in a selection gate circuit, only one transmission gate to which a predetermined information signal is applied is selectively made conductive among a plurality of transmission gates constituting the selection gate circuit. This was done by focusing on the fact that two types of control signals are required for the transmission gate configured with C-MO8T, and by using a new circuit configuration, it was possible to incorporate it into an IC without impairing the function as a selection gate circuit. It is an object of the present invention to provide an improved selection gate constituted by a transmission gate made of C-MO8T, which can increase the degree of integration at the same time.

FIG. 3 shows a circuit diagram for explaining a transmission gate applied to a selection gate circuit according to the present invention.

In the figure, the same or corresponding parts as in FIG. 1 are given the same reference numerals.

The transmission gate 11 shown in FIG. 3 is a P-type MO8T p
Consists of H only, Gpl is P type MO8T R
1□ gate terminal.

A control signal S1 is applied to the gate terminal Gpit.

FIG. 4 is a circuit showing an embodiment of the selection gate circuit according to the present invention using the transmission gate shown in FIG.

This embodiment is a selection gate circuit that can selectively output one information signal from three information signals D1 to D3 to the output terminal Out, and includes three transmission gates 112131,
It is composed of an N-type MO8T n□ and a capacitor C8.

The transmission gate 11 is the same as that shown in FIG. 3 and is given the same reference numeral.

The transmission gate 21 is connected between the input terminal I21 to which the information signal D2 is applied and the output terminal Out.
It is composed of O8T P2.

The transmission gate 31 is connected between the input terminal I31 to which the information signal D3 is applied and the output terminal Out, and is connected to the P-type MO
It is composed of 8TP3.

In addition, GI) 2□J GPS, each P type MO8TP
21 + P is the gate terminal of 3t.

Further, a control signal S1 is applied to the gate terminal Gp,1, Gp
A control signal S2 is applied to 21, and a control signal S3 is applied to Gp3□.

Furthermore, at least between the input terminal IL and the output terminal OUT to which an L level signal is applied when all of the control signals 81 to S3 are at the H level, the N-type MO8Tn□ always applies a constant level signal. terminal IH and output terminal OUT
A capacitor C8 is connected between them.

Here, the input terminal IL is a terminal that enables the function of the selection gate circuit by supplying a first potential from outside the IC.

Gno is a gate terminal of the N-type MO8T nO, and a control signal T is applied to the gate terminal Gno.

FIG. 5 shows N embodiments of the invention shown in FIG.
is an integer) when applied to a general circuit having information signals.

In the figure, the same or corresponding parts as in FIG. 3 are given the same reference numerals.

In addition, in the figure, D1 to Dn are N information signals, 81 to Sn
are N control signals, and 1121 to n1 are N transmission gates.

The transmission gates each include a P-type MO8T to which a predetermined control signal is applied.

The selection gate circuit makes one selected from among the plurality of transmission gates making it conductive, makes the other transmission gates non-conductive, and outputs an information signal applied to the input terminal of the selected transmission gate. This is a circuit that takes out the signal to the output terminal.

In the conventional selection gate circuit shown in FIG. 2, in order to take out the information signal D1 to the output terminal O, an L level signal is applied to the transmission gate 1 as the control signal S1 to make it conductive, so that the information signal D1 becomes L. At level, N type MO8TN
1 is P-type MO8TP1 when the information signal D1 is at H level.
serves to take out the information signal D1 to the output terminal OUT.

Therefore, if the output terminal OUT is set to the L level in advance, when the information signal applied to the input terminal is at the L level, there is no need to take out the L level to the output terminal OUT. Therefore, the transmission gate is composed of only P-type MO8TP. That's fine.

The transmission gate 11 shown in FIG. 3 applied to the present invention utilizes the above-mentioned points.

That is, in the conventional transmission gate 1 shown in FIG. 1, a P-type MO8TP1 to which a control signal S1 is applied and an N-type MO8T N1 to which an inverted signal R complementary to the control signal S1 is applied are connected in parallel. It was composed of a connecting body.

On the other hand, the transmission gate 11 according to the present invention has a P-type MO88 to which the control signal S1 is applied, as shown in FIG.
It is composed only of TPII, and the output terminal OUT
By setting the gate to L level in advance, it has a function corresponding to the transmission gate 1 shown in FIG.

The operation of the embodiment circuit shown in FIG. 4 is that when outputting the information signal D1 to the output terminal OUT, first the control signal T
is set to H level, N-type MOS T n .

conducts, charges the capacitor C6, and outputs the output terminal O.
After setting UT to L level, control signal T is set to L level, N-type MO8T n□ is made non-conductive, and control signal S1
as an L level signal and a control signal S2. S3 is set as an H level signal, transmission gate 11 is turned on, and transmission gate 2131 is turned on.
).

That is, when the information signal D1 is at H level, the transmission gate port is in a conductive state, so H level is output to the output terminal OUT.
When the information signal D1 is at the L level, since the output terminal OUT was previously at the L level, the L level is output to the output terminal OUT.

Similarly, when outputting the information signal D2 to the output terminal OUT, the control signal S2 is set to an L level signal, and the control signal S1. The transmission gate 21 uses S3 as an H level signal.
It is sufficient to make the transmission gate 1131 conductive and the transmission gate 1131 non-conductive. When outputting the information signal D3 to the output terminal OUT, the control signal S3 is set to an L level signal, and the control signal S1 . S
2 as an H level signal, the transmission gate 31 is in a conductive state,
The transmission game N121 may be rendered non-conductive.

Therefore, in this embodiment circuit, the transmission gate 1121
The potentials of the control signals 81 to 83 applied to the P-type MO8TP1 in the conventional selection gate circuit shown in FIG.
The potential is exactly the same as that of the control signals 81 to S3 applied to ~P3, and since the information signals D1 to D3 are not always applied to the input terminals Ill to I31, the input terminals 11□ to ■3□ If the N-type MO8T n□ is made conductive when the information signals D1 to D3 are not applied to the circuit, the circuit becomes similar to the conventional circuit.

As described above, in the conventional circuit, the control signals 81 to S3 applied to the P-type MO8T as control signals and the control signals 81 to S3 applied to the N-type MO8T
Since inverted signals 81 to S3 that are complementary to the control signals S1 to S3 applied to T are required, six control signal lines are required when incorporated into an IC, and furthermore, inverted signals are formed. An impark circuit was required for this purpose.

However, in this embodiment circuit, the control signals for operating the MOS T are 81 to S3 and T.
When incorporated into an IC, the number of control signal lines is reduced to four, and since an inverted signal is not required, there is no need to form an inverter circuit.

Therefore, the selection gate circuit according to this embodiment has the effect of reducing the pattern size and improving the degree of integration of the IC.

In the circuit of FIG. 5, in order to selectively output one information signal from the N information signals D1 to Dn to the output terminal OUT, this selected information signal is applied to the input terminal. The control signal applied to the P-type MOS T constituting the transmission gate may be an L-level signal, and the other control signals may be H-level signals.

By the way, when a selection gate circuit having N information signals is constructed using a conventional circuit, the control signal is a P-type MOS T
N control signals 81 to Sn applied to the N-type MO8T
2N inverted signals S, ~Sn, which are applied to the control signals S1 to So and are complementary to each other, are required.
N inverter circuits were also required to form the inverted signals [1 to S'r1.

However, in the embodiment circuit shown in FIG.
It can be operated with control signals 81 to So and T,
The pattern size can be reduced and the degree of integration of the IC can be improved.

In the embodiments shown in FIGS. 3 to 5, the transmission gate is made up of one P-type MOS, but the present invention is not limited to this, and the transmission gate is made up of N-type MO8T, and the selection information An H level signal is applied as a control signal to the gate terminal of the N-type MOS T constituting the transmission gate to which the signal is applied to the input terminal, and a control signal is applied to the gate terminal of the N-type MO8T constituting the other transmission gate. Apply an L level signal as P to the MOS T controlled by the control signal T.
This can also be realized by applying an L level signal as a control signal to the MO8T, and applying at least the same H level as the information signal VH to the information signal vL when the control signal T is at the L level.

As described above, in the selection gate circuit according to the present invention, the N transmission gates connected between the N information signal input terminals and one common output terminal are M
A gate of the first conductivity type MO8T among the transmission gates mentioned above is configured to transmit N control signals having a potential relationship such that when one of them is at the first potential, all the others are held at the second potential. The first conductivity type M of the transmission gate is selectively made conductive because it is applied to the terminals sequentially.
The potential of the control signal applied to the gate terminal of O8T is the first
The potential and the potential of other control signals become the second potential, and this first
Because of the novel circuit configuration in which control signals having two types of potentials, ie, the second potential, are applied to the gate terminals of the single MO8T of the first conductivity type constituting the transmission gate, the function as a selection gate circuit is It has the effect of improving the degree of integration when incorporated into an IC without any damage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining a transmission gate constructed of a general C-MO8T, FIG. 2 is a circuit diagram showing a conventional selection gate circuit, and FIG. 3 is a selection gate according to the present invention. FIG. 4 is a circuit diagram for explaining a transmission gate applied to a circuit. FIG. 4 is a circuit diagram showing an embodiment of a selection gate circuit according to the present invention. FIG. A circuit diagram showing a general selection gate circuit is shown. In addition, in the figures, the same parts or corresponding parts are given the same reference numerals. 1121~n1...Transmission gate, D...
・Information signal, P...P type MO8T, S...
...Control signal, N...N type MO8T, ■...
...Input terminal, OUT...Output terminal.

Claims (1)

[Claims] 1. Each gate terminal is connected between N (N is an integer) information signal input terminals and one common output terminal, and when one of the gate terminals is at the first potential, the others are a transmission gate constituted by a single first conductivity type field transistor to which N control signals having a potential relationship that all hold a second potential are sequentially applied; and an input terminal to which the first potential is supplied from the outside. When a control signal at a first potential is applied to any one of the gate terminals of the first conductivity type field effect transistor connected between the output terminal and the gate terminal, the control signal at the first potential is applied. a second conductivity type field effect transistor to which a voltage is applied; and a capacitor connected between a terminal that maintains a first potential or a second potential and the output terminal; A control signal having N 1. A selection gate circuit, characterized in that one signal from among the information signals is selectively outputted to the output terminal. 2. In the selection gate circuit according to claim 1, a P-channel field-effect transistor is used as the first conductivity-type field-effect transistor, and an N-channel field-effect transistor is used as the second conductivity-type field-effect transistor. . A selection gate circuit, characterized in that the first potential is a potential that makes the P-channel field effect transistor conductive, and the second potential is a potential that makes the N-channel field effect transistor conductive. 3. In the selection gate circuit according to claim 1, an N-channel field effect transistor is used as the first conductivity type field effect transistor, and a P channel field effect transistor is used as the second conductivity type field effect transistor, A selection gate circuit characterized in that the first potential is a potential that makes the N-channel field effect transistor conductive, and the second potential is a potential that makes the P-channel field effect transistor conductive.