JPS593853B2 - Method for manufacturing semiconductor devices - Google Patents
Method for manufacturing semiconductor devicesInfo
- Publication number
- JPS593853B2 JPS593853B2 JP9821176A JP9821176A JPS593853B2 JP S593853 B2 JPS593853 B2 JP S593853B2 JP 9821176 A JP9821176 A JP 9821176A JP 9821176 A JP9821176 A JP 9821176A JP S593853 B2 JPS593853 B2 JP S593853B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- aluminum layer
- etching
- sio2 film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子の製造方法に関し、等に電極配線の
改良された半導体素子の製造方法を提供することを目的
とするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and an object of the present invention is to provide a method of manufacturing a semiconductor device with improved electrode wiring.
従来半導体装置の製造において半導体素子(以降素子と
略称する)に配線層を形成したのち電気絶縁被膜(以降
絶縁被膜と略称する)を積層被着する場合、あるいは配
線層を形成したのち絶縁被膜を積層被着する場合に、絶
縁被膜として低温酸化法(CVD法:Chemical
V&porDeposition)によるSiO2膜、
コーティング用SiO2をスピンオンシリカ(Spin
onSilica)により形成されるSiO2膜が適用
されていた。Conventionally, in the manufacture of semiconductor devices, a wiring layer is formed on a semiconductor element (hereinafter abbreviated as an element) and then an electrical insulating film (hereinafter abbreviated as an insulating film) is laminated and deposited, or an insulating film is applied after a wiring layer is formed. In the case of laminated deposition, low temperature oxidation method (CVD method: Chemical
SiO2 film by V&porDeposition),
Coating SiO2 is coated with spin-on silica (Spin
A SiO2 film formed by onSilica) was applied.
次に上記を第1図aないしiに例示するM)SiCの1
部のMosn汀の製造工程はまずN型シリコン基板1の
主面にSiO2膜2を形成する(図a)。Next, the above is illustrated in FIGS. 1 a to i.
In the manufacturing process of the Mosn layer shown in FIG.
次に前記SiO2膜2に蝕刻を施して開口2a、2a’
を設け■)(図b)。前記開口よりボロンの如きP型不
純物を拡散導入してソース、ドレインのP型5 領域3
、3’ を形成する(図c)。ついでSiO2膜を形成
(図c)したのちゲート部形成のためのSiO2膜の除
去を施す(図d)。前記SiO2膜除去部を主にSiO
2のゲート酸化膜4を形成する(図e)。次に前記ソー
ス、ドレイン領域3、、3’10の一部を露出するため
の開孔3a、3a’を設け(図f)たのち、配線金属層
のアルミニウム層5を被着し(図g)、さらにこれに蝕
刻を施すためのフォトレジスト層6を積層して被着す■
)(図れ)。前記レジスト層6を所定のパターンに形成
し(図15i)、これをマスクとして前記アルミニウム
層5にエッチングを施す(図j)。図jにおいて5’、
、、5”’は残留されたアルミニウム層で電極金属層と
なる。上記の如くなるMOSICにおいては各MOSク
0 トランジスタ間はSiO2膜2によつて離隔されて
いるので寄生モスの発生がある。Next, the SiO2 film 2 is etched to form openings 2a and 2a'.
■) (Figure b). P-type impurities such as boron are diffused into the openings to form source and drain P-type regions 3.
, 3' (Figure c). Next, after forming a SiO2 film (FIG. c), the SiO2 film is removed to form a gate portion (FIG. d). The SiO2 film removed portion is mainly made of SiO
A second gate oxide film 4 is formed (Fig. e). Next, after openings 3a and 3a' are formed to expose a part of the source and drain regions 3, 3' and 10 (Fig. f), an aluminum layer 5 as a wiring metal layer is deposited (Fig. g). ), and then a photoresist layer 6 for etching is further laminated and deposited.■
) (figure). The resist layer 6 is formed into a predetermined pattern (FIG. 15i), and using this as a mask, the aluminum layer 5 is etched (FIG. 15j). 5' in figure j,
, 5"' is the remaining aluminum layer and serves as an electrode metal layer. In the MOSIC as described above, since the MOS transistors are separated by the SiO2 film 2, parasitic moss is generated.
そのためにこの寄生モスの発生を防ぐためにSiO2膜
2の膜厚は1.5〜2.5μであり、ゲート酸化膜4は
200σAという小なる膜厚であるため、前記両SiO
2膜間25には大きな段差がある。(第2図)。こゝで
上面に層厚1.0〜1.5μのアルミニウム層被着を行
なつた場合、段差部は0.5μ以下となり、さらに加え
て次に施されるアルミニウム層のパターン蝕刻において
、段差部の感光性樹脂との密着が悪いた30めに蝕刻液
が浸入し第2図において点線で示す如き狭隘部5a〃を
生じ、該部にて断線を生ずるという重大な欠点がある。
本発明は上記従来の半導体素子の製造方法における欠点
を改良す■)ための半導体素子の製造方法35を提供す
るものである。Therefore, in order to prevent the generation of this parasitic moss, the thickness of the SiO2 film 2 is 1.5 to 2.5μ, and the gate oxide film 4 has a small thickness of 200σA.
There is a large step between the two films 25. (Figure 2). If an aluminum layer with a thickness of 1.0 to 1.5 μm is deposited on the top surface, the step portion will be less than 0.5 μm. Due to poor adhesion to the photosensitive resin in the 30th area, the etching solution penetrates, creating a narrowed area 5a as shown by the dotted line in FIG. 2, which has the serious disadvantage of causing a wire breakage.
The present invention provides a semiconductor device manufacturing method 35 for improving the drawbacks of the above-mentioned conventional semiconductor device manufacturing methods.
本発明にかゝる半導体素子の製造方法は配線層のアルミ
ニウム層の表層を、り2o3・ nll20層に変える
処理を施し、該層を素子における絶縁被膜として用いる
もので、配線層との密着が極めて良好に得られる上に強
固な電気絶縁性を示すこと、さらに該層をマスクとして
アルミニウム層の蝕刻を施すことを特徴とする。The method for manufacturing a semiconductor device according to the present invention involves processing the surface layer of the aluminum layer of the wiring layer to change it into a 2O3/NLL20 layer, and using this layer as an insulating coating in the device, so that it has good adhesion with the wiring layer. The aluminum layer is characterized in that it can be obtained very well and exhibits strong electrical insulation, and that the aluminum layer can be etched using this layer as a mask.
以下に本発明を一実施例の半導体素子の製造方法につき
図面を参照して詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings regarding one embodiment of a method for manufacturing a semiconductor device.
第3図aないしjに一例のMOSICの1部のMOSF
ETの製造工程を示す。図aにおける1はN型シリコン
基板でその1主面にSiO2膜2を形成する(図a)。
次に前記SiO2膜2に蝕刻を施して開口2a,2iを
設ける(図b)。前記開口よりボロンの如きP型不純物
を拡散導入してソース、ドレインのP型領域3,3/
を形成する(図c)。ついでSiO2膜を形成(図c)
したのちゲート部形成のためのSiO2膜の除去を施す
(図d)。前記SiO2膜除去部を主にSiO2のゲー
ト酸化膜4を形成する(図e)。次に前記ソース、ドレ
イン領域3,3′ の一部を露出するための開孔3a,
31を設け(図f)たのち、配線金属層のアルミ ニニ
ウム層15を被着する(図g)。次に沸騰水中にて約1
0分ないし20分間処理を施すことにより、前記アルミ
ニウム層15の露出表層にM2O3・NH2O嘗16を
形成し、さらにフオトレジスト層を被着し所定のパター
ン形状に蝕刻成形したフオ ニトレジスト層17を設け
る(図h)。上記ん03・NH2Oは処理温度80℃に
て,A2O3・3H20(バイヤーマイト)、100℃
にてA!203・1H20(ベーマイト)に形成される
。なお加圧水蒸気中にて加熱しても同様に形成される。
次に前記フオトレジスト層17をマスクとして前記M2
O3・NH2O層16を蝕刻溶除する(図1)。上記蝕
刻にはフツ化アンモニウム(NH4F)、酢酸(CH3
COOH)の混液を用いて好適する。次いで前記残留し
たHe2O3・NH2O層16′,16Z161をマス
クとしてアルミニウム層15を一例のリン酸(H3PO
4)、硝酸u込03)、酢酸(CH3COOH)、水の
混液でなる蝕刻液をもつて蝕刻溶除して夫々の回路パタ
ーン電極15′,15〃,15I′ が形成される(図
j)。上記の如く形成された本発明のMOSICにおけ
る配線アルミニウム層はその表層に形成したAl2O3
・NH2O層を備え、該層はアルミニウム層との密着は
フオトレジスト層との密着性よりもすぐれ、またAl2
O3・NH2O層とフオトレジスト層との密着性も良好
であるため、従来みられた段差部にまたがつて配設され
たアルミニウム層における狭隘部を生ぜず、艮質のMO
SlCを得ることができるという顕着な利点がある。Figures 3a to 3j show some MOSFs of an example MOSIC.
The manufacturing process of ET is shown. 1 in Figure a is an N-type silicon substrate, and a SiO2 film 2 is formed on its 1 main surface (Figure a).
Next, the SiO2 film 2 is etched to form openings 2a and 2i (FIG. b). A P-type impurity such as boron is diffused and introduced through the opening to form source and drain P-type regions 3, 3/3.
(Figure c). Then, a SiO2 film is formed (Figure c)
After that, the SiO2 film is removed to form a gate portion (Fig. d). A gate oxide film 4 of SiO2 is mainly formed in the portion where the SiO2 film has been removed (FIG. e). Next, an opening 3a for exposing a part of the source and drain regions 3, 3',
31 (Figure f), then an aluminum layer 15 as a wiring metal layer is deposited (Figure g). Next, in boiling water for about 1
By performing the treatment for 0 to 20 minutes, an M2O3.NH2O layer 16 is formed on the exposed surface layer of the aluminum layer 15, and a photoresist layer 17 is further deposited and formed by etching into a predetermined pattern shape. (Figure h). The above 03・NH2O is treated at a treatment temperature of 80℃, A2O3・3H20 (Bayermite), 100℃
At A! 203.1H20 (boehmite). Note that it can be formed in the same way even if it is heated in pressurized steam.
Next, using the photoresist layer 17 as a mask, the M2
The O3/NH2O layer 16 is etched away (FIG. 1). For the above etching, ammonium fluoride (NH4F), acetic acid (CH3
A mixture of COOH) is preferably used. Next, using the remaining He2O3/NH2O layers 16' and 16Z161 as a mask, the aluminum layer 15 is treated with an example of phosphoric acid (H3PO).
4) The circuit pattern electrodes 15', 15〃, and 15I' are formed by etching and dissolving using an etching solution consisting of a mixture of nitric acid (03), acetic acid (CH3COOH), and water (Fig. J). . The wiring aluminum layer in the MOSIC of the present invention formed as described above has Al2O3 formed on its surface layer.
・Equipped with an NH2O layer, which has better adhesion with the aluminum layer than with the photoresist layer, and which has an Al2
Since the adhesion between the O3/NH2O layer and the photoresist layer is also good, there is no narrow part in the aluminum layer disposed across the stepped part, which was seen in the past, and the MO
There is a distinct advantage that SlC can be obtained.
また本発明は実施が容易であるとともに半導体素子の加
熱が低温でよいので、拡散領域の形状に変型を与えるこ
とも少ないなどの利点もある。なお、第4図aには本発
明方法のアルミニウム層とAl2O3・NH2O層との
一部断面写真(倍率5000倍)にもとづく断面図と、
同図bに従来の方法におけるアルミニウム層とSiO2
層との一部の断面写真にもとづく断面図とを示し、両層
の密着性の相違が顕著に認められる。Further, the present invention is easy to implement, and the semiconductor element can be heated at a low temperature, so that the shape of the diffusion region is less likely to be deformed. In addition, FIG. 4a is a cross-sectional view based on a partial cross-sectional photograph (magnification: 5000 times) of an aluminum layer and an Al2O3/NH2O layer according to the method of the present invention,
Figure b shows the aluminum layer and SiO2 layer in the conventional method.
A cross-sectional view based on a cross-sectional photograph of a part of the layer and a cross-sectional view based on a cross-sectional photograph, and a remarkable difference in adhesion between the two layers can be seen.
即ち図bにおいて両層の間に蝕刻液の流入による不所望
のアルミニウム層の蝕刻が顕著なるに比し、図aの本発
明においてはこれが全く認められない。That is, while in Figure b, the undesired etching of the aluminum layer due to the inflow of the etching liquid between the two layers is noticeable, this is not observed at all in the present invention shown in Figure A.
第1図aないしjは従来の半導体素子の製造方法を工程
順に示すいづれも断面図、第2図は従来の半導体素子の
一部を示す斜視図、第3図aないしjは本発明の半導体
素子の製造方法を工程順に示すいづれも断面図、第4図
は本発明を説明するための断面写真にもとづく断面図で
、同図aは本発明同図bを従来のいづれも半導体素子を
示す。
15・・・・・・アルミニウム層(配線層)、16・・
・・・・Al2O3・NH2O層。1A to 1J are cross-sectional views showing a conventional semiconductor device manufacturing method in the order of steps, FIG. 2 is a perspective view showing a part of a conventional semiconductor device, and FIGS. 3A to 3J are semiconductors of the present invention 4 is a cross-sectional view based on a cross-sectional photograph for explaining the present invention, and FIG. . 15... Aluminum layer (wiring layer), 16...
...Al2O3/NH2O layer.
Claims (1)
工程と、次に前記素子を水または水蒸気中において加熱
しその表層部をAl_2O_3・nH_2O層とする工
程と、前記Al_2O_3・nH_2O層に蝕刻を施し
て所定のパターンに形成する工程と、前記所定パターン
のAl_2O_3・nH_2O層をマスクとしてアルミ
ニウム配線層に蝕刻を施す工程とを具備した半導体素子
の製造方法。1. A step of forming an aluminum wiring layer on the surface of a semiconductor element, a step of heating the element in water or steam to form an Al_2O_3/nH_2O layer on the surface layer, and etching the Al_2O_3/nH_2O layer. A method for manufacturing a semiconductor device, comprising the steps of forming a predetermined pattern, and etching an aluminum wiring layer using the predetermined pattern of the Al_2O_3·nH_2O layer as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9821176A JPS593853B2 (en) | 1976-08-19 | 1976-08-19 | Method for manufacturing semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9821176A JPS593853B2 (en) | 1976-08-19 | 1976-08-19 | Method for manufacturing semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5324287A JPS5324287A (en) | 1978-03-06 |
| JPS593853B2 true JPS593853B2 (en) | 1984-01-26 |
Family
ID=14213634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9821176A Expired JPS593853B2 (en) | 1976-08-19 | 1976-08-19 | Method for manufacturing semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS593853B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61137552U (en) * | 1985-02-18 | 1986-08-26 |
-
1976
- 1976-08-19 JP JP9821176A patent/JPS593853B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61137552U (en) * | 1985-02-18 | 1986-08-26 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5324287A (en) | 1978-03-06 |
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