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JPS5938759B2 - Manufacturing method for printed circuit boards - Google Patents
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JPS5938759B2 - Manufacturing method for printed circuit boards - Google Patents

Manufacturing method for printed circuit boards

Info

Publication number
JPS5938759B2
JPS5938759B2 JP56107102A JP10710281A JPS5938759B2 JP S5938759 B2 JPS5938759 B2 JP S5938759B2 JP 56107102 A JP56107102 A JP 56107102A JP 10710281 A JP10710281 A JP 10710281A JP S5938759 B2 JPS5938759 B2 JP S5938759B2
Authority
JP
Japan
Prior art keywords
circuit
hole
catalyst
copper foil
wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56107102A
Other languages
Japanese (ja)
Other versions
JPS589398A (en
Inventor
峰雄 川本
敢次 村上
洋一 松田
元世 和嶋
泰定 森下
鐘治 川窪
豊房 吉村
富雄 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56107102A priority Critical patent/JPS5938759B2/en
Publication of JPS589398A publication Critical patent/JPS589398A/en
Publication of JPS5938759B2 publication Critical patent/JPS5938759B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/428Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は銅箔回路と電子部品のリード線挿入用スルーホ
ール内壁とを電気的に接続したプリント回路用基板の製
造法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a printed circuit board in which a copper foil circuit and the inner wall of a through hole for inserting a lead wire of an electronic component are electrically connected.

〔発明の背景〕[Background of the invention]

従来、特開昭56−13794号公報により、銅貼り積
層板をエッチング法などによつて回路を形成し、さらに
、電子部品のリード線挿入用スルーホールにも化学めつ
きを行い、回路とスルーホール内とを電気的に接続し、
電子部品の半田付け信頼性および該部品の回路との導通
信頼性を高めたプリント回路用基板の製造法が提供され
た。
Conventionally, according to Japanese Unexamined Patent Publication No. 56-13794, a circuit was formed on a copper-clad laminate using an etching method, etc., and chemical plating was also applied to the through-holes for inserting lead wires in electronic components to form circuits and through-holes. Electrically connect the inside of the hall,
A method for manufacturing a printed circuit board is provided that improves soldering reliability of electronic components and reliability of conduction between the components and a circuit.

この方法によればスルーホール内壁に対し、化学めつき
膜を厚く形成することができ、これにより上記半田付け
信頼性および導通信頼性を向上させることができる。本
発明者らは上記方法をさらに簡略化することについて検
討し、本発明を見出した。
According to this method, it is possible to form a thick chemically plated film on the inner wall of the through hole, thereby improving the soldering reliability and conduction reliability. The present inventors studied ways to further simplify the above method and discovered the present invention.

〔発明の目的〕[Purpose of the invention]

本発明は電子部品のリード線挿入用スルーホール内壁へ
の厚付けめつきを達成することによりプリント回路用基
板の電子部品の半田付信頼性および該部品と回路との導
通信頼性を確保するとともに、能率的な方法により所期
のプリント回路用基板を製造しうる方法を提供すること
を目的とする。
The present invention achieves thick plating on the inner wall of a through hole for inserting a lead wire in an electronic component, thereby ensuring soldering reliability of the electronic component on a printed circuit board and continuity reliability between the component and the circuit. It is an object of the present invention to provide a method for manufacturing a desired printed circuit board using an efficient method.

〔発明の概要〕本発明のプリント回路用基板の製造法は
、下記(a),(b),(c)および(d)の工程、(
a)エツチングにより形成された銅箔回路および電子部
品のリード線挿入用スルーホールを有する基板を化学め
つき用触媒液で処理して少なくともスルーホール内壁に
化学めつき用触媒を付与する工程、(b)スルーホール
内壁の触媒を残し、少なくとも非回路部分に付着してい
る触媒を除去する工程、(c)形成された回路銅箔を完
全に露出し、回路側基板表面の非回路部分のみを化学め
つきに対するレジスト皮膜でスクリーン印刷法により被
覆する工程、(d)化学めつき処理によりスルーホール
内壁および銅箔回路上に化学めつき膜を析出させ回路と
スルーホール内壁とを電気的に接続する工程、を含むこ
とを特徴とする。
[Summary of the Invention] The method for manufacturing a printed circuit board of the present invention includes the following steps (a), (b), (c), and (d).
a) A step of treating a substrate having a copper foil circuit formed by etching and a through hole for inserting a lead wire of an electronic component with a chemical plating catalyst liquid to apply a chemical plating catalyst to at least the inner wall of the through hole; b) Removing the catalyst attached to at least the non-circuit part while leaving the catalyst on the inner wall of the through hole; (c) Completely exposing the formed circuit copper foil and removing only the non-circuit part on the surface of the circuit side board. (d) Depositing a chemical plating film on the inner wall of the through-hole and the copper foil circuit by chemical plating treatment to electrically connect the circuit and the inner wall of the through-hole. The method is characterized by including the step of:

本発明によれば化学めつき用触媒(以下、単に触媒と略
記する。
According to the present invention, a chemical plating catalyst (hereinafter simply abbreviated as catalyst) is used.

)液による処理の後非回路部分のみを化学めつきに対す
るレジスト皮膜(以下、単にレジスト皮膜と略記する。
)で被覆することにより、前記従来法に見られるアルカ
リ可溶性インクの使用およびそれに付随する幾つかの工
程を省略することができ、能率的で、生産性の向上を計
ることができる0しかも、化学めつき処理に際しては、
上記従来法と同様に、非回路部分のみがレジスト皮膜で
覆われているのでめつき膜はスルーホール内壁および回
路部分の双方に一体に析出するため、両者を電気的に完
全に接続することができる。しかも、レジスト皮膜は回
路上に全くかぶつていないので長時間化学めつき処理し
ても該レジスト皮膜がめつき液中に脱落し、めつき液の
寿命を短かくするなどの心配がないので膜厚を厚くする
ことが可能である。そして、厚いめつき膜の場合はピン
ホールがなく、半田付の際のブローホールあるいはフイ
レツト不足などの欠点が生じない0これらが相まつて電
子部品の半田付け信頼性および該部品と回路との導通信
頼性を高めることができる。次に本発明のプリント回路
用基板の製造法を図面により説明する。
) After treatment with a liquid, only the non-circuit portions are coated with a resist film against chemical plating (hereinafter simply referred to as a resist film).
), it is possible to omit the use of alkali-soluble ink and several accompanying steps found in the conventional method, and it is efficient and can improve productivity. When plating,
Similar to the above conventional method, since only the non-circuit parts are covered with the resist film, the plating film is deposited on both the through-hole inner wall and the circuit part, making it impossible to completely electrically connect the two. can. Moreover, since the resist film does not cover the circuit at all, there is no need to worry about the resist film falling into the plating solution and shortening the life of the plating solution even if the chemical plating process is performed for a long time. It is possible to increase the thickness. In addition, in the case of a thick plating film, there are no pinholes, and there are no defects such as blowholes or insufficient fillets during soldering. Together, these factors improve the soldering reliability of electronic components and the continuity between the component and the circuit. Reliability can be increased. Next, a method for manufacturing a printed circuit board according to the present invention will be explained with reference to the drawings.

第1図において、図A,cおよびdは前記工稙a),(
c)および(d)に対応し、各工程終了時点の状態を示
すものである。第1図aにおいて、1は銅箔で形成され
た回路で、樹脂積層板などの基板2に貼られている銅箔
をエツチングにより所定パターンに形成したものである
。3は電子部品のリード線を挿入するためのスルーホー
ルである。
In FIG. 1, diagrams A, c, and d are
It corresponds to c) and (d) and shows the state at the end of each step. In FIG. 1a, 1 is a circuit formed of copper foil, which is formed into a predetermined pattern by etching the copper foil pasted on a substrate 2 such as a resin laminate. 3 is a through hole for inserting a lead wire of an electronic component.

工程(a)では上記基板を触媒液に浸漬するなどの方法
によつて、スルーホール3の内壁を含む少なくとも回路
側表面に触媒4を付着せしめる。次に、第1図cに示す
ように、工程(c)により非回路部分5をレジスト皮膜
6で被覆し、これにより、スルーホール3の内壁および
回路銅箔1土にのみ化学めつき膜が析出するようにする
0なお、図cにおいてはレジスト皮膜6の下の触媒の図
示を省略した。しかる後工程(d)により化学めつきを
行い、上記部分にめつき膜を析出させる。これにより、
回路銅箔1とスルーホール内壁とはめつき膜7により電
気的に接続され、電子部品のリード線(図示せず)と回
路銅箔との導通信頼性および半田付け信頼性を向上でき
る。本発明において、触媒、レジスト皮膜、化学めつき
液およびそれらの処理方法は公知のもの、および方法を
採用することができる。
In step (a), the catalyst 4 is attached to at least the circuit side surface including the inner wall of the through hole 3 by a method such as immersing the substrate in a catalyst liquid. Next, as shown in FIG. 1c, the non-circuit portion 5 is covered with a resist film 6 in step (c), whereby a chemical plating film is formed only on the inner wall of the through hole 3 and the circuit copper foil 1. In addition, in FIG. c, illustration of the catalyst under the resist film 6 is omitted. In the subsequent step (d), chemical plating is performed to deposit a plating film on the above portion. This results in
The circuit copper foil 1 and the inner wall of the through hole are electrically connected by the plating film 7, thereby improving the continuity reliability and soldering reliability between the electronic component lead wire (not shown) and the circuit copper foil. In the present invention, known catalysts, resist films, chemical plating solutions, and treatment methods thereof can be used.

例えば特開昭56−13794号公報に記載されたもの
、および処理方法を用いることができる。本発明におい
て、触媒となる物質例えば塩化バラジウムなどの活性化
処理、即ち、還元処理はレジスト皮膜を被覆する工程(
c)の前後いずれの時点で行つてもよい。
For example, the method and treatment method described in JP-A-56-13794 can be used. In the present invention, the activation treatment of a catalyst such as palladium chloride, that is, the reduction treatment is the step of coating the resist film (
It may be carried out either before or after c).

本発明者らは研究によれば、銅箔回路間の距りが短かい
場合、即ち、配線密度を高くする場合はレススト皮膜処
理工程(c)を行う前にスルーホール内壁以外の触媒、
つまり非回路部分の触媒を実質的に除去することに回路
間の電流リークを抑えることができることを見出した。
According to the research conducted by the present inventors, when the distance between the copper foil circuits is short, that is, when the wiring density is to be increased, the catalyst on the surface other than the inner wall of the through-hole must be
In other words, it has been found that current leakage between circuits can be suppressed by substantially removing the catalyst in non-circuit portions.

このプリント回路用基板の製造法は、上記(a),(b
),(c)および(d)の工程を順次行うことを特徴と
する。本発明方法を第2図の実施例により説明する。
The method for manufacturing this printed circuit board includes the above (a) and (b).
), (c) and (d) are performed in sequence. The method of the present invention will be explained using the embodiment shown in FIG.

第2図において、図(a),(b),(c)および(d
)の工程は前記工程(a),(b),(c)および(d
)に対応し、各工程終了時点の状態を示す。ここで、工
程(a),(c)および(d)は前述の工程(a),(
c)および(d)の工程と全く同じである。したがつて
、この方法は、前述の(a),(c)および(d)の工
程を含む方法において、工稙a)と工程(c)の間に以
下に具体的に説明する工程(b)を追加したものである
。(b)の工程により少なくとも非回路部分5上の触媒
4を除去すること(もし、片側のみ回路を有するものに
あつては回路と反対側の面に付着している触媒4も除去
するのが望ましい。:により触媒による電流リーク作用
の問題がなくなり配線密度をより高めることができる。
触媒の除去はブラシなど機械的な方法によつて容易に行
うことができる。ブラシによる場合は銅箔回路上の触媒
も除去されるが、銅箔上には触媒が存在しなくとも化学
めつき膜の析出には何ら支障はない。触媒は必ずしも完
全に除去しなくとも所期の目的は達成される。ブラシ法
以外の除去方法としては例えば触媒除去液に浸漬する方
法がある。これは本発明者等の一部の者の発明になる特
開昭53−91381号あるいは特開昭53−1124
64号公報記載のものがある。例えば塩化第二鉄または
過硫酸アンモニウムを希塩酸等に溶解したものである。
触媒除去液に浸漬することにより、基板表面の触媒は実
質的に除去される。スルーホール内壁に付着している触
媒も一部除去される場合もあるが、めつきには何ら支障
を来たす心配はない。以上詳述した本発明のすべての方
法はミ基板の両面に回路を有する所謂両面回路基板の製
造にも適用できるものである。また、本発明を実施する
に当り、スルーホール内壁への触媒液の付着を確実に行
うために、予め該内壁を界面活性剤で処理しておいても
よい。
In Figure 2, Figures (a), (b), (c) and (d
) is the step (a), (b), (c) and (d)
) and shows the status at the end of each process. Here, steps (a), (c) and (d) are the aforementioned steps (a), (
This is exactly the same as steps c) and (d). Therefore, this method includes steps (a), (c), and (d) described above, and includes step (b), which will be specifically explained below, between step a) and step (c). ) is added. At least the catalyst 4 on the non-circuit portion 5 is removed by the step (b) (if the device has a circuit on only one side, it is recommended to also remove the catalyst 4 attached to the side opposite to the circuit). Desirable: This eliminates the problem of current leakage caused by the catalyst and allows higher wiring density.
The catalyst can be easily removed by a mechanical method such as a brush. When using a brush, the catalyst on the copper foil circuit is also removed, but even if the catalyst is not present on the copper foil, there is no problem in depositing the chemically plated film. The intended purpose is achieved even if the catalyst is not necessarily completely removed. As a removal method other than the brush method, for example, there is a method of immersion in a catalyst removal solution. This is the invention of JP-A-53-91381 or JP-A-53-1124, which was invented by some of the inventors.
There is one described in Publication No. 64. For example, ferric chloride or ammonium persulfate is dissolved in dilute hydrochloric acid or the like.
By immersing the substrate in the catalyst removal liquid, the catalyst on the surface of the substrate is substantially removed. Although some of the catalyst adhering to the inner wall of the through-hole may be removed, there is no concern that this will interfere with plating. All of the methods of the present invention detailed above can also be applied to the production of so-called double-sided circuit boards having circuits on both sides of the board. Further, in carrying out the present invention, the inner wall of the through hole may be treated with a surfactant in advance in order to ensure that the catalyst liquid adheres to the inner wall of the through hole.

さらに、化学めつき処理においても同様で、該内壁のね
れ性を良くするために界面活性剤で処理することができ
る。〔発明の実施例〕 以下、具体的な実施例をもつて本発明を詳述する。
Furthermore, the same applies to chemical plating treatment, in which the inner wall can be treated with a surfactant to improve its bendability. [Examples of the Invention] The present invention will be described in detail below using specific examples.

参考例 1 片面銅箔貼り積層板(日立化成社製 MCL一461F
35μm厚銅箔)を用い、銅箔上にスクリーン印刷法で
回路状にロジン変性マレン酸樹脂を主成分とする耐エツ
チング用インクを印刷し、塩化第二銅水溶液にて非回路
部分の銅箔を除去して水洗し、次いでNaOH水溶液で
上記インクを除去した。
Reference example 1 Single-sided copper foil laminate (manufactured by Hitachi Chemical Co., Ltd. MCL-461F
Using a 35 μm thick copper foil), print an etching-resistant ink mainly composed of rosin-modified maleic acid resin in a circuit shape on the copper foil using a screen printing method, and then print the non-circuit portions of the copper foil with a cupric chloride aqueous solution. was removed and washed with water, and then the above ink was removed with an aqueous NaOH solution.

水洗して風乾した後ドリルで必要個所にスルーホールを
穿設した。次に前記工程(a)として1770塩酸水溶
液に1分間浸漬した後、液化第一錫、塩化パラジウムお
よび塩酸とを主成分とする触媒液に10分間浸漬し、か
つ水洗した後塩酸を主成分とする液で活性化を行い、更
に水洗し、そして乾燥した。次に工程(c)として非回
路部分にエポキシ樹脂を主成分とするレジストインク(
東京応化工業社製 NTS−30)をスクリーン印刷法
で印刷し、12『C−20分で予備硬化した〇風燥した
後、回路のない裏面全面に上記レジストインクを印刷し
、全体を150℃−30分で硬化した。次に5%HZS
O4液で処理して水洗した後、工程(d)として下記組
成の化学銅めつき液に浸漬し、71℃で4時間めつきを
行い、スルーホール内壁および銅箔回路上に約9〜10
μm厚の銅めつき膜を形成し、片面スルーホールプリン
ト回路用基板を作成した。参考例 2 前記参考例1において、出発材料に両面銅箔貼り積層板
(日立化成社製 MCL−437F35μm厚銅箔)を
用いたこと、および化学銅めつき時間を10時間行つた
こと以外は、該参考例1と同様に作業を行い、スルーホ
ール内壁及び銅箔回路上に約27〜30μmの銅めつき
膜を形成し、両面スルーホールプリント回路用基板を作
成した。
After washing with water and air drying, through holes were drilled in the necessary locations. Next, in the step (a), after being immersed in a 1770 hydrochloric acid aqueous solution for 1 minute, immersed for 10 minutes in a catalyst solution containing liquefied stannous tin, palladium chloride, and hydrochloric acid as the main components, and after washing with water, Activation was performed with a solution containing water, followed by washing with water and drying. Next, in step (c), resist ink (based on epoxy resin) is applied to non-circuit areas.
NTS-30 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was printed using a screen printing method, and precured for 12"C for 20 minutes. After air drying, the above resist ink was printed on the entire back surface without circuits, and the whole was heated at 150℃. - Cured in 30 minutes. Next, 5% HZS
After treatment with O4 solution and washing with water, as step (d), it is immersed in a chemical copper plating solution with the following composition and plated at 71°C for 4 hours to coat the inner wall of the through hole and the copper foil circuit with approximately 9 to 10
A copper plating film with a thickness of μm was formed to create a single-sided through-hole printed circuit board. Reference Example 2 In Reference Example 1, except that a double-sided copper foil laminated board (MCL-437F 35 μm thick copper foil manufactured by Hitachi Chemical Co., Ltd.) was used as the starting material, and the chemical copper plating time was 10 hours. The work was carried out in the same manner as in Reference Example 1, and a copper plating film of approximately 27 to 30 μm was formed on the inner wall of the through hole and the copper foil circuit, thereby producing a double-sided through hole printed circuit board.

実施例 1 前記参考例1において、レジストインクを非回路部分に
印刷する前に、前記(b)工程として金属ロールブラシ
を用い、スルーホール内壁以外の基板表面に付着してい
る触媒、即ち、銅箔回路上および非回路部分に付着して
いる触媒の大部分を除去する工程を加えた。
Example 1 In Reference Example 1, before printing the resist ink on the non-circuit portion, a metal roll brush was used in the step (b) to remove the catalyst, i.e., copper, attached to the substrate surface other than the inner wall of the through hole. A step was added to remove most of the catalyst adhering to the foil circuit and non-circuit parts.

この他の工程は参考例1と同様に作業を行い、片面スル
ーホールプリント回路用基板および両面スルーホールプ
リント回路用基板を作成した。実施例 2 前記実施例1において、工程(b)として銅箔回路上お
よび非回路部分に付着している大部分の触媒を塩化第二
鉄0.1f!,3770塩酸100dおよび水900m
tからなる触媒除去液に15分間浸漬してスルーホール
内壁以外に付着している触媒を除去する方法に変更した
以外は実施例1と同様にして片面スルーホールプリント
回路用基板および両面スルーホールプリント回路用基板
を作成した。
The other steps were carried out in the same manner as in Reference Example 1 to produce a single-sided through-hole printed circuit board and a double-sided through-hole printed circuit board. Example 2 In Example 1, in step (b) most of the catalysts attached to the copper foil circuit and non-circuit parts were replaced with ferric chloride 0.1f! , 3770 hydrochloric acid 100d and water 900m
A single-sided through-hole printed circuit board and a double-sided through-hole printed circuit board were prepared in the same manner as in Example 1, except that the method was changed to remove the catalyst attached to areas other than the inner walls of the through holes by immersing them in a catalyst removal solution consisting of T for 15 minutes. A circuit board was created.

実施例 3前記参考例1の(a)工程における触媒付与
および水洗処理の後(b)工程として金属ロールブラシ
により回路側表面に付着している触媒を除去した。
Example 3 After the catalyst application and water washing treatment in step (a) of Reference Example 1, the catalyst adhering to the circuit side surface was removed in step (b) using a metal roll brush.

次に参考例1と同じ(c)工程の処理を行い、さらに触
媒活性化処理後員)程を実施し、片面スルーホールプリ
ント回路用基板を作成した。上記実施例1〜3で得られ
たプリント回路用基板のうち、片面スルーホールプリン
ト回路用基板について半田上がり性を調べた。
Next, the same process (c) as in Reference Example 1 was carried out, and the catalyst activation process (7) was further carried out to produce a single-sided through-hole printed circuit board. Among the printed circuit boards obtained in Examples 1 to 3 above, the solderability of single-sided through-hole printed circuit boards was investigated.

基板を約235℃の半田浴に5秒間フロートした結果、
スルーホール内の約75%が半田で満たされており、め
つき膜が厚いため基板からのガス成分の吹出しがなく半
田ブローホールが1個もないことが確かめられた。また
、電子部品のリード線を挿入し半田上げした結果フイレ
ツト不足は全くなかつた。一方、両面スルーホールプリ
ント回路用基板についてはヒートサイクル試験後の導通
抵抗の増加率を調べた。〔試験条件〕 260℃のグリセリン/2〜3秒間浸漬→室温/10秒
間放置→トリクレン/2〜3秒間浸漬を1サイクルとし
、これを20サイクル試験した。
As a result of floating the board in a solder bath at about 235°C for 5 seconds,
Approximately 75% of the through-holes were filled with solder, and because the plating film was thick, no gas components were blown out from the board, and it was confirmed that there were no solder blowholes. Also, as a result of inserting and soldering lead wires for electronic components, there was no shortage of fillets at all. On the other hand, for double-sided through-hole printed circuit boards, the rate of increase in conduction resistance after heat cycle tests was investigated. [Test conditions] One cycle consisted of immersion in glycerin at 260° C. for 2 to 3 seconds → room temperature/standing for 10 seconds → immersion in trichlene for 2 to 3 seconds, and 20 cycles of this were tested.

この結果、初期値に対する試験後の導通抵抗の増加率は
約470であり、実用上、無視できるものであつた0こ
のことはめつき膜が厚いためにヒートサイクル試験にお
いてもめつき膜にクラツクが入りにくいことを意味する
ものである。次に、(b)工程の有無における銅箔回路
後(線間)の絶縁抵抗を調べた。
As a result, the increase rate of the conduction resistance after the test with respect to the initial value was approximately 470, which was negligible in practical terms. This is because the plating film was thick and cracks occurred in the plating film during the heat cycle test. It means difficult. Next, the insulation resistance after the copper foil circuit (between the lines) was investigated with and without the step (b).

測定は銅箔回路巾(線巾)0.3關、回路間距離0.3
7n7!L1回路長さ(線長)50朋の回路を有する前
記各実施例で得られたプリント回路用基板を用い、回路
間に500Vの直流電圧を60秒間印加した後の線間の
絶縁抵抗を測定したものである。この結果、(b)工程
を入れなかつた参考例1および2のものは2.0×10
11Ωであるのに対し、(b)工程を加えた実施例1〜
3のものは4.2X1012Ωであつた。〔発明の効果
〕 以上本発明によれば触媒の非回路部残留に起因する電流
リークが防止され、高密度配線を可能にするという効果
がある。
Measurements were made with a copper foil circuit width (wire width) of 0.3 mm and a distance between circuits of 0.3 mm.
7n7! Using the printed circuit board obtained in each of the above examples having a circuit with an L1 circuit length (line length) of 50 mm, measure the insulation resistance between the lines after applying a DC voltage of 500 V between the circuits for 60 seconds. This is what I did. As a result, those of Reference Examples 1 and 2 without step (b) were 2.0×10
11 Ω, but Example 1 to which step (b) was added
The resistance of No. 3 was 4.2×10 12 Ω. [Effects of the Invention] According to the present invention, current leakage caused by catalyst remaining in non-circuit parts is prevented, and high-density wiring becomes possible.

実に工数低減やめつきレジスト脱落の防止という副次的
効果も得られる。
In fact, the secondary effects of reducing the number of man-hours and preventing the resist from falling off can also be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本発明を説明するためのプリント
回路用基板の製造工程ごとの基板状態を示す一部断面図
である。 1:銅箔回路、2:樹脂積層板、3:スルーホール、4
:触媒、5;非回路部分、6;レジスト皮膜、7:化学
めつき膜。
1 and 2 are partial cross-sectional views showing the state of the printed circuit board for each manufacturing process for explaining the present invention. 1: Copper foil circuit, 2: Resin laminate, 3: Through hole, 4
: catalyst, 5; non-circuit portion, 6; resist film, 7: chemically plated film.

Claims (1)

【特許請求の範囲】 1 次の各工程を順次含むことを特徴とするプリント回
路用基板の製造法。 (a)エッチングにより形成された銅箔回路および電子
部品のリード線挿入用スルーホールを有する基板を化学
めつき用触媒液で処理して少なくともスルーホール内壁
に化学めつき用触媒を付与する工程、(b)スルーホー
ル内壁の触媒を残し、少なくとも非回路部分に付着して
いる触媒を除去する工程、(c)形成された銅箔回路を
完全に露出し、エッチングで露出した回路側基板表面の
みをスクリーン印刷法により化学めつきに対するレジス
ト皮膜で被覆する工程、および(d)スルーホール内壁
および銅箔回路上に化学めつき膜を析出させ、回路とス
ルーホール内壁とを電気的に接続する工程。
[Scope of Claims] 1. A method for manufacturing a printed circuit board, characterized by sequentially including the following steps. (a) a step of applying a chemical plating catalyst to at least the inner wall of the through hole by treating a substrate having a copper foil circuit formed by etching and a through hole for inserting a lead wire of an electronic component with a chemical plating catalyst liquid; (b) leaving the catalyst on the inner wall of the through hole and removing the catalyst attached to at least the non-circuit portion, (c) completely exposing the formed copper foil circuit, only the surface of the circuit side board exposed by etching (d) Depositing a chemical plating film on the inner wall of the through hole and the copper foil circuit, and electrically connecting the circuit and the inner wall of the through hole. .
JP56107102A 1981-07-10 1981-07-10 Manufacturing method for printed circuit boards Expired JPS5938759B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56107102A JPS5938759B2 (en) 1981-07-10 1981-07-10 Manufacturing method for printed circuit boards

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56107102A JPS5938759B2 (en) 1981-07-10 1981-07-10 Manufacturing method for printed circuit boards

Publications (2)

Publication Number Publication Date
JPS589398A JPS589398A (en) 1983-01-19
JPS5938759B2 true JPS5938759B2 (en) 1984-09-19

Family

ID=14450504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56107102A Expired JPS5938759B2 (en) 1981-07-10 1981-07-10 Manufacturing method for printed circuit boards

Country Status (1)

Country Link
JP (1) JPS5938759B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60213085A (en) * 1984-04-09 1985-10-25 株式会社 大洋電機研究所 Printed circuit board by electrically plating method and method of producing same
JPS6242493A (en) * 1985-08-19 1987-02-24 東京プリント工業株式会社 Manufacture of printed wiring board

Also Published As

Publication number Publication date
JPS589398A (en) 1983-01-19

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