JPS5939052B2 - Information processing device and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus and method, and specifically to a failure detection and method having an address degeneration function.

In recent years, as systems using information processing equipment have become more and more sophisticated, the impact of the failure of information processing equipment has become almost greater, and higher reliability of information processing equipment has been required, and this has not been achieved. ing. However, no matter how high reliability advances, it is impossible to completely reduce the probability of failure to zero. In cases where particularly high reliability is required, processing units may be duplicated to perform the same work. By comparing the outputs of the systems, if a failure should occur during system operation, the failure would be immediately detected and measures taken to deal with the failure. One of the methods for detecting failures during system operation that can be realized at a lower cost is the execution of a test program.

Among them, there are those that use the main memory as a storage location for the test program and execute the test program as one job, and those that store the test program in a storage device other than the main memory and run it at regular intervals. In some cases, the test program was executed by interrupting the processing of instructions. However, one of the disadvantages of storing test programs in the main memory is that the test programs temporarily reduce the storage capacity available to the user of the information processing device. Testing using microprograms is often performed to ensure that the program works properly.

Furthermore, these methods using test programs have drawbacks such as requiring the user to temporarily suspend program processing in order to execute the test program. In order to solve these shortcomings, we have developed a method that uses microprograms to perform tests using the idle state of information processing equipment. In other words, it is possible to detect failures without consuming information processing materials that should be used by users for testing. Japanese Patent Application No. 52-28433 (JP 53-113447
No.).

This application relates to an improvement in the test execution method using such a microprogram, and will be clarified based on the purpose of this application. Here, an inspection method using a conventional test program will be briefly described.

First, save the register memory to be tested. Main memory can be used as this save area, but when a test program is stored in a storage device other than main memory and tests are executed at the microinstruction level, scratchpad memory is often used as this save area. .
In the latter case, the number of registers and memories to be saved is reduced by selecting a point in time to execute the test after completing the processing of one instruction and before starting the processing of the next instruction. (Between instructions, only the so-called software visible registers determine the internal state of the information processing device.The contents of other control flip-flops and working registers always take a constant value at that point, or they (The contents have no effect on the subsequent operation of the information processing device.) However, since there is a limit to the number of words in scratchpad memory, the contents of main memory cannot be saved; Select one or several words as the test target in advance, and save only that one or several words, or exclude parts related to main memory from the test, or use hardware to interface with the main memory during the test. What about the contents of main memory so that Ace doesn't move? He took measures to protect them.

If the contents of the main memory are protected, when you try to read the main memory, depending on the method of memory protection,
stomach. Something that causes an error. Something that makes it appear as if a fixed value (for example, zero) has been read.c. In some cases, the last read or written content was read out.

However, the disadvantage of the above-mentioned method of saving one or more specific words in the main memory is that it is not possible to test by setting the address freely, so it is not possible to perform tests sufficiently. .

If you try to test without using the main memory, parts of the main memory that cannot be tested will remain. In the case of information processing equipment where every detail of the circuit is controlled by microprograms, this untestable part can be made quite small, so there is not much of a problem. When accessing a device, this method tends to leave a large portion untested, which is a problem. Furthermore, the problem with disabling the interface is that ``In order to test each part within the information processing device, it is necessary to ensure that the main memory is operating normally and reading or writing any data is not possible. The problem lies in the fact that it is not possible to freely simulate the state in which one is doing something.

Next, it is necessary to set the test data before testing.

By executing the operation ``adding the contents of a certain register and the contents of address 100 in main memory'' and examining the results, it is possible to confirm that the adder, operand register, and their peripheral circuits operate correctly. Taking the target test as an example, the registers and main memory 10
The contents of address 0 must be set to some predetermined value prior to testing.

Conventionally, test data was written to such addresses prior to testing in the test program after the contents were saved. On the other hand, a memory such as a buffer memory which has a copy of the contents of the main memory will logically operate correctly if its contents are destroyed during the test and the memory contents are left empty.

However, this is not preferable because it reduces the efficiency of the user's information processing performed after the test, and conventionally, the data has been saved together with the main memory. The present invention has been made in view of the above drawbacks, and it is an object of the present invention to provide an information processing device that reduces the storage capacity of various memories required for failure detection tests performed during system operation and shortens the time required for testing. purpose.

That is, before and after failure detection, the continuity of the internal state of the device visible to the user is maintained, and the internal state of the device required for testing is initialized (setting of test data).
The present invention provides an improved means for performing the following steps. Another purpose is to efficiently fulfill the two functions of protecting data in the main memory required for testing during system operation and setting test data in the main memory used for testing. The goal is to provide the following.

Another purpose is to unify and simplify the handling of buffer memory, paging associative memory, etc. during testing when a copy of part of the information in main memory is available, and to prevent a decline in information processing ability. The objective is to provide an improved means that does not involve In connection with the above, another object of the present invention is to provide means for simplifying testing of a processing circuit for abnormal operation. Hereinafter, the present invention will be explained in detail using the drawings.

Figure 1 shows the central processing unit (hereinafter referred to as CP) used in the present invention.
FIG.

In the figure, an instruction processing unit 1 sequentially extracts and decodes instructions to be executed, and causes an address calculation unit 2 to calculate operand addresses.

The operand address is given to the main memory interface unit 3, and the operand is read and placed in the operand register RD in the arithmetic unit 4. The internal structure of the arithmetic unit 4 is not shown because it is not directly related to the present invention. However, in order to symbolically represent important data input and output of the arithmetic unit 4, only the operand register RD and the arithmetic logic unit ALU are shown. On the other hand, the main memory interface unit 3 may or may not have a buffer memory 11.

The main memory interface unit 3 also has a portion called a port 12 for connection to the main memory device 5. There is one port 12 for each main storage device 5, and the number is not limited to two. In addition, in reality, there are main memory access requests from other CPUs in channel devices and multiprocessor configuration systems, so a system control unit is placed between the port 12 and the main memory device 5 to handle requests from each device. multiplexing of main memory access requests. The boat 12 actually exists in correspondence with the system control unit. however,
The system control unit is not shown since it is not directly relevant to the present invention. Since the CPU shown in FIG. 1 uses a microprogram control system, there is a microinstruction register 7 that receives microinstructions from the control storage unit 6, which controls each unit in the CPU.

However, the instruction word processing unit, address calculation unit 2,
Main memory interface unit 3 and other units often perform routine processing, so unless exceptional processing is requested, the microprogram gives a command to start work as a large unit, and then the hardware of each unit is It is designed to operate according to control logic. The read address of the mountain control unit 6 is given from the sequence control unit 8. The sequence control unit 8 is given micro-instructions and operation results, and has a function of sequentially giving the read address of the control memory unit 6 to the control memory unit 6 so that the microprogram is executed correctly and as scheduled. . In addition, the sequence control unit 8
is given the instruction code of the next instruction to be executed from instruction unit 1, and when the microprogram for processing the current instruction has finished executing, it has the function of starting execution of the microprogram corresponding to that instruction code. . Tests carried out during system operation are also started by this sequence control unit. FIG. 2 shows in detail the portion of port 0 in the main memory interface unit 3 in FIG.
Respective registers 21, 22, 23 of data are shown.

In the figure, commands and addresses can only be transferred in one direction, and only data can be transferred in both directions. Further, the port 12 and the main storage device 5 are connected by a bidirectional transmission path. When writing to the main memory 5, the data sent from the arithmetic unit 4 is put into the data register 23, and when reading from the main memory 5, the data is sent from the main memory 5 via the bidirectional transmission path. Data register 2 sets the received data to data register 23.
A selector 24 is placed in front of the main memory interface unit 3, and a port control circuit (described later) in the main memory interface unit 3.
along with registers in other ports. Further, operation commands to the main memory device 5 and response signals from the main memory device 5 to the commands are sent and received via the port 12. Here, the operation command is a control signal required for transferring commands to all main storage devices 5, and without this signal, the main storage device cannot operate.

Note that 24, 25, 26, and 27 are drivers, 28 is a receiver, and port 1 is not shown, but port 0
is exactly the same. FIG. 3 is a block diagram showing the general configuration inside the main memory interface unit 3.

When a memory access command for reading an operand is given, an address comparison circuit (not shown) checks whether the corresponding address has been copied to the buffer memory 11 or not. If the addresses match, a copy of the contents of the corresponding address stored in the buffer memory 11VC is immediately sent to the arithmetic unit 4 as an operand, and the buffer memory control circuit 32 does not send any command to the port control circuit 31. . If the addresses do not match, no match signal is sent from the address comparison circuit, so the buffer memory leg circuit 32 sends a miss-hit H signal to the port control circuit 31. The corresponding address of the main memory device 5 is read, and when the data reading is completed, the port control circuit 31 provides a block load signal to the buffer memory control circuit 32. The buffer memory control circuit 32 passes the read data to the arithmetic unit 4 as an operand, and also writes the data to the buffer memory 11.
In addition, in the case of a mishit H, it takes time until the operand is actually obtained, so a stop signal is sent from the port control circuit 31 to the outside (clock unit), and during that time the CPU
The operation of the remaining part of the operand is stopped, and the operand is stored in main memory 5.
It has the ability to be read from. On the other hand, the buffer memory control device 32 has a mode register (not shown, but this register determines the operating mode of the CPU, and can be read and written by machine language instructions).

) to buffer memory use prohibition signal (use prohibition mode)
is sent, and when this signal is output, the buffer memory control circuit 32 does not change the internal state of the buffer memory 11 at all, and sends a bypass signal of the buffer memory 11 to the port control circuit 31, indicating that the buffer memory is present. The port control circuit 31 is made to operate in exactly the same way as when it is not used. Note that control signals are transmitted and received between the port control circuit 31 and each port 12 for each port.

This concludes the general description of the CPU used in the embodiments of the present invention, and the embodiments of the present invention will be described below.

First, I will give an overview. The present invention is to protect the contents of the main memory by hardware by operating as if all addresses in the main memory had been degenerated into data registers in the port, and to carry out a series of tests. The main idea is to set the test data required in advance in order to perform the test just once in the data register, and the test data can be operated and tested as if any address was freely accessed. More precisely, all addresses of the main memory device accessed through port n are degenerated into data registers within that port n.

Buffer memory, which is provided to keep a copy of the currently frequently accessed part of the main memory so that subsequent accesses to that part can be processed at high speed, is similar to main memory. data must be protected.

By forcing this mode as if it were a buffer memory use prohibition mode, the data in the buffer memory can be easily protected. By setting the buffer memory to disable mode, it becomes impossible to test the buffer memory itself, but the memory elements that occupy the majority of the entire buffer memory (as is well known, the directory area, data area, and control club area) )
Since the parity has been checked, the memory element portion is not subject to failure detection in this test in the embodiment of the present invention. Since the remaining buffer memory-related logic is relatively small, the method of reading an address that happens to already be in the buffer memory to confirm a match using the conventional technique and the instruction to be executed are not required in the embodiment of the present invention. The required failure can be detected by checking the corresponding buffer memory directory using the fact that the number is always stored in the buffer memory, and by testing by means of confirming that the number is in the directory. We are getting a detection rate. Depending on the degree of failure coverage required, this may be simple, or may require duplication of control-related logic. Then the fourth
Embodiments of the present invention will be described in detail with reference to the drawings.

First, an address reduction flip-flop 41 is provided, and in order to be able to set/reset freely in a test program, the address reduction flip-flop 41 is set/reset under the control of a microinstruction.

Alternatively, it may be set at the start of the test program and set at the end of the test program execution. The output of the address degeneracy flip-flop 41 is connected to an OR gate 4 which is logically ORed with the buffer memory use prohibition mode signal.
2 and the inverter 43. The output of the OR gate 42 is then applied to the buffer memory control circuit 44 in place of the buffer memory use prohibition mode signal. AND gates 46, 47, and 48 are inserted into each of the stop signal going from the port control circuit 45 to the clock unit and the operation command signal going to port O and port 1. The output of the inverter 43 is applied to the input. Hereinafter, the operation of the embodiment of the present invention will be explained in detail.

First, it is clear that the circuit of FIG. 4 works exactly the same as the circuit of FIG. 3 when address degeneration flip-flop 41 is reset.

Next, the operation when the address degeneration flip-flop 41 is set will be explained.

First, due to the action of the OR gate 42, the buffer control circuit 44 operates as if the buffer memory use prohibition mode signal had become "1", so that the contents of the buffer memory 11 are not changed at all as described above, and the bypass signal is sent to the port control circuit 45. Therefore, every time a memory access command is issued, it is as if the buffer memory 1
Port control circuit 45 as if 1 were not present.
works. Now, the memory access command is sent to main memory 5.
If the instruction is to write data to address A, the port control circuit 45 selects a port by looking at some bits of the given address. Assume that port 0 is selected. A command, address, and data are loaded into the command register 21, address register 22, and data register 23 of port 0, respectively, by the function of a port register control signal sent from the port control circuit 45. Subsequently, the port control circuit 45 attempts to send an operation command to the main storage device 5 via the port 012. However, since the output of the inverter 43 is "O", the operation command is not sent to the port 12 due to the action of the AND gates 47 and 48. That is, since the address degeneration flip-flop 41 is set, even if a write command to the main storage device 5 is issued, writing will not actually be performed. means that the content is protected. The data sent to be written to address A remains in the data register 23 of port 012. Next, it is assumed that a memory access command for reading an operand from address B is given, and that address B is also an address to be accessed via port 012 like address A.

Since the bypass signal is sent from the buffer memory control circuit 44, the port control circuit 45
The command and address are respectively loaded into the command register 21 and address register 22 of. It then attempts to send an operation command to the main memory device 5 and a stop signal to a clock unit (not shown). However, since the output of the inverter 43 is ``0'', neither a stop signal nor an operation command is actually sent.In normal conditions, that is, when the address degeneration flip-flop 41 is not set, the The storage device 5 operates, reads out the contents of address B, puts it on the data line, and sends it to the port 12, sends a response signal, sets the data in the data register 23 in the port, and issues the stop signal that had been issued until then. This series of operations continues, but since the address degeneration flip-flop 41 is set, the CPU proceeds to the next operation without performing this series of operations. This means that the given read command is executed at time zero (the time during which the stop signal is sent to the clock unit is zero), and the read data is actually originally stored in the data register 23 in port 12. It means that it operated as if it were That is,
In this example, the data read from address B is actually the data previously written to address A.

Therefore, addresses become meaningless and all addresses are port 1.
The data register 23 operates as if it had been degenerated into the data register 23 in the data register 23. This concludes the general description of the present invention, and next, a method for creating a test program that effectively utilizes the present invention will be described.

The present invention is used in a test program executed for the purpose of fault detection during system operation, and its main purpose is to reduce the capacity of the scratchpad memory used by the test program and shorten the time required to execute the test program. shall be.

It is also an object of the present invention to enable effective use in information processing apparatuses in which main memory access-related logic is hard-wired controlled. In light of such a purpose, the data in the main memory device is protected by hardware using the present invention, and the known data required for testing is limited to only the first of a series of tests. Initialize the data register 23 by writing known data to the main memory in the program, and after that, try to use the data written as a result of the previous test as data for the next test. It is best to do so.

If there is a failure in the part operated during the previous test, the data written to the main memory (actually to the data register in the port) as a result of that test will often be incorrect.

The results are then used as data for the next test, resulting in the next test performing haphazard processing based on incorrect data. However, as long as the purpose of the test is only to know whether a fault exists, and the save area of the software visible register is reliably protected,
This "random" processing has virtually no effect and the purpose of the test is achieved.

Note that in this embodiment, commands for peripheral devices are also sent from the CPU through port 12, and actually
Commands are sent from a system control unit (not shown) located between the main storage device 2 and the main storage device 5 to peripheral devices via a channel device.

Therefore, by preventing the operation command from being issued using the AND gates 47 and 48 in FIG. 4, it is possible to prevent the command from being sent to the main storage device, and also prevent the command from being sent to the peripheral devices. It's getting old. When the present invention is applied to a computer having a structure in which a circuit that sends commands to peripheral devices exists independently, the AND gate 47 is also applied to that circuit.
, 48 must be provided. In addition, in the embodiment of the present invention, it is impossible to stop the information processing device itself from the microprogram, and as will be described later, the exception handling sequence associated with abnormality detection is beyond a certain point where it can be turned back. We are taking measures to prevent it from progressing.

However, regardless of the above, if necessary, it is easy to create a test program that stores known test data in the data register before starting each test. When multiple operands are required in a single, indivisible test, it is not possible to freely preset each operand individually, and the test can be run, for example, in single-step mode. At the same time, it is necessary to sequentially write the test data to be read next into the data register according to the progress of the test. Another disadvantage of using the results of a previous test as data for the next test is that each test is not independent, so the test results are not independent. The two points are that it is extremely difficult, and that when a test program or the hardware to be tested is changed, a single change has a wide-ranging effect. Because of these shortcomings, conventional test programs have been designed so that the previous test and the next test are as independent as possible. However, in the case of tests performed while the system is running, it is necessary to minimize the storage capacity for storing the test program, and one way to do this is to reduce the data storage area for the test and transfer the results of the previous test to the next test. It is an effective method to use it. The above two drawbacks can be overcome by employing recently developed failure simulation techniques when designing test programs. It is recommended that you design and change the test program as follows.

First, in order to use the results of the previous test as data for the next test, it is necessary to clarify the test target for each test and the conditions that the test input data must have, so that humans can understand the basic connections of the entire test. design, and also create test input data for the first test. By running it through a fault simulator, you can find out which faults were detected in which tests, what data was written to registers, memory, etc. as a result of each test, and was passed on to the next test. It becomes clear how many failures have gone undetected. Based on this, the designer changes the test program to rewrite the contents of a small number of registers and memory between tests, and then reworks the test program so that subsequent tests are as originally planned. And,
Further tests are added to ensure that the detected failure rate exceeds the required level.

In this way, test programs can be designed with the help of a failure simulator. When changes are made to the test program or hardware, first try making the changes on a fault simulator, and then look at the output of the fault simulator to see how the changes affect which tests and which faults become undetectable. After knowing this, the designer can process the improvements in the same way as the improvements made at the time of designing the test program.

The disadvantages of using the results of previous tests as data for subsequent tests become less of a problem by using a failure simulator to design and maintain test programs.

Furthermore, in the present invention, address information is ignored as a result (bits used for port selection are not ignored), so when creating a test program, test the data path of address information using the conventional method. It is necessary to keep it.

Next, a case where the information processing apparatus has a virtual addressing function and an address calculation unit includes an associative memory for converting virtual addresses to real addresses will be described.

This associative memory is also essentially a copy of the virtual address to real address conversion table stored in the main memory.

Because the hardware uses associative memory to enable high-speed access, the = part of the virtual address to real address conversion table in the main memory may not be extracted as is, but may be stored with some modification. However, it is essentially a copy, just as buffer memory stores a copy of a portion of main memory with respect to commands and data. Therefore, if an associative memory exists, basically, in the same way as buffer memory, when the address degenerate flip-flop is set, the associative memory is forced into a disabled state so that the contents of the associative memory are not updated at all. good. As a result, when virtual address to real address translation is required, the address calculation unit accesses the virtual address to real address translation table stored in main memory to perform the necessary address translation work.

Then, the main memory access is degenerated to the data register in the boat by the function of the address degeneration flip-flop in the present invention.

In the case of the embodiment of the present invention, when address translation starts, the operations of other units are stopped, only the address translation work is performed, and data is read from the main memory multiple times during the address translation process, so this part is not tested. In the future, by operating the address translation mechanism in single-step mode, a test program can intervene between accesses to main memory and rewrite data registers in ports using diagnostic commands. It is possible to test by reading out a conversion table with arbitrary contents. Next, a test of the abnormality detection means will be described with reference to FIG.

For example, in the case of a main memory device, the information processing device according to the embodiment of the present invention has a function to send data with a parity error to the main memory, so it degenerates addresses and uses that function when testing. The data is written to the data register of the port, and then read out to cause the parity checker 51 to detect a parity error.

Then, one of the abnormality detection flip-flops 52, FFTi, is set to test whether the parity check has been reliably detected. Such an abnormality detection flip-flop 52
are grouped according to the nature of the abnormality and are designed to start the abnormality handling procedure, but just before actually starting the abnormality handling procedure, the activation signal is sent by the output of the inverter 43 in Fig. 4. A prohibition condition is applied by the AND circuit 55 to prevent the abnormality detection procedure from being activated in the address degeneration mode, thereby facilitating testing of the abnormality detection means in the test program.

In the embodiment of the present invention, the abnormality detection flip-flop FFTO-
Since the flip-flop FFTn is made to look like one (n+1) bit register, it is easy to test the results of abnormality detection. Additionally, items related to overall system control and abnormality detection, such as abnormalities in the input power supply of the information processing system, timer overflows, and input/output device operation completion interrupts, are grouped into separate groups. In this case, inhibition by the address degeneration flip-flop 41 as in the AND circuit 55 of FIG. 5 is not performed.

In the embodiment of the present invention, there is a data register in the port, so all addresses in the main memory are reduced to that data register, but it is possible to have only one data register in the main memory interface unit instead of in the port. It may be used when applied to an information processing device.

Alternatively, a new one may be established. Further, in FIG. 5, 53 and 54 are OR gates, and 55 is an AND gate. As explained above, according to the present invention, there is no need to save data in the main memory device for testing, and therefore no save area is required, and there is no need for time and procedures for saving and restoring data. It takes less time and requires less scratch pad memory and memory capacity for test program storage for testing.

Furthermore, since the data in the buffer memory etc. is not destroyed by the test, the information processing efficiency of the user will not be reduced after the test is completed. On the other hand, the parts that cannot be tested by implementing the present invention are the main memory, buffer memory,
Although they are associative memories, most of them are made up of memory elements, and since the parity can be easily checked, the failure detection rate does not decrease much.

Further, since the state of the address degeneration flip-flop according to the present invention can be controlled by a test program, conventional test methods can also be used in the test program. Furthermore, since the addresses are degenerate, there is no need to write data for the test in advance to the address to be read by the test before the test is performed, and the results of the previous test can be used as data for the next test.

This means that there is no need to store test data or set that data, which reduces the time required for testing and requires less memory capacity for storing test programs. This effect is produced. Further, since the address and data can be separated, the test of the address generation circuit and the test of the arithmetic unit independent of the test can be performed simultaneously.

Furthermore, since the test is performed by operating the main memory as if the access time is zero, various advantages such as a reduction in the time required to execute the test are produced.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration example of an information processing device used in an embodiment of the present invention, FIG. 2 is a block diagram of a port portion in FIG. 1, and FIGS. 3 and 4 are main memory interfaces in FIG. 1. FIG. 5 is an example of an abnormality detection circuit. 1... Instruction word processing unit, 2... Address calculation unit, 3... Main memory interface unit, 4... Arithmetic unit, 5...
...Main memory, 6...Control memory unit, 7...Microinstruction register, 8...
・Sequence control unit, 11...Buffer memory, 12...Port, 21...Command register, 22...Address register,
23...Data register, 24, 25, 26,
27... Driver, 28... Receiver 31, 45...- Port control circuit, 32, 44
...Buffer memory control circuit, 41...
・Address degeneracy flip-flop, 42, 53, 54・
...or gate, 43...inverter,
46, 47, 48, 55...and gate, 5
1...Parity check, 52...Flip flop.

Claims (1)

[Claims] 1. A main memory, an address register that holds an address of the main memory, a data register that holds read data or write data of the main memory, and a main memory that sends a read command or a write command to the main memory. a data processing section that performs read or write access to the main memory using the address register and data register; means for setting a processing mode of the data processing section to a specific mode; and a means for setting the processing mode of the data processing section to the specific mode. When set,
For the write access, simply setting data in the data register prohibits sending the write command to the main memory, and for the read access, the contents set in the data register are read data. The main memory is provided with a control means for prohibiting sending the read command, and the data processing section set to the specific mode detects a failure in the information processing apparatus using the control means. An information processing device characterized by: 2. In an information processing device having a second memory that stores a copy of a part of the contents of the main memory, in response to the read or write command of the data processing unit set to the specific mode, the second memory Claim 1 characterized in that the content of the memory is controlled so as not to change.
The information processing device described in the section. 3. A main memory, an address register that holds the address of this main memory, a data register that holds read data or write data of the main memory, and the address register and data register that send a read command or a write command to the main memory. a data processing unit that performs read or write access to the main memory using a data processing unit; means for setting a processing mode of the data processing unit to a specific mode; and when the data processing unit is set to the specific mode;
For the write access, simply setting data in the data register prohibits sending the write command to the main memory, and for the read access, the contents set in the data register are read data. The main memory is provided with a control means for prohibiting the sending of the read command, and is made up of a plurality of individual tests, and is executed by a fault detection test program in which the plurality of individual tests are sequentially executed in series in time. In order to detect a failure in the information processing device, the data processing unit is set to a specific mode, the preceding individual test is executed, and data to be written to the main memory is set in the data register;
An information processing method characterized in that the subsequent individual test is executed and data set in the data register is used as output data.