JPS5939908B2 - Transistor manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a transistor that can prevent deterioration of direct current amplification factor hFE during actual operation.

When a transistor is actually operated, its direct current amplification factor hFE often deteriorates.

Such deterioration of hFE is particularly likely to occur during actual operation in a small current region, and when hFE deterioration occurs, a circuit configured using this transistor will not be able to perform the intended operation. Incidentally, the occurrence of the above-mentioned deterioration of hFE is mainly brought about by the surface condition of the transistor. This is clear from the fact that things that have deteriorated temporarily recover to their normal state.

However, by performing such heat treatment, hF
Even in a transistor whose E has been restored, its hFE deteriorates again during a life test or during actual operation. 15 The present invention:
This was done based on the confirmation that the above deterioration of hFE is affected by the processing conditions before electrode formation, especially the atmosphere during emitter diffusion and the slow cooling rate after emitter diffusion processing. The process is divided into two steps: in the 120th step, an insulating film with the minimum thickness necessary to separate the electrodes is formed on the semiconductor substrate, and in the second step, an emitter diffusion treatment is performed in an inert atmosphere, and then, It is characterized in that the cooling treatment is performed at a cooling rate selected within the range of 0.5 to 5°C per minute.

25 That is, when heat treatment for emitter diffusion is performed in an inert atmosphere, the insulating film (
The effect of reducing the fixed charge (Qss) introduced into the SiO2 film) was achieved, and the slow cooling selected at a cooling rate of 0.5 to 50C had the effect of preventing the occurrence of lattice defects. It is played.

Incidentally, fixed charges (Qss) and lattice defects are both related to the surface state, and these contribute to surface recombination in a small current region. Therefore, if the introduction of fixed charges into the SiO2 film is reduced35 and the generation of lattice defects is prevented as described above, it is possible to prevent the deterioration of hFE. Next, the manufacturing method of the present invention will be explained in detail using an example of manufacturing a triple diffusion type NPN transistor. FIGS. 1a to 1e are manufacturing process diagrams showing the process of manufacturing a triple diffusion type NPN transistor by the manufacturing method of the present invention. First, phosphorus is diffused into an N type silicon substrate 1 to form an N form. Next, a window for base diffusion is formed in the silicon dioxide film formed on the surface of the N-type silicon substrate 1, and boron is diffused through this window to form a P-type base region. FIG. 1b shows the state after such processing, in which 3 is a silicon dioxide film and 4 is a P-type base region. A window for emitter diffusion is bored in the silicon dioxide film on the silicon substrate in which the base region has been formed in this way, and then phosphorus is deposited to form a phosphorus layer 5 as shown in FIG. 1C. The steps up to the above are the normal manufacturing steps of a triple diffusion type transistor. Next, the deposited phosphorus is diffused to form an N-type emitter region, and here a two-step process, which is a feature of the present invention, is performed.

The first step is to form a silicon dioxide film with the thickness necessary for electrode separation, and as shown in Figure 1c, the silicon substrate, on which the phosphorus vapor deposited layer has been formed, is placed in oxygen containing water vapor. By performing heat treatment at 1100° C. for 2 hours, a silicon dioxide film with a thickness of about 0.5 μm is formed.

Next, the atmosphere is changed to an inert nitrogen atmosphere, and in order to obtain a predetermined diffusion distribution, an emitter region is formed by performing heat treatment at 1100°C, which is the same as oxidation, followed by cooling at a rate of 1°C per minute. A second stage process is performed, which consists of slow cooling to about 750°C at a slow speed. FIG. 1d is a diagram showing the state of the silicon substrate after the above-mentioned treatment;
7 is the silicon dioxide film formed to the necessary thickness for electrode separation in the first stage of processing, and 7 is the N film formed through the second stage of processing.
This is the type emitter area. Next, as shown in FIG. 1e, a collector electrode 8, a base electrode 9, and an emitter electrode 10 are formed to complete the triple diffusion type NPN transistor according to the method of the present invention. The table below shows transistors 50 formed by making full use of the method of the present invention explained above.
We prepared 50 transistors formed using books and conventional methods, and conducted an accelerated operation test (Pc = 2W, Ta = 85°C).
) is shown below.

Note that deterioration was determined by regarding a change of 20% with respect to the initial value as deterioration. As is clear from this result, the transistor formed by the method of the present invention has a high HFE
There was no deterioration at all. FIG. 2 is a diagram showing the results of comparing the HFE linearity of the transistor formed by the method of the present invention with a transistor formed by the conventional method after 1000 hours of accelerated operation test, and the solid line indicates the HFE linearity of the transistor formed by the method of the invention. The dotted line shows the change in HFE with respect to the change in collector current Ic of the transistor manufactured by the conventional method, and the dotted line shows the change in HFE with respect to the change in the transistor c manufactured by the conventional method. As shown in the figure, the HFE of the transistor manufactured by the method of the present invention does not decrease in the small current region, unlike the transistor formed by the conventional method, and exhibits a substantially constant value. As is clear from the above explanation, the method of the present invention prevents deterioration of HFE and improves the linearity of HFE by switching the atmosphere during emitter diffusion and adding slow cooling selected to a predetermined cooling rate. Therefore, the manufacturing yield and reliability of transistors are dramatically improved, and this greatly contributes to the creation of high-performance transistors.

Note that although the above description has been made using a triple diffusion type NPN transistor as an example, it goes without saying that the same effects can be achieved even when the present invention is applied to the manufacture of other transistors.

[Brief explanation of the drawing]

1a to 1e are diagrams showing the manufacturing process of a triple diffusion type NPN transistor according to the method of the present invention. FIG. 2 is a diagram showing a comparison result regarding the linearity of the current amplification factor HFE of transistors manufactured by the method of the present invention and the conventional method. 1... N-type silicon substrate, 2...
... Phosphorous diffusion layer 0 type), 3, 6 ... Silicon dioxide film, 4 ... P type base region, 5 ...
... Phosphorus deposited layer, 7... N+ type emitter region,
8, 9, 10... electrode.

Claims (1)

[Claims] 1. The emitter region step is to create an emitter region in a semiconductor substrate in which the base region has been created. The emitter region process involves vapor deposition of emitter impurities and then heating the semiconductor substrate in an oxidizing atmosphere to form a thermal oxide film of a desired thickness. The first stage treatment consists of a thermal oxidation treatment to form a semiconductor substrate, a heat treatment in which the semiconductor substrate is heated in an inert atmosphere to diffuse the emitter impurities to obtain a desired diffusion distribution, and the semiconductor substrate after the treatment is slowly cooled. 1. A method for manufacturing a transistor, comprising a second step of slow cooling treatment.