JPS5940306B2 - Denkai Koukahandou Taisouchinoseizouhouhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an insulated gate type semiconductor device having a metal-insulating film-semiconductor structure, a so-called MIS type field effect semiconductor device.

In general, MIS type field effect elements are roughly divided into two types: those using metals such as aluminum or molybdenum for their constituent gate electrodes, and those using polycrystalline silicon.

Field effect devices using polycrystalline silicon for the gate electrode have many advantages due to their structure, such as self-alignment between the gate, source, and drain, reproducibility of threshold voltage, and polycrystalline silicon.
It is widely used because it allows two-layer wiring of silicon wiring and metal wiring. An element with this structure is generally called a silicon gate type MIS transistor.
When miniaturizing this silicon gate type MIS transistor and constructing a large-scale integrated circuit device, if the gate dimensions are fixed, an electrode extraction window or contact is formed in the diffusion layer soil, such as the source or drain. The spacing between the window and the polysilicon gate is an impediment to miniaturization.

For example, when two silicon gate MIS transistors are connected in series and a contact window is to be opened in the diffusion layer between the transistors, in the conventional technology, the contact window must be opened in advance so as not to overlap the gate pattern. , the distance between the polycrystalline silicon gates on both sides is 2-3μ.
We designed the pattern with the above margin in mind. That is,
An inactive area of 4 to 6 microns or more must be included in the design on both sides. If this interval is oμ, then
When opening a contact window, the silicon oxide film on the surface of the polycrystalline silicon is simultaneously removed at locations where the contact pattern overlaps polycrystalline silicon, and the wiring metal formed over the contact window is removed at the same time. This results in a short circuit between the diffusion layer and the polysilicon gate. Therefore, in the prior art, in order to avoid overlapping the contact and the polycrystalline silicon gate, the pattern design soil is 2 to 3 μm thick.
The above intervals were taken into consideration. Therefore, in order to enable the contact window to overlap the polycrystalline silicon gate, an insulating film with a thickness sufficient for electrical insulation must remain on the polycrystalline silicon surface even after the contact area insulating film is removed. must have been done.

JP-A No. 47-32781, which is already well known, describes a manufacturing method that makes it possible to overlap the contact window and the polycrystalline silicon gate by thickening the insulating film on the surface of the polycrystalline silicon in advance. It is being The first method is
This method involves covering the polycrystalline silicon surface with a thick silicon oxide film by anodizing the surface, but in this method, a part of the polycrystalline silicon to be anodized comes into contact with the substrate, and an anodizing current flows through it. must be maintained. For this purpose, it is necessary to newly provide a portion where a portion of the polycrystalline silicon contacts the substrate. In addition, in the same invention, as a second method,
By making the gate insulating film a two-layer structure of silicon oxide film and silicon nitride film, and using an insulator that does not allow oxygen to pass through even at high temperatures, such as silicon nitride film, only a polycrystalline silicon gate electrode can be used. Although this method mainly oxidizes the gate insulating film, this method results in a complicated structure including a different type of insulating film different from the silicon oxide film, such as a silicon nitride film, in a part of the gate insulating film. The present invention is disclosed in Japanese Patent Application Laid-open No. 47-327.
By improving the manufacturing method shown in No. 81, it was possible to overlap the contact window and the polycrystalline silicon gate.
This method achieves the desired improvement in device density, and also achieves the reproducibility and stability of the threshold voltage of the MIS type field effect element using a conventional method for manufacturing a silicon gate MIS type field effect semiconductor device. In the semiconductor device of the present invention, polycrystalline silicon doped with a high concentration of N-type impurity such as phosphorus is deposited on a gate insulating film and processed into a desired shape to form a gate electrode.

At this time, the silicon oxide film in the portions where N diffusion layers such as sources and drains are to be formed in the future is also removed at the same time.

After that, when thermal oxidation is performed at a temperature of, for example, 800°C, the thickness of the oxide film at the locations that will become the source and drain and the thickness of the oxide film on the surface of the N-type polycrystalline silicon are different due to the difference in growth rate.
For example, when the former grows to about 1000X, a thick oxide film grows on the polycrystalline silicon surface from about 3000X to about 5000X depending on the N+ concentration.

If the N-type impurity is thermally diffused over the entire surface using this oxide film thickness difference, the thin oxide film becomes a glass-like oxide film (hereinafter referred to as a PSG film) containing the N-type impurity. Further, an N diffusion layer as a source and drain region is formed below it, but on the polycrystalline silicon surface with a thick oxide film, only a part of the oxide film becomes a PSG film, and the polycrystalline silicon is still 2,000 yen thick. It is covered with a remaining oxide film of ~3000X.

After thermal diffusion of the N-type impurity, a nitride film and then an oxide film are deposited on the entire surface by vapor phase growth, and then a contact window is formed using conventional technology. Even if it is processed over polycrystalline silicon, silicon is exposed only in the N diffusion layer and can be used as a contact window, but only the PSG film on the polycrystalline silicon surface is etched away. , the polycrystalline silicon is still protected by a silicon oxide film 2000X to 3000X.

Therefore, when metal wiring is applied after the above contact window processing, the wiring metal forming the contact window formed overlapping the polycrystalline silicon comes into contact with the N+ diffusion layer, and electrical continuity is established with each other. However, insulation from polycrystalline silicon is maintained by the oxide film remaining between them. According to the structure of the present invention, the gap between the contact window and the polycrystalline silicon that was conventionally required is no longer necessary, and therefore, the N diffusion between the two silicon gate type MIS transistors connected in series is eliminated. When contacts are taken out from a layer, only the necessary contact width is required between the silicon gate.Integrated circuit devices using silicon gate MIS transistors can significantly improve device density. I will be able to do it.

Next, an embodiment of a field effect semiconductor device according to the present invention will be described with reference to the drawings.

1 to 5 show cross-sectional views in the order of manufacturing steps. 1st
The figure shows that a P diffusion layer 2 as a channel stopper is formed on a P type silicon substrate 1 by a known selective oxidation method, and a silicon oxide film 3 is selectively formed only in the P diffusion region. After that, a gate oxide film 4 with a thickness of about 1000λ is newly formed in the region where di-oxidation has not progressed due to the mask effect against oxidation of the silicon nitride film or the like.

After the gate oxidation shown in FIG. 1, polycrystalline silicon 5 containing a large amount of N-type impurities such as phosphorus is deposited on the entire surface, and this surface is thermally oxidized. Using this oxide film 6 as a mask, the gate area and polycrystalline silicon wiring are The area other than the oxide film 6 is removed using the conventional method.
Polycrystalline silicon 5 and oxide film 4 are selectively removed in this order (second
figure). When low-temperature thermal oxidation is then carried out at about 800° C., an oxide film 8 with a thickness of about 5000× is grown on the surface of the polycrystalline silicon 5 and an oxide film 7 with a thickness of about 1000× is grown on the surface of the single crystal silicon substrate (FIG. 3). Next, an N-type impurity such as phosphorus is diffused over the entire surface, and the oxide film 7 on the surface of the single crystal silicon substrate is converted into PSG.
In addition to the film 10, an N-type diffusion layer 9 such as a source and a drain is formed. At this time, a part of the thick oxide film 8 on the surface of the polycrystalline silicon becomes a PSG film, and the oxide film becomes as thin as 8", about 3000X. Immediately after diffusion, a nitride film 11 is spread over the entire surface by about 500X. , furthermore, the oxide film 12 is
It is continuously deposited by a vapor phase growth method of about 0λ (Fig. 4). Next, a contact pattern is formed overlying the polycrystalline silicon as shown in FIG. At this time, the oxide film 12, the nitride film 11
．． Since each PSG film 10 is removed in order with a dedicated etchant, when the last PSG film 10 is removed, the oxide film 8' on the surface of the polycrystalline silicon is hardly corroded, and about 3000X remains as it is. After opening the contact window, 300-50
0X polycrystalline silicon 13, approximately 1μ aluminum 1
4 was successively deposited, and aluminum and polycrystalline silicon were selectively etched and removed in this order to complete the aluminum-polycrystalline silicon wiring (FIG. 5). Note that instead of depositing polycrystalline silicon containing a large amount of N-type impurities such as phosphorus after gate oxidation, polycrystalline silicon containing no impurities is deposited and then impurities are introduced by thermal diffusion, ion implantation, etc. Good too. or,
The silicon nitride film can be replaced with any other insulating film as long as it has a significantly slower corrosion rate than the silicon oxide film. Furthermore, the PSG film after the formation of diffusion layers such as the source and drain may be removed using a special etchant before growing the silicon nitride film, or after removal, a thin PSG film may be re-formed using a low-temperature phosphorus diffusion method, etc. It is okay to grow and develop. The manufacturing method of the present invention has been described above in detail, but the important point is that polycrystalline silicon is impregnated with N-type impurities such as phosphorus, and the subsequent oxidation creates a source.
The point is to make the oxide film grown on the polycrystalline silicon surface sufficiently thicker than the silicon oxide film in the region where the drain and the like are formed.

In addition, when forming a contact window, a silicon nitride film is present in contact with the source, drain, etc. diffusion layers, or a PSG film, which has a significantly higher corrosion rate than a silicon nitride film or a silicon oxide film, exists between them. It is preferable that you do so. According to the invention. Like the first conventional method,
Since the formation of the oxide film around the polycrystalline silicon does not involve anodic oxidation, there is no need to create a conductive path for the anodic oxidation current to flow between the polycrystalline silicon and the substrate, and the manufacturing process is simple. It is possible to prevent an increase in the element area due to the provision of a conductive path, that is, a decrease in the degree of integration when implemented in C. Furthermore, according to the present invention, unlike the second conventional method, there is no need for the gate insulating film to have a two-layer structure of a silicon oxide film and a silicon nitride film, making it difficult to control the thickness of the silicon nitride film. It is possible to prevent variations in characteristics due to this.

Silicon gate MIS manufactured according to the manufacturing method of the present invention
In a type field effect semiconductor device, even if a contact window is placed over the structural layer of polycrystalline silicon, only the single crystal portion of the silicon surface is exposed, and the metal wiring of the contact layer is made of polycrystalline silicon. It is not allowed to short circuit. Therefore, conventionally, a distance of at least 2 to 3 μm was required between the diffusion layer contact and the polycrystalline silicon, but according to the manufacturing method of the present invention, this can be reduced to 0 μm, and the device density can be reduced. This will have a great effect on improving the Furthermore, since a nitride film or the like is used, it is possible to manufacture a silicon gate MIS type field effect semiconductor device that is resistant to external contamination and has a long life and stable device characteristics.

[Brief explanation of drawings]

1 to 5 are cross-sectional views showing the manufacturing process of an embodiment of the present invention. + 1...P-type silicon substrate, 2...P diffusion layer, 3...
・Silicon oxide film, 4... Gate oxide film, 5... Polycrystalline silicon, 6... Oxide film, 7... Oxide film of about 1000X, 8... Oxide film of about 5000X, 8''・
...Oxide film of about 3000λ, 9...N-type diffusion layer, 1
0... PSG film, 11... Nitride film, 12... Oxide film, 13... Polycrystalline silicon 14... Aluminum.

Claims (1)

[Claims] 1 Oxidize a polycrystalline silicon pattern provided on a semiconductor single crystal substrate of one conductivity type via a silicon oxide film to cover it with a thick silicon oxide film, and form a thin silicon oxide film on the exposed substrate. forming a diffusion region of a second conductivity type different from that of the substrate under the thin silicon oxide film; and converting the thin silicon oxide film into a glass layer and removing the glass layer. A method for manufacturing a silicon gate MIS type field effect semiconductor device characterized by: