JPS5940327B2 - Offset compensation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single digital-to-analog converter (hereinafter referred to as D/analog converter).
This invention relates to an offset compensation system for an encoder/decoder in which an encoder/decoder (referred to as A converter) is used as a local decoder of a decoder and an encoder in a time-division manner.

When an encoder/decoder that uses a single D/A converter in time division operates as an encoder, a sample holding circuit and a comparator are required; The device is an analog circuit, and changes in offset caused by temperature changes and other various factors pose a problem, so it is necessary to adjust the offset as appropriate.

Conventionally, as a method for compensating for this type of offset, for example, in an encoder that handles audio signals, an offset detection circuit with a large time constant is provided at the output section of the comparator, and the fluctuation status of the output of this detection circuit from the zero level is detected. The offset amount is detected from the encoder, and this detection result is fed back to the analog circuit section of the encoder to compensate for the offset amount.

However, such a detection-based compensation method has the disadvantage that it is undesirable because it increases the circuit scale.

An object of the present invention is to perform offset compensation for an encoder/decoder that uses a single D/A converter in a time-division manner using a small-scale circuit configuration with an arbitrary time constant, thereby preventing encoding and decoding operations. The object of the present invention is to provide an offset compensation method that does not cause problems.

To achieve the above objects, the present invention features an encoder comprising a sample holding circuit, a comparator, and a single digital-to-analog converter used as a local decoder in a decoder-encoder in a time-sharing manner. In the offset compensation method for a dual-decoder, the offset amount of the sample holding circuit and the comparator is detected during a period in which the operations of the sample holding circuit and the comparator are in a dormant state, and Offset Compensation Method for Adjusting Offset According to the Offset Amount The method of the present invention will be explained in detail below with reference to the illustrated embodiments.

FIG. 1 shows an embodiment of an encoder/decoder configured to perform an offset compensation operation according to the method of the present invention.

In the encoder/decoder 1, 2 is an input terminal into which the analog signal S1 to be encoded is input, 3 is a sample holding circuit, and 4
is a comparator, 6 is a logic and memory circuit, 7 is a buffer circuit for taking out the encoded output S2 from the logic and memory circuit to output terminals 81 to 83, and 9 is an input from input terminals 10□ to 103. The digital input signal S3 to be decoded and taken out via the buffer circuit 11
and a selector that selectively outputs either one of the encoded outputs S2, 12 a D/A converter that D/A converts the output from the selector 9, 13 an amplifier, 14 a resampling circuit, and 15 to 18 a A switch 20 is an offset compensation circuit operated by a mode switching signal S4 inputted to a terminal 19.

When the level of the mode switching signal S4 reaches a predetermined state for operating the encoder/decoder 1 as an encoder, the switch 15 is closed and the switch 16 is opened.
The switches 17 and 18 are respectively switched to the B and D sides as shown, the selector 9 is switched to select and output the encoded output S2, and the offset compensation circuit 20 is made inactive.

Therefore, the analog signal S1 is inputted via the resistor 21 to the sample holding circuit 3 consisting of amplifiers 22, 23, a resistor 24, a capacitor 25, and a switch 26, and is held by the capacitor 25.

Since the switch 27 is open, the output from the sample holding circuit 3 is input through the resistor 28 to the comparator 4, which in this case acts as a local decoder and is compared with the output from the D/A converter 12. Ru.

This comparison result is input to the logic and memory circuit 6, and is converted into a predetermined number of bits (in the case of 3 bits in the drawing) by the logic and memory circuit 6, the D/A converter 12, and the comparator 4, through successive feedback operations. is shown) is encoded.

That is, when working as an encoder using the mode switching signal S4, it operates as a so-called feedback encoder.

Next, when the level of the mode switching signal S4 changes to a predetermined level for operating the encoder/decoder as a decoder after a predetermined period of time has elapsed, the switch 15 opens and the switch 16
is closed and switches 17 and 18 are switched to the A and C sides, respectively.

At the same time, the selector 9 is switched to output the digital input signal S3.

In this state, the signal S3 is input to the D/A converter 12, converted into an ablog signal, subjected to waveform modification via the amplifier 13 and resampling 14, and outputted from the output terminal 28.

During this decoding period, the offset amount of the sample holding circuit 3 and the comparator 4 is calculated by utilizing the fact that the analog sample holding circuit 3 and the comparator 4, which form part of the encoder, are in an inactive state. In order to perform the correction, when the D/A converter is disconnected from the analog circuit by the mode switching signal S4, the offset compensation circuit 20 is also activated by the signal S4,
It operates to detect and process the offset amount of the output of the comparator 4.

During this decoding period, the switch 16 is closed and the level of the input signal to the sample holding circuit 3 becomes zero level, so the output from the comparator 4 is A voltage corresponding to the offset amount is output and input to the offset compensation circuit 20.

The offset compensation circuit 20 generates a correction signal for correcting the offset amount of the comparator 4 so that the output voltage of the comparator 4 becomes zero based on this input voltage value, and when the timing pulse S is input. This correction signal S6 is output, and the offset amount of the comparator 4 is corrected analogously or digitally.

Although the illustrated embodiment shows a case where the offset is corrected in the comparator 4, it goes without saying that the offset may be corrected in the sample holding circuit 3 or both.

The input timing of the timing pulse S must be such that the sample holding circuit 3 and the comparator 4 are in an inactive state so as not to cause distortion.

Therefore, as in the case of a synchronous transmitting/receiving encoder/decoder,
When the signal S4 is supplied so that the 1 decoding operation period and the code operation period are given regularly and alternately, it is possible to input the timing pulse S5 during any decoding operation period. good.

In addition, like an asynchronous transmitting/receiving encoder/decoder,
Even if the conversion clock and the D/A conversion clock are not synchronized and the positional relationship between the A/D conversion operation and the D/A conversion operation on the time chart is not determined, the above-mentioned synchronous type can be used. This is the same as in the case of a transmitting/receiving encoder/decoder.

However, if the decoding operation is performed by an interrupt during the encoding operation, when the above-mentioned offset adjustment operation is performed, the signal is held in the sample holding circuit 3 by inputting a zero level signal for detecting the offset amount. Since the voltage value that is present will be erased and the encoded signal will be distorted,
For example, as shown in FIG. 2, in the case of an offset adjustment operation performed at the time of an interrupt, the capacitor 25 may be disconnected from the circuit 3 by a switch 30.

Additionally, there is a possibility that the encoded signal may be distorted due to offset correction of the comparator 4 during the above interrupt operation, but in this case, the information of the comparator 4 when the zero level signal is input is temporarily held. Then, after the interrupt operation is completed, the input of the timing pulse S5 may be controlled so that the offset is adjusted via the compensation circuit 20 when the next sampling command is input to the sample holding circuit.

However, if this type of distortion does not become coarse, the offset compensation operation can be performed without considering such timing operation.

In the above embodiment, it is easily understood that if it is desired to perform offset adjustment of only the comparator 4, it is sufficient to close the switch 27 at the time of offset adjustment.

According to the present invention, the offset adjustment operation of analog circuits can be automatically performed during the decoding operation period, so there is no need to set a special time period for adjustment, and offset compensation can be performed digitally. Furthermore, it can be carried out using a circuit with a small time constant, which has the effect of reducing the size of the circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a main part of a modification of the embodiment of FIG. 1... Encoder and decoder, 3... Sample holding circuit, 4... Comparator, 6... Logic and memory circuit, 9... ...Selector, 1
2...Digital-to-analog converter, 15,1
6, 17, 18... switch, 20...
・Offset compensation circuit.

Claims (1)

[Claims] 1. In an encoder-decoder offset compensation system comprising a sample-holding circuit, a comparator, and a single digital-to-analog converter used as a local decoder of the decoder-cum-encoder in a time-sharing manner, the sample-holding The offset amount of the sample holding circuit and the comparator is detected while the operation of the circuit and the comparator is in a rest state, and the offset is adjusted according to the offset amount during any period of the rest state. Features an offset compensation method.