JPS5940338B2 - Digital signal reception processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal reception and processing device, and when the digital signal reception and processing device adds a cyclic code test bit to data and performs data transmission, the cyclic code is verified to determine whether or not there is an error in the data. It is an object of the present invention to provide a highly reliable digital signal reception processing device capable of early discovering a failure in a cyclic code verification circuit itself.

FIG. 1 shows an example of a conventional digital signal reception processing device, in which 1 indicates a digital signal to be transmitted;
2 is a receiving circuit, 3 is a signal path, and 4 is a second signal flowing through signal path 3.
This is a signal discrimination control circuit for extracting only a data word from the example signal shown in the figure and inputting it to a cyclic code verification circuit 6 via a signal path 5.

Here, the reason why only the data words are extracted from the signal string and inputted to the cyclic code test circuit 6 is that the frame synchronization word is generally not guaranteed to be normal for the cyclic code test. This is because it cannot be input to the sign verification circuit 6. The cyclic code test circuit 6 tests the cyclic code test bit in the data word to detect whether there is an error in the received data, and the result is sent to the data processing circuit 9 via the buffer circuit 8 using the test result signal T. supplied and processed. Here, various types of received digital signal 1 can be considered, but one example is shown in FIG. 2 as described above.

Figure 2a shows the frame structure, where one frame consists of frame synchronization words F (!11, n data words D
It consists of 1 to DN. The frame synchronization word F is unique to the data word in any data mode. Figure 2 shows the structure of the data word.
m bits of data and n bits of cyclic code (CRC) verification bits for the data are added. Then the second
The operation when the digital signal of the signal train shown in the figure is processed by the circuit of FIG. 1 will be explained.

A digital signal 1 having a signal sequence as shown in Fig. 2 is input to the receiving circuit 2.
is supplied, the receiving circuit 2 identifies the synchronization word, establishes synchronization, and performs series-to-parallel conversion (hereinafter referred to as S-P conversion).
and outputs it to signal path 3. This S-P conversion is performed when the input signal is bit series or word series.
It is not necessary in the case of word parallelism. The output signal from the receiving circuit 2 is passed to the buffer circuit 8 via the signal path 3, but at the same time, the signal discrimination control circuit 4 extracts only the data word from the signal string on the signal path 3 and sends it to the cyclic code verification circuit 6. input. The cyclic code verification circuit 6 detects errors in the received data, and sends the verification result signal T to the buffer circuit 8. In the buffer circuit 8, if there is a data error based on the test result signal T supplied from the cyclic code test circuit 6, a data error flag is added to the data and transmitted to the data processing circuit 9. The problem with the conventional method shown in FIG. 1 is that when the function of the cyclic code verification circuit 6 is lost, for example, when the cyclic code verification circuit 6 is out of order,
Error detection is not performed on the data, and erroneous data is overlooked as normal.

As a countermeasure to this problem, there is a method of checking the cyclic code verification circuit 6 using another check signal, but the circuit becomes complicated and this is not a good idea. As is well known, the cyclic code verification method is also called the cyclic code method, in which the same generator polynomial is guaranteed on the transmitter and receiver sides, and the transmitter first divides the data by the generator polynomial and checks the remainder. (cyclic code test bit) and is added to the data and transmitted.

On the receiving side, the data plus the cyclic code test bit is divided by a generator polynomial, and if it is evenly divisible, it is determined to be normal. On the other hand, the frame synchronization word is used to establish synchronization between the transmitting side and the receiving side, and is a fixed pattern agreed upon by both parties. Therefore, even if the frame synchronization word is divided by the generator polynomial using the cyclic code verification circuit, it is generally not divisible, and it is possible to determine the pattern of the frame synchronization word so that it is not divisible. The present invention focuses on this point and attempts to solve the above problem by checking a cyclic code verification circuit using a frame synchronization word, and will be explained below using an embodiment.

FIG. 3 shows an embodiment of the digital signal reception processing device according to the present invention, and the difference from FIG. 1 is that the signal discrimination control circuit 4
, and all the signals flowing through the signal path 3 are directly input to the cyclic code testing circuit 6, which not only detects errors in data words, but also tests the frame synchronization word to perform the testing function of the cyclic code testing circuit itself. The reason is that it is configured so that it also checks.

In FIG. 3, the same reference numerals are used for the same components as in FIG. 1 or those having the same functions. In FIG. 3, an example of the digital signal 1 input to the receiving circuit 2 is the signal sequence shown in FIG.
The number of bits in the frame synchronization word is equal to or N times the number of bits in the data word, and the number of bits in the data word is the same for all words.

Further, it is assumed that the pattern of the frame synchronization signal is set so that the cyclic code test does not hold, nor does it hold when it is divided into 1/N. Next, to explain the operation of FIG. 3, when the digital signal of the signal train as shown in FIG. is established, subjected to S-P conversion, and output to signal path 3.

The output signal of the receiving circuit 2 is delivered to the buffer circuit 8 via the signal path 3, and at the same time, the cyclic code verification circuit 6
is also entered. Conventionally, a cyclic code verification circuit 6 detects errors in received data, and a verification result signal 7 is supplied to a buffer circuit 8. In the buffer circuit 8, if there is a data error, a data error flag is set in the data by the verification result signal 7. and transmits it to the data processing circuit 9. However, in the present invention, all the output signals of the receiving circuit 2 are input to the cyclic code testing circuit 6, so the function of the cyclic code testing circuit 6 is the same as that in FIG. In addition, the frame sync word will also be tested. Since no cyclic code test bit is added to the frame synchronization pattern and the setting is such that the cyclic code test does not hold, all test results for the frame synchronization word are abnormal. FIG. 4 shows an example of such a case. That is, as shown in FIG. 4, the test result flag "1" is always set when the frame synchronization word is tested. Therefore, it is normal for a flag to be set for a frame synchronization word, and it is normal for a flag not to be set for a data word. In the present invention, the buffer circuit 8 adds a determination result flag (for example, FIG. 4b) based on the test result signal from the cyclic code verification circuit 6 to the processed signal from the receiving circuit 2 (for example, FIG. 4a), and processes the data. transmit to device 9;
If the data processing device 9 recognizes the determination result flag, the function of the cyclic code verification circuit 6 can also be confirmed. That is,
In the data processing device 9, the data content of the signal string is confirmed by the word address or word number, and it is possible to identify the data word and the frame period word.

Therefore, in the data processing device 9, if the verification result flag "1" is added to the frame synchronization word based on the discrimination between the data word and the periodic word, it is normal and "O".
”, it is possible to judge that it is abnormal. Also, the test result flag for the data word is the opposite. There is a data error in the frame synchronization word, and as a result, the cyclic code test result of the frame synchronization word is Although there may be a case where the error occurs, the receiving circuit 2 identifies the synchronization word as described above.

Therefore, if there is an error in the synchronization word, synchronization identification becomes impossible, so a flag indicating "synchronization failure (synchronization word failure)" is sent to the data processing device 9. Therefore, in the data processing device 9, the function of the cyclic code detection circuit 6 can be determined based on the combination of the "synchronization failure flag" and the verification result flag added to the synchronization word. Therefore, the present invention uses a frame synchronization signal and checks the cyclic code verification circuit 6 every frame. In this way, the cyclic code verification circuit 6 can be checked for each frame by using the constantly flowing frame synchronization signal without intentionally applying another check signal, and highly reliable digital signal reception can be achieved. Can configure processing equipment.

According to the present invention described above, errors in received data (code errors in data words) can be detected using a simple circuit configuration in which all incoming digital signals are tested by a cyclic code test circuit without adding a signal discrimination control circuit. In addition, the function of the cyclic code verification circuit itself can be confirmed, and a highly reliable digital signal reception processing device can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional digital signal reception processing device, FIG. 2A and b are diagrams showing an example of a digital signal format, and FIG. 3 is an embodiment of a digital signal reception processing device according to the present invention. A block diagram showing the
, b are explanatory diagrams of the present invention, in which 1 is a received digital signal, 2 is a receiving circuit, 3 is a signal path, 6 is a cyclic code test circuit, 7 is a test result signal, 8 is a buffer circuit, and 9 is a A data processing circuit is shown.

Claims (1)

[Claims] 1. In a device that receives and processes a digital signal consisting of a frame synchronization word and a data word to which a cyclic code test bit is added, the digital signal is input to a cyclic code test circuit that detects code errors in the data word, and the frame synchronization word is output. A digital signal reception processing device characterized in that it is configured to test the cyclic code testing circuit and also check the testing function of the cyclic code testing circuit itself.