JPS594045B2 - Line control processor in digital systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to digital computing and/or data processing systems, including means for controlling data transfer between a variety of different peripheral devices and a main memory of a central processing unit. and methods.

Basically, the system takes the load off the processing unit and
and distributed among various Intelligent/0 interface units, which interface units can operate independently of the central processing unit in processing data transfer operations. The invention described herein relates to the efficient implementation of an intelligent I/0 interface unit, which may be designated as a line control processor and which handles data transfer between peripheral devices and the main system. Provides intelligence capabilities to process and control transfers.

Prior Art and Its Problems The general shape of a data processing system is typically a processor, main memo! eight and a plurality of various types of peripherals or terminal devices (sometimes one
The various types of peripheral devices or terminal devices include, more specifically, card readers, magnetic tape devices, card punches, printers, disk files, monitoring terminal devices, etc. It's okay.

Optimal systems generally include configurations in which the peripheral devices are handled by a separate interface control unit so that the processor is free to access and process data contained in main memory. In configurations with separate control means for peripheral input/output devices, it is possible to have parallel or simultaneous processing at the same time that input/output operations occur. These concurrent 1/0 operations occur within the same program that runs through one of the processors and also initiates all I/O operations. Additionally, the program may perform I/O operations inactive. There must be some means of determining when the I/O operation is complete or when the I/O operation is completed. As an example, if a program requests a file of data to be loaded into main memory, it must determine when that operation is completed before it can proceed to use the data. must be able to do so. Thus, an I/O operation is typically initiated or initiated by a program with some type of "start instruction" that provides an address pointing to an "I/0 descriptor" stored in main memory, for example. It will be started. This descriptor identifies the peripheral device on which the data is to be received and/or transmitted, it identifies the type of operation such as "read" or "write", and it also identifies the type of operation to be used for input/output operations. Identifies a field in a main memory storage location. Generally this I/0
The descriptor is transferred to control means (1/0 control means) to control data transfer between the peripheral terminal device and the main memory. When an I/O operation is "completed", for example by transferring data from a peripheral to main memory, such as loading into main memory, some form of completion status is required, and this is typically is indicated as a "result descriptor". Usually this is transferred from the I/0 control means to some specific location in main memory known to the program being used. Typically, a result descriptor includes information identifying a particular peripheral terminal device and further includes information regarding the result or status of that particular input/output operation;
Therefore, whether a transfer was completed and correct, or whether an exceptional condition occurred or any error occurred or any other specific case is indicated with respect to a transaction involving that particular peripheral terminal. information on whether or not the Therefore, when a program initiates an I/O operation, the program must have some means to determine when the I/O operation is completed.

The standard technique for this is for programs that have instructions to periodically interrogate a result descriptor to determine when and whether a particular input/output operation has been completed. It is. However, if the input/output control means
It is fairly easy to indicate when a transfer operation is finished. Achieving this typically requires the processor to interrupt any operation that has an underway, and force it to examine the result descriptor and take appropriate action. It is necessary to do so. This cessation or interruption of processor activity is commonly referred to as an "interrupt." Thus, when an interrupt occurs, the processor must stop the running program, it must create a fixed indication of at what point in program execution it was interrupted, and it must determine the contents of some register. and control the flip-flop so that it can have information about where it should return to in the program after the completion of the interrupt cycle, and then the processor directs its attention and operations to , the interrupt condition must be handled and forwarded to the designated program for servicing.

Some systems, such as the one described here, are
has a program for servicing "interrupt"conditions;
The program is sometimes referred to as the MCP or master control program.

The program must keep a record of the current I/O operation and must associate the particular I/O operation that caused it with that particular interrupt. It must then analyze the results of this interrupt cycle to know if any abnormal circumstances or exceptions have occurred or if an error condition has been reported, so that corrective and appropriate actions can be taken.

The interrupt program must take the results of the I/O operation and make them available to the program that initiated the I/O operation and then It must be determined whether the input/output operation is enabled and, if so, action must be taken to initiate other necessary input/output operations. In many traditional and current system configurations, a call or request for memory access is
It has become popular to obtain memory services, but due to the limited bandwidth and time available to various peripherals, many 1/O transfers are incomplete and result in "access errors." .

Also, many prior art system configurations provided only one or two communication paths or channels to a large number of peripheral terminals, so that a particular peripheral terminal's I/O transfers were limited to access and use of the communication bus. They had to wait their turn in allowing.

This caused congestion and delays to the system. It also made systems involving multiple programming difficult,
This is because an effort is made to match a job with heavy I/O requirements to another job that is "processor limited" and has only limited I/O requirements. Many of today's data processing systems have one or a limited number of communication paths between a central processing unit and peripheral devices. Generally, there are one or more "input/output control" means within the communication path.
When an I/O path is requested by a processor, the path is generally used when the peripheral is not initiating a transfer operation, when the peripheral is in use during a transfer, or during other operations with I/O control means. When not inside,
and only become available when the peripheral device or its input/output control means is not in use by other operations. The data transfer rate of the input/output pedestal means is, of course, the limiting factor in the operation of the system, since the slow transfer rate of certain peripherals (which are passed through the input/output control means) This is because it unnecessarily impedes processor and memory activity for the slower speeds of peripheral terminals.

Thus, many data processing systems are now provided with multiple input/output controls, including buffers, to allow a particular peripheral or group of peripherals to communicate with the main system. There is.

Some prior art systems perform data transfer operations in a sequential manner when there are multiple input/output control means that pass communication channels to individual peripheral devices or groups of such devices. Because of the method of operation, the various input/output control means take turns in providing the peripherals associated with them. Some peripherals and their associated I/O controls are in use more than others, and some of the channels they actually involve require more air time than they are getting. Difficulties arise in determining this.

A "channel" may be viewed as a communication path between main systems to peripheral devices via input/output control means. In this way, a channel within which a large number of "access errors" occur can cause cases where "short changes" are made. Access errors include the case where the data byte being transferred via the input/output control means does not contain a complete message unit, but only consists of an unusable part of the message unit. As a result, the central processing unit is not acquiring or transferring useful information and must become stuck when continuously requesting the same input/output operation over and over again. Thus, when peripheral devices are placed in the event that they are unable to send or receive all message units or records, they can lead to uncompleted cycles on a particular channel and to unsuccessfully complete the transfer of the required information data. There is a possibility of access errors leading to If the maximum transfer of data is through the aforementioned multiple input/output control means and incomplete cycles of data transfer (which cannot be used and whose time periods are labored and unused, It is desired that such access errors occur without causing such access errors which would otherwise lead to errors (which would otherwise take up valuable processor time).

Thus, in such system configurations, questions arise as to how much time should be allocated to each individual channel for data transfer operations, and furthermore, which channels have priority status over others. This raises the question of whether it should be provided across channels.

Now, in a data processing system that includes a large number of peripheral devices (many of which are located in different facility locations), it is necessary to group the input/output control means that are to handle the various peripheral devices at each given location. Must have. Thus, the priority problem not only includes the priority to be given with respect to competition between peripherals at one locally given location, but also includes the priority problem of priority assignment as between different local locations; Each of the different local locations has their own input/output control means. OBJECTS OF THE INVENTION It is therefore an object of the invention to enable all data (i.e. message length blocks of data) required at any time to the main system to always be transmitted in one cycle without interruption. An object of the present invention is to provide a line control processor in a digital system.

SUMMARY OF THE INVENTION The present invention provides a digital data processing system for the control and processing of input/output operations (data transfers), such as between a plurality of various types of peripheral devices and a central main system (processor and main memory). include.

Two types of I/O subsystems are provided for communication to the central master system. An I/O subsystem uses a type of intelligent interface control unit designated as a "line control processor" (LCP), and each LCP has a specific A system specifically oriented to control and process data transfers to and from peripheral terminals of a particular type.

For example, the basic LCP is adapted in each particular case to handle power readers, disk units, train printers, or other special types of peripherals. LCPs are typically placed in groups of eight units to form the LCP base module. Each of the base modules is grouped in sets of three to form an LCP cabinet unit. A plurality of such LCP cabinet units may be used to configure the first I/O subsystem. Another I/0 subsystem is provided for those types of peripheral terminals for which no specific line control processor (LCP) is generated.

This second I/0 subsystem is organized so that
A central control unit is provided to control paths from the central processing unit and main memory to selected input/output channels that provide data paths to individual peripheral devices. These individual channels each have their own memory buffers and connect to the main system via a central control unit. In the /0 subsystem with line control processors (processor and main memory)
The main system also includes an input/output translator unit (I
A unit called OT) is provided, and the IOT is
It is part of the main system and provides an interface between the main system and another distributed control interface designated as a "distributed card unit" which processes the base module (group-free of line control processors and its IOT connects selected individual line control processors to the LCPI/0 subsystem.

The line control processors (LCPs) are organized into eight groups called LCP base modules, each of which supports the input/output b lansulator IOT of the main system and the eight LCPs of any given base module. It has one "distribution card unit" that provides an interface between the two. Each base module also has a maintenance card unit that can provide all maintenance and check functions for the base module's group of eight LCPs. Each base module is also provided with one common "terminal card unit" which provides a common locking function for all LCPs of the group and is also provided with the various LCPs of that particular base module, distribution cards, and provide the correct termination for the transmission line connecting the maintenance card. The main system IOT operates in a unique relationship with the distribution card unit of the LCP base module in the LCP7O subsystem, allowing any number of simultaneous data transfer operations to be performed in a manner that does not overload the central processing unit. data transfers between peripherals and main memory in a manner that allows data transfers to occur between peripherals and main memory. This is facilitated by the use of each LCP's record length buffer memory. Data transfer cycles are accomplished using a complete data message block that prevents "access errors" from occurring. The embodiments of the invention described herein provide a system that helps alleviate certain problems inherent in prior art systems. By providing separate channels from the main system to each peripheral, data transfers (between a particular peripheral and the main system) are not required to wait for the use of a shared communication channel because Each individual peripheral is provided on its own channel so that each of the plurality of peripherals can operate simultaneously without any further demands from the processor or any interference with processor operations. It is possible to complete an input operation without any problems. I/O data transfer control in the subsystem is provided by an individual "Line Control Processor" (LPC) for each peripheral. "Line control processors" receive I/O commands from main memory (via the 1/O translator unit), and they execute these commands independently of the main processor, so that I/O control operations are responsible for their processing. This is done in parallel and asynchronously. Memory control unit 10c
(Figure 1A) shows the main memory, central processing unit and I
/O Regulates the flow of data between subsystems.

This allows each of the system components to access main memory on a priority basis, giving highest priority to the I/0 subsystem. Since the memory control operates independently of the processor, the processor is free to perform memory independent functions at the same time that memory access is allowed to the I/O subsystem. Each line control processor is provided with a memory buffer capable of storing all message blocks or record lengths of data.

In this way, data transfers between the main memory and the line control processor can occur at high speeds and constitute a complete message program in itself. Since a complete message block of data is transferred in any given cycle, the problem of access errors is eliminated, so no further notes are required to complete the incomplete previous data transfer cycle. Recycling time is also not required, which may result in cases where there is no record length buffer. Because the line control processors are functionally the same except for slight variations that may occur, they can be adapted to work with different types of peripheral terminal equipment, and the LCP It is "transparent" to the main system.

In some cases, no specific line control processor (LC)
P) also includes non-generated peripherals and data storage devices. In this case, another input/output control subsystem is used that can operate in parallel with the first I/O subsystem and its line control processor (LCP). A main or central system of the described embodiment (a device called an output translator or IOT) is provided which includes a processor, main memory and memory control.

When the 0T receives a 1/0 descriptor from memory, it operates with the LCP base module to establish a connection to a particular LCP for the channel specified by the "Start 1/0" command from the program. It is a special part of the processor that

The 0T converts the l/0 descriptor into a format (command descriptor) understandable to the LCP (Line Control Processor) and passes the converted descriptor to the LCP when the connection is established. Data transmission then begins.

During the time that data is being transferred between the LCP and the main system, the IOT requests memory access and addresses memory based on demand by the LCP;
Then change and compare the data addresses. OT controls the routing of data between the selected LCP and the main system, and it performs data conversion (ASCII/EBCDIC) if so required.

ASCII/EBCDIC stands for American Standard Code/Extended Binary Coded Decimal Code for Information Interchange. When the operation completes, 0T receives the result descriptor (
R/D) information and then stores a result descriptor (R/D) in a predetermined storage location. A line control processor (LCP) is a device that, when receiving a command descriptor (C/D) from the main system via OT, establishes a communication path to a selected peripheral device.

Once this path is established, the LCP receives data from or passes data to the peripheral. Each LCP has a "data buffer" (typically 256
data) so that data can be transferred to and from the peripheral at the relatively low speed of the peripheral, and then when the buffer is filled, the data can be transferred to and from the peripheral at the relatively low speed of the main memory. can be transferred to the central master system at maximum speed. Thus, a unique interworking relationship exists between the main system's 10T (input/output translator) and the LCP, which is the interface control between the peripherals and the main system. Furthermore, the unique operating relationship is that each LC of the base module
P and the distributed card unit, which interfaces a given LCP to the main system's IOT. The /O subsystem, described herein, provides for interconnecting the host system to selected LCPs as well as coordinating priority among the LCPs for access to main memory. The present invention, which is specifically claimed within the scope of the present invention, is an intelligent I/O interface device designated as a line control processor that provides the functions described above.The primary purpose of the line control processor I/O subsystem is Some of these are summarized below.

One of its goals is to ease the central processing unit's involvement in monitoring and controlling data transfers between the system's main memory and numerous peripheral devices.

One of its objectives is to increase the speed of data transfer between various different peripheral devices that are all connected to a main system having a main memory and a processor.

This includes transfers from main memory to any individual peripheral device and vice versa in this system. One of its objectives is to provide an intelligent I/O interface control unit (line control processor) that offloads much of the central processing unit and is responsive to the needs of various peripherals for access to main memory. That's true.

One of its purposes is to be able to receive I/O instructions from the central processing unit and then independently continue to control, monitor, and execute this instruction so that the main system memory and an intelligent interface/O control unit that establishes data transfer between any specifically desired peripheral devices. This is done asynchronously as necessary and requests occur. Interface unit (LCP)
also as to its completeness, incompleteness, or error status.
In addition to keeping the main system informed of any data transfer cycles, all word and message processing. Handles error checking for block transmissions. The line control processor also monitors requests from peripheral devices for access to main memory and
Informs the main system of "in use" or its unavailability. Another purpose is to allow easy modular system expansion.

The /O subsystem of a central processing unit serving multiple terminal devices is set up such that the interface units (line control processors) are organized into base modules in groups of eight devices. Each module has a distribution card unit that interfaces a group of eight line control processors to the main system via the main system's OP. Thus, priority can be set between any of the eight line control processors in the distributed card unit (person base module).Furthermore, when multiple base modules occur in the system, each base module The distribution of units within the entire set of base modules can be given a priority ranking (denoted as overall priority) as between the priority ranks allowed for any given base module. .In this way, the included 1/0
Another purpose of the subsystem is to have global priority (priority as between base modules in the system) and also local priority (precedence of each line control processor in a group of eight line control processors in the base module). The objective is to provide a configuration for setting up state preferences. One of its objectives is to ensure that all data required at any time for the main system (i.e., the message length block of data) is transmitted in one completed cycle without interruption (except under emergency conditions). The goal is to eliminate "access errors" so that they can be read and error checked. One of its purposes is that once a communication channel is established, it can be transferred between the system's main memory and a given peripheral without interruption or incomplete data transfer (except in some emergency cases). The purpose of this invention is to allow rapid completion of data transfer operations. One of its purposes is to provide the main system with the current state of any line control processor at all times and the result (complete, incomplete or error) of any given data transfer cycle.

One of its objectives is to provide a modular building process to facilitate expansion of the system by increasing the number of peripherals that can be included in the system in a simple and economical manner. One of its purposes is to
O subsystem by which the central processing unit is removed from performing I/O data transfer cycles and whose operational loads are grouped into modular program units. distributed throughout the system.

Summary of Embodiments A digital system in which a line control processor according to a preferred embodiment of the present invention is implemented includes a main system (processor (central processing unit), memory) and peripherals attached to the main system and working within the system. Device and first input/output (1/0) subsystem (input/output control device 10C)
and a second input/output subsystem (line control processor L
CP).

Communication of data between the main system and peripheral devices is controlled through these input/output subsystems. "Descriptor" information is used to control the input/output subsystem. The first input/output subsystem works with the processor and the central controller CC. The second input/output subsystem works with the input/output translator IOT, which is part of the processor. The invention relates in particular to a line control processor LCP and therefore in particular to a second input/output subsystem. The line control processor LCP is an interface between the main system and the peripheral device that receives command descriptors (C/D) from the main system via the input/output translator IOT and establishes a communication path to the selected peripheral device. It is a device.

Once this path is established, the line control processor L
A CP receives data from or passes data to a peripheral. Each LCP has a “data buffer” (
(typically 256 words), data can be transferred to and from the peripheral at the peripheral's relatively low speed, and then when the buffer is filled, the data is transferred to main memory. It can be transferred to the main system at the highest rate allowed by speed. In this way, the input/output translator 10 of the main system
A unique interworking relationship exists between T and the line control processor LCP. The line control processor LCP is L
It is organized into eight groups called CP base modules.

For example, LCP2OOO to LCP2007 form one LCP base module 200. Each of the base modules has one common distribution card device that interfaces between the input/output translator IOT of the main system and the eight line control processors LCP of that LCP base module. A unique cooperative relationship also exists between each line control processor LCP and its line control processor LCP.
It exists between the distribution card unit of the base module to which it belongs. The distribution card unit is the selected LCP.
It not only interconnects the main systems to each other, but also coordinates priority among the LCPs for access to main memory. L.C.
P can be made in a wide variety of formats, each configured to work with a particular type of peripheral.

Since peripherals differ in their operational characteristics, the LCP handles its own specific peripherals and
It is devised to be able to be controlled and specifically adapted. FIG. 6B shows a generalized block diagram of the line control processor LCP.

FIG. 6B also shows the distributed card device 200d and the IOT
Figure 2 shows the interrelationship of the line control processor LCP to lOt. If the LCP is in the “connected” state and
If a WRITE operation is being initiated, data is provided from IOTlOt to the LCP via backplane receiver 23r. for operation
Multiplexer 24x to select data source
1 is used. In this case, the data source is IOTlO
It is t. The output of multiplexer 24x is sent to LPW (vertical parity word) circuit 24w and multiplexer 2
The multiplexer 24x2 transfers the data from the multiplexer 24x1 to the data buffer 250.
Gate to 0. LCP is data buffer 250
Continue to receive data from 0T10t until 0 is filled. While the LCP continues to receive data, the LPW circuit 24w generates the LPW sum.

When the transmission is finished, IOTlOt has a vertical parity word (
LPW), and the vertical parity word LPW is transmitted to the LPW circuit 24 if there are no errors in transmission.
Clear w. If circuit 24w is not cleared, an error will be displayed. Once the data buffer 2500 is filled, the LCP backplane transmitter driver 23x and backplane receiver 23r are disabled and the LC
P is cut off from the main system (0T).

Next, the LCP drives the front plane transmitter 1 driver 28
x and frontplane receiver 28r to establish a data path to peripheral device 50. Once this path is established, the LCP uses multiplexer 27x to select the data buffer 250 to be transmitted to peripheral device 50.
Select and translate (translated or untranslated) data from 0. Transmission continues until the data buffer 2500 is empty, at which point the LCP requests a "reconnect" to the OT to store the result descriptor or request more data. If a "read" operation is in progress and the LCP is
OT), data from peripheral 50 is provided to the LCP via frontplane receiver 28r.

The output of frontplane receiver 28r is bussed to multiplexer 24x1, which in turn selects peripheral device 50 (via frontplane receiver 28r) as the "data source." The output of multiplexer 24x bypasses LPW circuit 24w and is applied to multiplexer 24x2, which selects multiplexer 24x1 as an input to data buffer 2500. data buffer 250
When 0 is satisfied, front plane receiver 28r and front plane 1 driver 28x are disabled;
The LCP is reconnected to the IOTlOt and the backplane receiver 23r and backplane driver 23x are activated. The LCP now begins transmitting data (to the main system 10) from the data buffer 2500 via the multiplexer 24x and the drive 23x to the IOTlOt.

During this transmission, the output of multiplexer 27x is also
The signal is applied to the LPW circuit 24w via the multiplexer 24x. When the data buffer 2500 is empty, the LC
P sends a signal to IOTlOt and vertical parity word LP
W is incoming, and then the LCP, via multiplexer 27x and driver 23x,
Gate the final LPW sum into OTlOt.
After transmitting the longitudinal parity word (LPW), the LCP is disconnected from the main system (OT) for the purpose of receiving additional data from the peripheral device 50.

If there is no further data, the LCP stores the result descriptor and proceeds to the "idle" state. A data buffer provided in each line control processor LCP is capable of storing an entire message block or record length of data.

Therefore, the main memory and line control processor LCP
Data transfer between the
It essentially constitutes a complete message block. Since a complete message block of data is transferred in any cycle, the problem of access errors is eliminated, thus making it possible to complete the "incomplete previous data transfer cycle" that would otherwise occur in the absence of a record length buffer. No additional memory cycle time is required. DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention, a line control processor in a digital system, will be described in the following indexed order.

〔overview〕

The digital system described herein includes a processor, memory, a series of input/output controllers (IOCs) forming a first I/O subsystem, and a line control processor (LCP) organizing a second 1/0 subsystem. ) system.

The line control processor essentially handles input/output operations for a particular peripheral device with minimal interference with the main processor operations. Furthermore, no peripheral is "aborted" waiting for memory access because the LCP for that peripheral is always readily available to service that peripheral. Prior art data processing systems use a hierarchical system of main memory in which large, slow, large memories store information in small, high-speed blocks before it can be used. Must be transferred to processor memory.

The system described here consists of a processor and I/
0 subsystem directly access any region of memory, and since memory can be up to 1 million bytes in size, more information can be sent to the processor without imposing additional I/O activity. It can be used. The system is equipped with high speed (250+1 second cycle time) bipolar memory along with an error correction system. Bipolar memory is not only faster, but is also inherently more immune to the types of errors that cause program failures. If an error is detected, error correction is performed during a normal memory cycle and no additional time is required for the correction cycle. The various operating relationships between the main memory of the processor of the system of this invention and other devices are described in [Burroughs B28OO/B38OO/B48OO Series, MS-2 Reference Manual, Catalog 10]
905601 Copyright 1976'', published by Burroughs Corporation. Typically, /0 memory cycles occupy only a small portion of the total available memory cycles.

However, during periods of high 1/0 activity, the probability of any two devices requesting the same memory cycle increases. When a device does not access memory within a system-allocated time period due to concurrent requests, valuable time is lost while the operation is retried. Additionally, many memory cycles are unused during periods of low/0 activity. The /O activity problem is solved in the system of the present invention by distributing /0 processing among groups of LCPs or line pedestal processors that are organized into base modules of each of the eight LCPs. .

In doing so, the central processor is only required to initiate I/O activity and it takes no further role in input/output (1/O) operations. The central processor has an input/output translator (
0T) to initiate I/0 activity. Once started, LCP can buffer large amounts of data and, in most cases, can buffer the entire message process.

At some point in the operation, when the LCP requests access to memory and is granted access, the LCP transfers information from its word buffer to memory at the maximum speed of the memory operation. Now, if the requested access to memory is not granted, the LCP
It continues to fill its word data buffer while having the opportunity to access memory. In this way, the peripheral device is protected against inactivity because its data is transferred to the LCP's buffer. It transfers it to main memory without losing the memory access period. The results of this method and system are:
The peak load placed on memory by the demands of I/O activity is removed, and the I/O subsystem instead uses those memory cycles that would otherwise be lost. This method of I/0 processing is more efficient, so the system can have higher input/output (1/0) data transfer rates and also more I/O
It can support the device. [Descriptor Information] This computer system has two content input/output subsystems, a first subsystem of a 1/0 controller and a second subsystem of an input/output translator working with a group of line control processors. In the system, control of the system is facilitated by the use of "descriptor" information that is passed between the various units.

A "result descriptor" is a report to the main operating system that describes the manner in which an operation was completed or why the operation could not be completed.

The result descriptor for the processor and for the I/O control system is 16 bits (1 word) long.
However, the LCP result descriptor may be longer than one word, and each bit of the result descriptor represents the state of some condition to be reported to the main operating system. The LCP (line control processor) and I/0C (1/0 controller) always write a result descriptor upon completion of an operation; the processor writes a result descriptor only if an error condition is encountered. The result descriptor is written to a predetermined location in memory, which for the processor is, for example, address 80. L.C.
The result descriptor for P and /0C is the formula (C
H x 20) plus 200, where CH is the channel number of the device being started.

The IOT result descriptor is written to address 260. After the result descriptor is written, an interrupt is generated. LCP Result Descriptor, R/D When its assigned operation completes, the LC
P stores a result descriptor that describes to the processor the manner in which the operation was completed.

The LCP result descriptor consists of one, two or three 16-bit words. first result descriptor, R/
D, is stored in memory at a memory location specified by the equation (CH x 20) plus 108, where CH is L
It is the number of channels of CP. Result descriptor information 2
If more words are to be written (expanded result descriptor), additional words are stored in the address memory of the IOT. As shown in Table 1 below, the first LCP result descriptor word is preceded by a one-word link and channel (IOT) result descriptor. Typically, that link is used by the operating system as the address to the next result descriptor to be examined. The table is 4 digits,
The basic word format is shown for a "data" word with A, B, C, D, each digit having 4 bits and each character having 8 bits. A8,
Symbols are used to indicate the parts of each digit, such as A4, A2, Al, etc. 1 word - ABCD = 16 bits The table below shows the format for the /O descriptor, which is normally stored in main memory and then used for the purpose of coordinating certain types of input/output operations. be accessed.

As seen in the table, there are four syllables (hereinafter referred to as syllables), and each syllable consists of six digits. These digits are D1-D6, D7-Dl2, D to indicate the relative position of each digit.
They are labeled l3-Dl8 and Dl9-D24. In syllable 1, digits D1 and D2 always specify the type of input/output operation to be performed and are commonly referred to as "OP-codes." Digits D3-DD6 are
Specific input/output operations are indicated as [different orders] in that they specify various options that can be combined. Syllable 2 contains the address of the most significant digit (MSD) of the main memory section used for this particular I/O operation as a memory buffer area. This buffer area is indicated as the starting address. Syllable 3 is the lowest digit plus 1 (
Contains the address of LSD+1). The highest and lowest addresses plus one represent the maximum memory boundary limit of the record being transmitted. The record length may or may not use all of the area within this limit. However, any attempt to exceed this limit will terminate data transmission to that area. Syllable 4 is used only for the disk file descriptor and contains the disk address. The record length may or may not use all the space within the start address and end address limits.
As explained, any attempt to exceed this limit will terminate data transmission to that region. For example, a punch card
May be read out to an area larger than 80 characters,
i.e. MSD and LSD with 80 characters independently
+1, or the punched card may be read into an area of 80 characters or less, eg, the record area defined in the specific purpose program reflects the 40 characters in the card reader record. The data in columns 1 to 40 of the punch card are MSD and L
It is stored in the record area of the core memory allocated by SD+1. 1/O Subsystem System Description: (General) The 1/O subsystem is provided as part of a digital systems environment and includes a central data processing system and a wide variety of peripherals attached to and working within the system. Provides a means of communication with the device.

Peripherals that work with the overall digital system described here can range from mass storage devices such as disks or disk packs to system control devices such as operator monitoring terminals, or printers, card readers, card This ranges from punches to various other peripheral devices such as magnetic tape storage devices and the like. The I/0 subsystem described herein can be divided into two main subsystem categories based on how the various peripherals are controlled.

The first category uses methods that use an I/O controller (IOC) that works with a processor and a central controller to handle the I/O activity. The second category uses central processing unit input/output translators (IOTs) that work together with a separate unit called a line control processor (LCP). The device, known as a line control processor, is a device that establishes a communication path from the system (main memory and processor) to a particular peripheral device. Once a communication path is established, the LCP can receive data from or pass data to a particular peripheral for later transmission to the main system. Each LCP has a built-in data buffer so that data can be transferred to and from a given peripheral at the relatively low speed of the device; however, the LCP's data buffer transfers to the main system memory and processor. When connected as such, data can be transferred to the main system at the highest rate allowed by the central system's memory. The first category of I/O subsystems that use IOCs as an interface from peripherals to main memory and processors have a central control (CC) unit that interfaces I/O channels and IOCs with the central processor and memory.

These input/output controllers receive instructions from the processor and they return data information including the results produced with respect to that particular instruction. This resulting information is placed in a specialized memory location in main memory. /O subsystem second
The category includes systems in which the processor and main memory communicate through an input/output translator (IOT) to a group of LCP-based modules, each of which supports a group of eight line control processors (LCPs). Configure the device that will be used.

In this way, instructions from the processor are converted into specialized sets of commands that can be accepted into individual LCPs.
Transformed by T. After the LCP receives an instruction from the IOT, it reports back some "result information" that is stored in a specialized memory location in main memory.
Thus, all communication between the main system processor and memory to a particular peripheral is controlled by the LCP that is uniquely tailored to that particular peripheral.

When a line control processor LCP (or input/output control means with a central controller) is provided, it
It is assigned a unique number called "channel number".

For I/O controllers, this number corresponds to one word of scratchpad memory located in the processor.
For the Line Control Processor (LCP), this "number of channels" corresponds to one word of scratchpad memory in the I/O Translator (0T). Start 1
It is initiated by the /O instruction, which tells the processor where to find the appropriate I/O descriptor in main memory and what number of channels it is intended for.

The /O descriptor includes the OP code and also includes a variant for the type of /0 operation selected, as well as the starting A and ending B main memory addresses of the included memory region. The processor accesses this I/0 descriptor and then selects the IOC (first
subsystem) or IOT (second subsystem)
Send the 0P code and its variations to.

The IOC or IOT verifies the OP code and signifies acceptance or rejection of the request. In the first subsystem, the processor loads the starting A ending B address into a local register and informs 10C that the address is available.

These specific addresses are transferred by the IOC to the scratchpad memory location for the indicated I/O channel. In the second subsystem, IOT
accesses the A and B addresses directly from the memory address lines leading to the processor's "local register 10pr" (Figure 3) during transfers from main memory, and thus the IOT accesses its own local scratch. Load the padded memo l river 0ps.

Access to main memory is shared by the IOT, central controller and processor. highest priority is IO
shared by T and the central controller. The timing is so configured that each central controller is guaranteed to
limited. 10T is guaranteed for the remaining cycles.

When the central controller is not requesting memory, the IOT can take all memory cycles. Processors take all available memory cycles based on lowest priority. In this way, I/O communications in the system are initiated by the processor with 1/O instructions (which are, for example, 0P-94
).

This start command specifies the number of channels of the requested device and also specifies the location of the /O descriptor in main memory. The 1/O descriptor specifies the action to be taken by the peripheral and specifies the memory boundaries of the data field.

The descriptors, and the manner in which they are executed, vary based on how the peripheral is controlled. If the start 1/0 instruction is /O control (first 1/0 subsystem)
, the processor sends the descriptor OP code, variant, and C address (if used) to the I/O controller.

The descriptor's A (start) and B (end) addresses are stored in the processor's I/O channel address memory. The I/O controller ensures that the OP code is valid and then signals the peripheral where the data transfer should begin. As previously discussed, the digital system embodiment of the present invention includes a dual relationship of input/output subsystems.

The second of these is an input/output translator (IOT
), a base module having a plurality of line control processors (LCPs), and a plurality of peripheral devices;
As shown, it includes a central controller 12 that interfaces with a plurality of /O controllers 13a and 13b, which in turn interface with a plurality of peripheral devices 14a and 14b, etc. interface. First I/O Subsystem The following discussion encompasses a first I/O subsystem that includes an IOC along with a central controller CC.

FIG. 1B shows a system in which the /O channel is connected via central controller 12 to processor 10p and main memory 10m.

The logic level is 100, 101 for each 1/0 channel (1st C
) and is combined by central controller 12 before being sent to processor 10p and main memo 1J10m. Other logic levels are generated by the processor and in memory and distributed by central controller 12 to each 1/0 controller, such as 13a in FIGS. 1A and 1B. There are also logic levels that pass through central controller 12, which serves as the connection between processor 10p and the I/O chain. Priority logic 10pc of FIG. 1C determines which of the I/O channels is allowed to access main memory 10m if more than one channel needs to be accessed simultaneously. As seen in FIG. 1C, the central controller 1
As part of 2, a plug is included in the translator, which translates BCL (Burroughs Common Language) data into EBC when EBCDIC (Extended Binary Coded Decimal Code) goes to or comes from core memory 10m.
Can be converted to or from DIC.

I/O controllers 13a, 13b of FIG. 1A request central controller 12 to use translator 12t of FIG. 1C or to bypass it. Conversion occurs when data is transferred between an I/O controller, such as 13a, and main memory 10m. No additional time is required for I/0 operation even if conversion is required. Translator logic translates incoming Burroughs Common Language (BCL) data into EBCDI
FBCDIC data to be converted or output to C (extended binary coded decimal code) data is written in Burroughs Common Language (BCL).
). These EBCDIC codes that are not assigned to BCL codes cause the BCL signal [? ” is generated. Central controller 12 serves as an interface between the /0 channel and main memory 10m during system operation, as seen in FIGS. 1B and 1C. If more than one channel requires access, it determines the priority of memory access, and it determines whether data comes into memory from an I/O channel or from an I/O channel, such as memory 10m to 100. Convert data to

A central controller correlates the various functions of the channels. The sequence of events is initiated by processor 10p when a 1/0 channel is required. When the program being executed requires a peripheral device, such as 14a or 14b of FIG. 1A, processor 10p executes a Start 1/O instruction.

This command reads the /O descriptor from memory 10m and then sends the necessary information to I/O channel 100 via central controller 12. This information includes the type of operation (OP code) and transformation information. The remaining portion of the I/O descriptor, including the start (4) and end (3) addresses, is stored in address memory 10pam (FIG. 1C) of processor 10p. The channel is selected by the channel designation level (CDL) seen in Figure 1B, and the line comes from processor 10p. Once all the information is available, the /0 channel 100
Start channel busbar (STC) to operate independently
B) (Figure 1B). When an I/O channel is freed, it acts as another processor and connects to the main processor 10p or another channel (1C
) and the main memory 10m are shared. If the operation being performed involves an input peripheral device 141, such as a card reader, the data is received by the I/O channel 100 seen in FIG. 1C;
And that data is sent to buffer C within I/O channel 100.
.

Stored in The I/0 channel then requests access to main memory 10m via central controller 12. This request is handled by the priority logic 10pc which simultaneously controls other requests. Once memory access is granted to the channel, information is transferred to memory 10m. Information may or may not be transformed based on the 1/O descriptor. The information is then the start and end of the address memory 10pam (
B) written to the main memory 10m at the memory location specified by the address. If at some point it is desired that data or information be transferred to a peripheral device, this is called an "output" operation (first
Figure D).

If the ``output'' operation had been performed, a similar sequence of events would occur if the data were stored in main memory 1.
Occurs as before, except from 0 m to a 1/O channel such as 102 in Figure 1D. Therefore,
For example, when a peripheral device such as a printer 14p needs data, a memory access request is sent to the /O channel 10.
2 to the central control unit 12. When priority is granted to that channel, data is transferred to main memory 10 from the address specified by the start and end addresses located in address memory 10pam.
This data is then transferred to I/O channel buffer C2 via translator 12t (or bypassed around the translator based on the I/O descriptor). As seen in Figure 1D, the data is then transferred to a peripheral such as 14p. As seen in FIG. 1E, central controller 12 provides an interface to/from I/O channels, processor 10P1 and core memory 10m. Control information from the processor 10p is sent to the central controller 12,
There it is distributed to each /O channel as 100, 101, etc. The central controller 12 controls this first I
Processes all core memory requests made by the I/O controller of the /O subsystem. Data from each 1/O channel to be written to core memory 10m is placed by central controller 12 on the memory write bus, and data to be read from core memory 10m is placed on the core memory read bus. and distributed to each 1/O channel. When a request is made by an I/O channel device, central controller 12 obtains the core memory address from address memory locations reserved for that particular I/O channel.

This address is used to access main memory I0m and a memory cycle is then initiated.
Memory cycles are either "read" or "write" based on the specific I/0 operation. When processor 10p requests a memory access, the memory address involved is obtained from address memory 10pam located in processor 10p. This address is used to access main memory 10m and a memory cycle (either read or write) is initiated. Since only one memory access can be made at a given moment, multiple memory requests must be handled individually, and this processing is prioritized by the central controller 12, as described above. Rights control 10pc
(Fig. 1C, Fig. 1D).
Each central controller 12 includes a "priority logic" 10pc, which is established or changed by field engineering adjustments. When I/O channels are added to central controller 12, those channels are also added to the priority network. In this case, processor 10p has lower priority than central controller 12. The highest priority request is granted first, and as soon as it is completed, the next highest request is automatically granted. This process is repeated until all multiple requests are processed. The request is made to each central controller (when multiple central controllers are used) based on which control was granted the last request.
be accepted alternately. If the central controller does not want access, then it is granted to processor 10p.
During the progress of a data transfer operation within the first category of subsystems, the I/OC (input/output controller)
Some functions may be performed based on the type of OP code, variations, and peripherals. Typically, an I/O controller has the ability to buffer only one byte or at most one word. Therefore, when the controller's data buffer is loaded, the I/O controller or I/O
O channel units 100, 101, 102 must request memory access, and therefore the rate at which data is transferred to and from the system is limited by the rate at which peripherals can be read or written to. Mainly controlled by A second I/O subsystem using a base module with a line control processor does not have this speed limitation. When a 1/O controller requests a memory access, it is actually asking the processor to perform a series of operations.
These operations include (a) transferring a data field address from the processor's I/O channel address memory to a local address register; (b) starting a memory cycle; and (c) transferring data field addresses to and from the channel's address memory. including restoring the data field address.

The /0 controller also indicates to the processor the amount by which the address must be incremented to point to the next data field location. When an operation completes, the I/O controller creates a result descriptor (R/D) that describes how the operation was performed, and then the I/O controller writes the result descriptor (R/D) into a reserved memory location. , and then it sets the processor interrupt flip-flop. [Second I/O
Subsystem] 2nd subsystem that controls 1/O activity
In this category, input/output translator (IOT) interface devices located on the central processing unit 10 are used.

The IOT interfaces with a group of line control processors (LCPs) located on the LCP base module. Up to eight LCPs may be housed in the LCP base module.

The base module for an LCP is up to the same number as eight LCPs. The LCP is an intelligent interface device that establishes a buffered data transfer path between included peripheral devices and the main system of processors and memory. This communication path is established by the LCP when receiving a command descriptor (C/D) from the IOT, and the 10T transfers the original I/O descriptor to a command descriptor specified for the LCP. Convert. Each LCP has a large "data buffer", typically 256 words, so data can be transferred to and from a particular peripheral at the relatively low speed of the device. However, when the data buffer is filled, the data becomes
It can be transferred to the main system at the highest speed allowed by the memory speed of the main memory, which is at high speed.

The LCP base module, which accommodates up to eight LCPs, works with the IOT to establish a connection to and initiate the operation of a particular LCP.

The LCP base module also provides timing signals, maintenance logic, power and cooling, which is provided by the individual LC
Support each group of P. 10T is that part of the central processing unit which, when receiving an I/O descriptor, works with the LCP base module to determine the specific LC of the channel specified by the start 1/O command.
Establish a connection to P.

The ITO converts the I/O descriptor into a format (command/descriptor) recognized by the LCP, and when the connection is established, passes the converted descriptor to the LCP before data transmission. begins. During the time that data is being transferred between the LCP and the main system, the IOT requests memory access, address memory, and then modifies and compares its data addresses based on demand from the LCP. Furthermore, I.O.T.
controls the routing of data between the selected LCP and the main system, and it performs data conversion (ASCII/EBCDIC) if so required.
When the operation completes, the IOT receives R/D (result descriptor) information from the LCP and then stores the result descriptor in a predetermined storage location. The LCP system geometry allows up to 68 I/0 channels.

In the I/O control subsystem there are two CCs with 8 1/O controllers each for a total number of channels of only 16 (there may be a central controller; however, L
In the CP subsystem, there may be up to eight LCP base modules for one IOT.

Each base module services and carries up to eight LCPs. Therefore, one IOT serves as many as 64 LCPs. multiplex adapter is
It is used to give the effect of "2" IOTs connected to a common LCP base module. This shape may be used to improve the I/O bandpass to main memory. Every /0 system has a channel address that must be unique to itself.

Access to main memory is shared by the IOT, central controller and processor. [Configuration of FIG. 1A] In FIG. 1A, an overall system diagram showing dual categories of I/O subsystems is shown.

The first I/0 subsystem includes peripheral devices 14 and 14, respectively.
It is made up of a central controller 12 supporting 1/O controllers 13a and 13b connected to 1/O controllers 13a and 14b. This first I/0 subsystem (using a central controller) is connected to the main system 10 by an interconnect bus 11. Main system 10 is shown to include a main memory 10m, a central processing unit 10p, a memory controller 10c, and an input/output translator 10t. A PCC (Peripheral Control Cabinet) interface 101 connects via bus 5 to a peripheral control cabinet 6 which houses the central controller and I/0 controller of the first I/0 subsystem. The input/output translator 10t of the main system in FIG. 1A is 160, 161, 16
2, the second I/O through the use of LCP cabinet numbers 0, 1, 2.
form a subsystem.

Each of the LCP cabinets supports three LCP base modules O-8, e.g.
60 carries base modules 200, 201, 202, while LCP cabinet 161 supports LCP base modules 203, 204, and 205, and similarly, LCP cabinet port 62 supports LCP base modules 206 and 207. do. Each individual LCP base module is connected to the IOTIOt by a message level interface cable (MLI) 15, each of which is made up of 25 lines. [Figure 2 (LCP base module)] With reference to Figure 2, a typical LCP base module 2
00 is shown in more detail.

The base module 200 is a common distribution card 200d
, a common maintenance card 200rI1 and a common termination card 200t, plus eight line control processors (LC
P) Consists of 2000 to 2007. Distribution card 20
0d connects to a set of message level interface cables 15 that connect to LOTlOt (see Figure 5E). Each individual line control processor is connected by an output line to a particular peripheral, where LCP2OOO through 2007 are respectively connected to peripherals 50, 51, 52, 53, 54, as seen in FIG. ,55,
Connect to 56 and 57.

Although each LCP of the base module may differ slightly in some situations where the purpose is to suit the specificities of each particular peripheral that the LCP handles, each LCP has essentially the same design and functional capabilities. It is something. Referring to FIG. 2, a typical example of each LCP is found in LCP2OO6,
That LCP2OO6 is system interface 21s
i, device interface 22di, and a word buffer 2506 that can typically hold 256 words. FIG. 3 (Main System) Referring to FIG. 3, a more detailed plotter diagram of the main system is shown as it relates to the I/0LCP subsystem.

The main system 10 has a main memo 1 river 0 with a reserve section 10mi for the /0 descriptor and another reserve section 10mr for the result descriptor.
It has m. Furthermore, the main memory 10m has another reserve portion 10nc for storing the number of channels. I/O descriptors, result descriptors, and channel numbers are information used by the system for control and recognition of the state of the operation. These will be explained in more detail later. Processor 10p has local registers 10pr useful for storing information for the IOT.

The input/output translator 10t holds a channel scratch pad memo I of 0 ps. Local registers 10pr of processor 10p are used to store the start (4) and end I3) addresses of the appropriate I/O descriptors.

(In the case of the first I/0 subsystem using a central controller (Figure 1A), the 1/0C transfers these addresses to a temporary storage location called channel scratchpad memory or channel address memory. In the IOT case, the second subsystem using 0T accesses the A and B addresses directly from the memory address lines leading to the processor's local registers 10pr. A channel scratchpad note for all 64 LCPs is included in the IOT.
The channel scratch pad memory also contains the required number of channels. [Operating Correlation] A quick look at these information words and their functions, with reference to Figure 4A and the transfer of information such as between the main system 10 and a typical LCP2OOO, shows that the operating The nature of the correlation will be shown.

The operating relationships are described in the order of the index below. Index Command Descriptor ... 79 Descriptor Link ... 80 Data (Intelligence) ... 82 Result Descriptor
... 83 vertical parity words
... 83 input/output translator (IOT)
・・・ 84 start module ・・
・90 connection module...9
3 Polling test...94 Data transfer module...97 Reconnection module...100 Address store
...106 message level interface ...108 LCP state count
...113LCP Base Module Backplane Line Control Processor Polling Request Error Check (a) Vertical Parity (b) Vertical Parity Check Scripter Link (D/L) Shutdown Mode Reconnection Mode In "Write Mode"... 114 ...116 ...130 ...134 ...135 ...136 ...143 ...144 ...144 ...155 In "Reading mode" ...155 "Upper load mode ”...156 “Status” line ...157 Read mode
...in 160 write mode
...162 Command message C/M mode ...165 Reset timer R/T mode ...
・166 second command descriptor C/D mode
...166 Last word of block mode ...166 Conditional cancellation
...167 Unconditional cancellation
...167LCP functional components A-C
...170A. Peripheral terminal control section B. Data flow section C. Receipt of instructions by system logic section line control processor...194LC
Action of P: (a) System-LCP connection...19
6(b) Receiving LPW by LCP
...197(c) Receiving descriptor links and descriptor links LPW ...198 Alternative flow paths: (a) Receiving conditional cancellation commands ...199(b) Receiving transmissions from peripheral terminal units.・
・199 (c) Reception of time-out level ...200 (d) Reception of test command ...201 error condition:
...201 write operation
...202LCP action: (a) Receiving data from the system ...202(b) L
Reception of PW and blocking from system 10...
・205 (c) Data transfer to peripheral terminal device...206 (d) Request for reconnection to system 10...208 (e) Transfer of descriptor ring and descriptor link LPW...209 (f) Receiving additional data and encoding codes from the system 10...210 (g) Receiving LPW and disconnecting from the system 10...210 (h) Transferring data and encoding codes to peripheral terminal devices - ...211 (1) Request for reconnection for terminated write operation ...212 Alternative flow path: (a) Request for emergency access to system 10 ...213 (b) Ending code (AB digit) ...214 (c) Reception of end signal from system 10 ...216 (1) Reception of end signal before ending code ...216 (2) Reception of end signal after ending code ... 217 Error condition (a) Access error...220(b)
System vertical parity error...221(c) Vertical parity error...221(d) Terminal vertical parity error...222 Read operation
...222 General flow path: (a) Isolated from the main system 10 ...224 (b) Receiving and recording data from the terminal device ...224 (b-1) Receiving and perpendicular to the first character Generation of parity...226 (b-2) Storing the first character in buffer...227 (b-3) Receiving and storing the second character...228 (b-4) Additional Reception of Character and Start of Block Check Gear Lag (BCC) Accumulation...230 (c) Buffer Filled...231 (d) Request for Reconnection to System 10...
・231 (e) Transfer of descriptor link D/L and descriptor link LPW...233 (f) Transfer of data to system 10...234 (g)
Transmit vertical parity word to system 10 ・
...235 (h) Receive additional data and ending codes from peripheral terminal equipment ...236 (1) Check BCC and request for reconnection to system 10 ...238 (j) Descriptor Transfer of link D/L and descriptor printer LPW...239 (k) Transfer of data to Systema 10...239(1) LP
Transmission of W and result descriptor R/D to system 10...240 Alternative flow paths: (a) Reception of timeout level...241 (b) Transmission still expected from peripheral terminal equipment...
・242 (c) Request for emergency reconnection ...242 (d) Reception of ending code (AB digit) ...
・243 (d1) Reception of the ending code following the data ...244 (D2) Reception of only the ending code ...246 (e) Receive end signal from the system ...248 (e1) Before the ending code is received 248 e1(a) to e1(d) (E2) Receive an end signal after receiving the ending code 251 e2(a) to E2(c) Error condition: ・・・253(a) Access error...254(b) ・Vertical parity error...254(c) Program check character error...255 Write flip-read operation...255 Test operation...258 Test enable operation...259 Conditional cancellation operation...261 Echo operation
...262 Result descriptor R/D return...26
5 Offline mode...268 Online mode...Specific operations (table) that the 268LCP can perform...
269(a) writing...270(
b) Read...271(c) Write flip read...273(d) Test
...275(e) Testability
...276(f) Conditional cancellation ...2
77(g) Echo...278 Command Descriptor (Figure 4A) The command descriptor (C/D) is a modified form of the /O descriptor.

I/O descriptors are information residing in main memory 10m of FIG. 1 (and specifically 10mi of FIG. 3), which main memory 10m contains data and information regarding the type of input/output operation to be accomplished. give.
I/O descriptor modification is accomplished by 10T10t (input/output translator, Figure 1), which
lOt receives an I/O descriptor from the system memory 10m, holds an instruction part, and transfers an applicable part to CP2OOO as a command descriptor. The command descriptor has 0P code digits (
A), a 17-bit word A, B, C consisting of modified digits 1 (B), 2 (0, and 3 (D) and parity bits)
, D (Figure 4B).

However, LCP2OOO only uses the OP code digit and variant digit 1 for imperative purposes. Deformation digits 2 and 3 are always equal to O. 0P code digit prisoner is LCP2O
Defines the basic operation to be performed by OO, and modification column 1(3) specifies the modification of the basic operation.

No memory address information is sent to the LCP and system memory address functions are accomplished by 0T10t. Figure 4B contains command descriptor code for all operations that can be performed by the LCP. These operations are write,
Includes read, write flip read, test, test enable, conditional cancel, and echo. These operations will be explained later. Descriptor Link (FIG. 4A) The descriptor link (D/L) consists of two 16-bit information words followed by a vertical parity word (LPW).

Descriptor links are exchanged between 10T10t (FIG. 1) and the LCP (eg, LCP2OOO) at specific times during communication between the two devices. The contents of the descriptor link are shown in the following table. Data bits not listed are reserved for future use. Table: Descriptor printer (see also Figure 5D) Data Bit Designation A8 Prohibit access to system memory A2 Required ASCII conversion C2 base module address: 4 bits C1
Base module address: 2 bits D8 Venice module address: 1 bit D4 LCP address: 4 bits D2 LCP address: 2 bits Dl LCP address: 1 bit Data (intelligence) (Figure 4A) These are 5
A bidirectional communication line for transferring data from system 10 to an LCP, such as 2000, for possible transfer to a peripheral such as system 50, or otherwise transferring data from peripheral 50 to LCP2OOO and This is a two-way communication line for transferring the memo to the system 10 for storage in the memo I river 0m.

In FIGS. 1 and 3, these channels are message level interfaces (MLI) 15.
Data transmission between system 10 and LCP2OOO is
Except for certain transmissions which are limited to one character or transmissions at the end of an odd number of characters, they are in word format (table). Each "data word" consists of two 7-bit ASCl characters and one parity bit. Data bits A8 and C8 are not used (table). It should be noted with respect to the command descriptor that after receiving the command descriptor, but before executing the operation, LCP2OOO receives the descriptor link from 10T10t and stores it in the LCP buffer 2500. Figure 2).

When LCP2OOO disconnects from system 10 and then reconnects for further communication, a descriptor is returned to IOTlOt to identify the LCP and the operation in progress. Result descriptor (4th A)
Figure) A result descriptor is generated by LCP2OOO after the instructions contained in a command descriptor (C/D) have been executed or when an error occurs while receiving a command descriptor or descriptor link. and is sent to system 10.

The result descriptor is sent by the LCP to system 10 in 16-bit word format with parity bits. FIG. 4C shows a 16-bit format for the result descriptor, with digits A, B, C, and D each having 4 bits. Vertical Parity Word (Figure 4A) The Vertical Parity Word (LPW) is the system 10 and L
It is a 16-bit word representing the vertical parity of each transmission between CP2OOO.

LPW uses IOTlO during the transfer of information between two devices.
It is accumulated in both t and LCP2OOO. L
A PW register is provided in LCP2OOO, and LCP2O
In OO, with LCP2OOO, the accumulation of LPW provides each word being transferred to the input of the LPW register and performs a binary add operation (exclusive 0R function) without a carry. It consists of things.
When the data transfer ends, the exclusive 0R function is again performed between the LPWs of the transmitting and receiving devices.

If no echo occurred, both LPWs would be identical and the resultant value of the LPW register would be "all zeros" 4. The input/output translator (IOT) (FIG. 5C) 10T converts the system I/0 descriptor into the appropriate operational messages appropriate for each LCP.

Instead, the result message from the LCP in the form of a result descriptor is not translated by the 10T but is stored directly in the memory 10n1 in the 10mr transmitted by the LCP. The IOT performs all information transfer between the LCP and the main memory 10m needed to support the input/output capabilities of the second I/O LCP subsystem.
The /O descriptor sent from m to IOT is shown in Figure 5A.

Section 1A of this figure shows the descriptor used by the IOT to generate command messages C/M for the LCP. These can also be referred to as command descriptors C/D. Section 1B shows descriptors used by the IOT. Operations 40 to 58 are converted to LCPOP code and LC in "message" format.
Sent to P. The "L" digit of the transformation field increments the information used in the transformation digits (B, C, and D) of the descriptor information sent to the LCP. The S digit is used by the IOT as indicated by the note in section 1A of Figure 5A. Each operation shown in FIG. 5A has two OP codes, the difference being in the number of addresses used by the LCP.

The first digit of the OP code specifies the number of addresses desired.

For example, a value of 4 specifies a 2-address operation (except for "test," which has none), and a value of 5 for the first digit of the OP code specifies a 3-address operation. The second digit of the 0P code is LC as the [A] digit.
The actual 0P code sent to P is mapped.

FIG. 5B shows data field boundaries for forward and backward operations.

Sequential - System for LCP Figure 5A also shows the four types of standard operational messages used to control the LCP.

These are 1, Read 2. Write 3.Test 4. Echo (EchO).

Specific descriptor information is obtained in the form of variations with these OP codes.

"Reads" and "writes" require system memory access. All operations that do not transfer data are considered "tests." Therefore, a "test" is defined as an action occurring on an IOT that receives only result information. [Echo] is a trust test operation,
This operation causes the LCP to receive a buffer load of information from system 10 and return it to system 10 for checkout. All communications between the main system 10 and the LCP occur through a standard message level interface 15 (MLI).

Communication between this LOT and the various LCPs is
This is achieved by standard flow order common to CP. Fifth
In Figure C, IOTlOt receives the /O descriptor from processor 10p.

The IOT connects to the requested LCP channel via the distribution device 200d and sends descriptor information (command descriptor C/D) converted in a message format representing the LCP task. IOT is then L
CP becomes "driven state". This means that 10T is in LCP
and in response to various LCP conditions (including memory requests) indicated via control lines between the IOT (FIG. 4A). The IOT manages the transfer of information between main memory and the LCP. I, CP's memory request is 0T for all data transfers except that of the start.
to drive. Either 10T or LCP can initiate a connection to main memory 10m.

IOT is “Polling Test”
LCP by performing an algorithm called
(and its associated peripherals). On the other hand, the LCP initiates connections to the IOT and main memory by an algorithm called "Polling Request". Once the LCP is connected, it indicates its status via the control lines of Figure 4A. The LCP initiating the "polling request" has to compete with other LCPs in the system and has 10 m of main memory.
Connection to is permitted based on the priority rights described below. During operation, IOTlOt is disconnected from one LCP for the purpose of servicing other LCPs. 1
Message transmission between 0T and LCP includes data and control messages that are 16 bits transmitted when accompanied by vertical odd parity bits.

Following the last message, a 16-bit vertical odd parity word (LPW) is transmitted followed by a vertical odd parity bit. Parity is checked by both 0T and LCP. If parity error is LC
If detected by P, the LCP then transmits the information (
report this in the result descriptor) and stop the operation. If the IOT detects a parity error, it is inserted into the LCP result descriptor. The input/output translator 10t (IOT) consists of four major functional sections, each of which is associated with a particular aspect of human output operations.

These functional sections are shown in Figure 5C. Additionally, the operating relationships between the OT and the main system (processor and main memory) and between the LCP and peripherals are also shown. Referring to FIG. 5C, input/output translator 10t communicates with processor 10 and main memory 10m.

IOTlOt also communicates with selected LCPs and peripherals 50, such as line control processor 2000. The series of control lines in FIG. 5C are from processor 10 to initiation module 10ta1 connection module 10th, data transfer module 10tc and reconnection module 10td.
It is shown to lead to. Start Module Start module 10ta receives descriptor information, including addresses, from processor 10, and then converts the descriptor 0P code and transfers the information to LCP2O.
Assemble into usable form by OO.

The A and B addresses of the descriptor are the IOT in Figure 3.
The descriptor information is stored in the scratchpad memory 10ps, which has a memory location reserved for each designated channel, and the remainder of the descriptor information is then stored in a register (see Figure 5D) for transmission to the LCP2OOO. (as shown in ). Once the information is assembled in this "Descriptor Information Register" and the address is stored, the contents of the first register are shifted into a second identical register.
register can be cleared and the initiating module 10ta is thereby freed to receive the second descriptor. The information contained in the descriptor register of FIG. Become.

(a) LCPOP code: These are four mutually exclusive bits that are translated from the 1/O descriptor OP code by the IOT, which determine the type of operation to be initiated in its LCPOP code. Display against.

(h) LCP Variation: These are the three digits used to pass supplemental information to the LCP regarding the operation to be initiated.

(c) IOT digit: This digit specifies whether data transfer should be initiated and whether data should be converted.

(d) When a reverse flagion, this flag bit indicates that the reverse operation should be performed.

(e) LCP address: This is the processor start 1/O
Decoded from the instruction's "BF" (number of channels), this field is 3 bits that identify one of the eight LCP base modules, and is combined to select a particular LCP for the specified base module. Contains three other bits used as

(f) C-Address: This is the 6-digit C-address field (file address) of the /O descriptor.

The combination of the 10T digit, reverse flag, and LCP address is
LC to re-establish connectivity to the system following previous shutdown.
Descriptor link (D/L) used by P
Configure.

When the processor signals the IOT that all I/0 descriptors have been sent, the IOT disconnects from the processor and the initiation module 10ta passes control to the connection module 10tb. Connection module 10tb in Figure 5C is LCP2OOO
It has the purpose of establishing a communication path between a specified LCP such as and the input/output translator 10t.

The connection module 10th decodes the number of channels appearing in the processor start command, and with the decoded value,
Select a communication path to an LCP base module, such as 200 (FIG. 1A), where the desired LCP is located.
Connection module 10tb sends the LCP address to the selected LCP base module and then
A base module such as 0 is turned into a signal to start a "polling test". Polling test "Polling test"
The boring test algorithm is the algorithm used by the LCP base module to establish a connection between the CP and the boring test algorithm (the connection initiated by the LCP). Contrast this with an algorithm called "Polling Request".

) Once the connection between the LCP base module and a particular LCP is established, the base module, such as 200 in FIGS. 1A and 2, becomes transparent to data transfer between the LCP and the IOT. The "polling test" algorithm also checks for priority, transmission errors, and busy conditions, any of which, if detected, aborts the connection attempt. If the connection attempt is successful, the particular LCP remains connected to the IOTlOt until the connection is terminated by the IOT.

LCP base module is selected LCP and IOT
It takes no further function in communication between the two. During the progress of an attempted connection, a condition is detected that stops or aborts the connection attempt, so that the existing condition is reported in the IOT result/descriptor.

The format of the condition detected and reported is shown below. (
a) The addressed channel does not contain an LCP or the channel's LCP is offline.

(b) The LCP of the particular channel addressed is '
(i.e. the LCP state is not 2 or 3; the use of [state count] is discussed below). (c
) The port is in use in that the base module is currently connected to the system 10, i.e., some other L
It is CP.

(d) The LCP address has a parity error within it.

0T and base module distribution control means for specific LC
When using the 'polling test' for connection to P,
If the polling test results in a connection to that LCP, IOTlOt connects the descriptor link (D/L),
Transmit the LCPOP code and variant and C address to the selected LCP.

After receiving this information, the LCP signals the IOTlOt whether it is disconnected or whether it is now ready to start transferring data.
Typically, a "write" operation (data from main memory 10m to a peripheral device such as peripheral device 50)
The LCP selected by requests "data transfer",
A "read" operation, on the other hand, typically results in a blockage. If data transfer is requested, connection module 10tb passes control to data transfer module 10tc.

If LCP2OOO is blocked, then LC
Communication between P2OOO and IOTlOt is stopped until LCP requests to re-establish communication via reconnection module 10td. Data Transfer Module In Figure 5C, data transfer module 10tc is I
LCP2OO connected used by OTlOt
10m and main memory 10m.

The LCP may be in the connected state as a direct result of the action of the connection module 10tb or as a result of the action of the reconnection module 10td, in either case the operation of the data transfer module 10tc being the same. When control is passed to the data transfer module 10tc, the A and B addresses of the descriptors are retrieved from the IOT scratchpad memory 10ps of FIG.
by ta or data transfer module 1 of FIG. 5C.
Stored by 0tc at the end of a preceding data transfer operation. A memory access request is made and the A address is from IOTlOt to main system 1 in Figure 3.
0 processor memory address register 10pam. In Figure 5C, assuming that a "write" operation is in progress, data from the memory storage location identified by address A is bussed to IOT data transfer module 10tc via Bm. Ru.

Once in the module, the data is transformed (if specified by a descriptor) and used to generate vertical parity, and then accompanied by a strobe pulse. Gated via bus Bg to the selected LCP, such as LCP2OOO. L.C.
When P2OOO receives data, it acknowledges its reception by sending a strobe pulse back to IOTlOt. While the data transfer from memory 10m to LCP2OOO is occurring, IOTlOt increments the A address and compares it against the B address.

If A address is smaller than B address, LCP2O
Another memory access is requested by receiving a recognized strobe pulse from OO and the data transfer sequence can continue. When the LCP buffer, such as 2500 in FIG. memory 10
ps (Figure 3), after which it terminates the connection between IOT and LCP. An LCP such as LCP2OOO begins transmitting data with its peripheral 50 via its Bp, and 0T10t is now free to connect to another LCP. The data buffer 2500
When transferring the contents of LCP2OOO to the peripheral device 50,
requests re-establishment of the data path to main memory 10m. This re-establishment is handled by LCP base module 200 and 10T reconnection module 10td.
To increase the overall speed of input/output (1/0) activity, the 0T10t may optionally include an IOT multiplexer.

This multiplexer enables the IOT to service the LCP for those memory cycles that would otherwise be lost while the IOT is busy in some non-memory function. . After an LCP such as the reconnection module 2000 is connected to the IOTlOt and receives a command descriptor (C/D) and a descriptor link (D/L), the LCP2OO
O may be disconnected from the system for the purpose of communicating with its associated peripherals, such as device 50.

Now, if the LCP subsequently requests access to memory 10m, it sends the request to base module 200. The algorithm called "polling request" is L
The CP base module (in response to LCP's request)
This is a method of attempting to connect CP to 0T10t. The base module distribution card contains hardwired logic to accomplish this. The purpose of the reconnection module 10td is to acknowledge the "polling request" and reestablish the data path to 0T10t. During the reconnection attempt,
The reconnection module 10td, working in conjunction with a base module such as 200 and 200, resolves any priority conflicts that arise between the various requesting LCPs.

When the priority is resolved, the reconnection module establishes a data path from the requesting LCP to main memory 10m. Once the data path is re-established, the LCP returns the descriptor link to the IOTlOt. (The descriptor link is connected to the LCP during the original connection sequence.)
(first passed to 2OOO). base module 20
0 takes no further function in LCP-10T communications. Following the transfer of the descriptor link, reconnection module 10td busses control to data transfer module 10tc. 10T10t must have the ability to receive, store, and modify data field addresses for the purpose of transferring data to and from modified memory storage locations.

Main memory 10m has 2 million digits (address O to 1)
, 999, 999) and because the various input/output devices may directly address memory 10m, the /O descriptor data field address must be seven digits long.

I/O descriptor data field address is MO
It must be either D2 or MOD4 (modulus is abbreviated as MOD) and no odd addresses are allowed. Since odd addresses are not allowed, the least significant bit of the least significant digit is not required. Furthermore, since the least significant digit can only be a "1" or an "O", only one bit is needed for the digit position. From these facts it is possible to construct a 7 digit address using 24 bits. The format for the I/0 descriptor data field address is shown in the table below. 1/0
Descriptor Data Field Address Note: The field must be zero to indicate that the bit is not used.

In the address, digit G may be 1 or O,
Digits B through F may be any decimal value (0 through 9), and digit A may be any even decimal value (O through 8).
).

As shown in FIG. 3, IOTlOt has 10 ps of scratchpad memory.

This is shown in more detail in Figure 5F. The IOT contains 256 words of scratchpad memory, each word being 24 bits long. As seen in Figure 5F,
Scratchpad memory is divided into five major areas. The areas marked A and B are used to store the starting and ending (B) addresses of the memory data field, both of which are 24 bits long. The areas marked EXRDW1 and EXRDW2 are used to store extended result descriptors, where each of these words is 16 bits long. The area marked "temporary storage" is used to store flags representing errors detected during IOT operations.
When a result descriptor is assembled, information from temporary storage is added to any existing result descriptor information. Each of the five main areas is one for each channel.
each is subdivided into 64 separate storage locations.

The scratch pad storage location includes the number of base modules, number of LCPs, and terminal address flag (ADDRSB).
, as well as the extended result descriptor flag (EX
RDWl). The six least significant bits of the scratchpad address (base module number and LCP number◆ are extracted from the BF part of the processor start instruction (BFA radix,
BFB=LCP number). The EXRDWl signal is generated by IOTlOt whenever access is required either to the expanded result descriptor word or to temporary storage. ADDRESB is
It is generated by 10T whenever an access is required to the B address or to the second extended result descriptor area. Scratch pad 1
0 ps memory element is 24 RAM (256×
1), which are organized into a 64x4x24 array (64 channels, 4 words per channel, 24 bits per word).

As seen in Figure 5G, the 8-bit address bus Bad
, all RAMs 6OO, 6Ol, etc. in the array as they go to writeable line 68
... Go to 6024. Each RAM has one data input line and one data output line, and these individual data lines are combined to form data input (RAMIN) 701 and data output (RAMOUT) 700 buses, respectively. When a scratchpad address is applied to the array and write enable is enabled, data on the 10T address bus is written to RAM.

For the purpose of reading from the scratchpad, the desired memory location must be specified with a scratchpad address and 'readable' must be enabled. The requested data is then transferred from the scratch pad to the IOT.
Transferred to address bus. During execution of the address store start 1/O instruction, processor 10p constructs the start A and end B addresses of the data field.

The processor then transfers the complete A address from processor register 10pr to the IOT address bus. IOT
At the appropriate point in the start sequence, the IOT generates the appropriate signals and then gates the base module and LCP address bits to the scratchpad 10ps.
Now in the scratchpad memory location of the addressed channel and with write enable active, the A address can be written to the scratchpad. Following this, processor 10p places the terminal B address on the IOT address and the IOT generates the appropriate control signals along with the base module and LCP address. However, at this time the IOT also generates ADDRESB, which causes the address on the bus to be written to the B address area of the scratchpad (Figure 5F). The start and end addresses of the data field are now stored in the channel's address memory clutch pad 10ps. When a data transfer operation begins, these scratchpad storage locations are accessed by data transfer module 10tc (Figure 5C). Message Level Interface As described above with reference to FIG.
It is also typical of other base modules in that each individual base module includes a distribution card 200d that services up to eight LCPs.

Furthermore, each LCP base module has a maintenance card such as 200m and a terminal card 200t. Each LC
Distribution card for P base module is main system 1
0 LCP base module and the input/output translator 10t.

As seen in FIG. 2, the message level interface 15 provides the IOT1Ot channel from each LCP base module by 25 lines. These lines are shown in Figure 5E. The function of each of these individually identified lines is listed in the table below.
20 of certain LCP base modules such as 200
Connecting a distribution card like 0d to IOTlOt25
A message level interface 15 (MLI), consisting of two signal lines, defines the signals presented to the 10T as standard, regardless of the logic and operational variations found in different types of LCPs. give a guarantee.

It will be noted that some of the MLI signal lines 15 shown in FIG. 5E are bidirectional and assigned to multiple functions based on the signal source and LCP status (connected or disconnected). The distribution card 200d for a given LCP base module is used to provide part of the message level interface between the 0T and the individual LCPs within the base module. The distribution card also includes an IOT connectivity module 10tb to establish a data path to a specific LCP (polling test).
and works with the 10T reconnection module 10td to establish a path from that particular LCP to the IOT (Polling Request) based on a request by the LCP. LCP State Count During the time a particular ICP is connected, it follows standard communication procedures with the IOT.

Although the sequence of events followed in the communication procedure is not the same for all LCPs, the events that occur at any point in the sequence are the same. The steps in the sequence numbered 0 to 15 are called ``state counts'' and are transmitted to the IOT. Each time the IOT receives a strobe pulse from the LCP, it examines the "state count" and takes appropriate action based on the state count. A more detailed explanation of the sequence and use of state counts will be provided below. FIG. 6A is a diagram showing the various state counts and the logic flow they contain. A more detailed explanation of this logic and state counts will be provided below. L
CP base module backplane (Backplane) Local common backplane is LCP base module 20
0, 201, 202, etc., respectively.

Each backplane connects to all eight LCPs of the base module. The backplane is configured such that all signal lines are busbared to the length of the backplane, thus making each line available to all LCPs in its base module. Signal L
From the individual locations of the CPs, these backplane lines take two general forms: (a) they go to the distribution cards and onto the IOT, and (b) they go to the maintenance and terminal cards. Proceed to. Except for the various clock and voltage lines, those lines to the maintenance card (eg, 200m in FIG. 2) are used for local or offline maintenance functions. Some of those lines going to the distribution card and onto the IOT, such as data and parity lines, must be gated to individual LCPs.

This gating is enabled only when the LCP is in the "connected" state, and is disabled when the LCP is disconnected. When the LCP is able to transfer data between the IOT and itself, the LCP
"Connected" state. The "blocked" state of an LCP is when the LCP is disconnected from the IOT, but is now able to transfer data between itself and its peripherals. In addition to the gated lines, there are several lines each dedicated to an individual LCP, e.g.
There is a line going from the distribution card to only one LCP.

Those lines that do not require any gating are used for signals such as LCP requests for reconnection or LCP address lines. During the time an LCP is connected to the IOT, the LCP has exclusive access to the base module backplane. IOT-LC
It is during this "connected" time that P data transfers occur. Upon cessation of data transfer, the LCP disconnects from both the OT and base module backplanes, thus freeing them for use by other LCPs in the system. Once disconnected, the LCP is free to communicate with associated peripherals, such as device 50, via the front plane. When a broken LCP needs its connection to 0T to be re-established, it sends a request signal over one of its dedicated backplane lines to a distribution card such as 200d. send. Upon receipt of the LOP request, the distribution card initiates the "Polling Request" algorithm and initiates the IOT reconnection module 10td of FIG. 5C. A line control processor LCP, or line control processor, is a device used as an interface device between certain peripheral devices and the main system.

LCPs come in a wide variety of formats, each designed to work with a particular type of peripheral device. Since peripheral devices differ in their operational characteristics, L
The CP is devised to be able to handle, control and specifically adapt its own specific peripherals. However, L
There are certain general characteristics of CP interface devices. Basically, the common characteristics of each LCP are the ability to convert serial data to parallel data or parallel data to serial data, and the ability to convert from character word format to format or word character graph format. and the ability to recognize and adopt appropriate actions in response to certain standard control characters or signals. A generalized program diagram of the line control processor is shown in FIG. 6B, which also shows its relationship to distribution card device 200d and IOTlOt. If the LCP is assumed to be in the ``connected'' state and a ``write'' operation has been initiated, data from 10T10t enters the LCP via backplane receiver 23r. . Multiplexer 24x1 is used to select the Data Source for the operation, which in this case is 10T10t. multiplexer 24x1
The control is performed by the selector 24s. The output of multiplexer 24x1 is bussed to an LPW (vertical parity word) circuit 24w and to multiplexer 24x2, which receives data from multiplexer 24x1 under the control of MUX2 control 242s, which is controlled by processor logic 53p. Gate to data buffer 2500.

The LCP continues to run until the data buffer 2500 is filled.
Continue to receive data from OTlOt. During the period when the LCP is receiving data, the LPW circuit 24w generates the LPW sum, and then when the transmission ends, the IOT
lOt is a vertical parity word (
LPW).

Circuit 24w must be cleared or an error will be displayed.
When the data buffer 2500 is filled, the LCP:
Having disconnected from the main system (IOT) by disabling its backplane transmitter driver 23x and backplane receiver 23r, the LCP then disables its frontplane transmitter driver 28x and frontplane receiver 28r. Activation establishes a data path to the peripheral device, e.g.

Once this path is established, the LCP uses multiplexer 27x to transfer data (
Peripheral 5
0. Multiplexer 27x is controlled by MUX3 control 24sc, which is controlled by processor logic 53p. Transmission continues until the data buffer 2500 is empty, at which time the LCP requests a "reconnect" (to the IOT) to store the result descriptor or request more data. If a "read" operation is in progress and the LC
If P is disconnected from the main system (0T), data from peripheral 50 enters the LCP via frontplane receiver 28r.

The output of receiver 28r is bussed to multiplexer 24x1, which now serves as a "data source" to peripheral device 50 (
(via front plane receiver 28r).
The output of multiplexer 24x1 bypasses LPW circuit 24w and goes to multiplexer 24x2, which selects multiplexer 24x1 as an input to data buffer 2500. When data buffer 2500 is filled, frontplane receiver 28r and frontplane drive 28x are disabled and LCP is
Reconnect to OTlOt and backplane receiver 23
r and backplane drive 23x are activated. LCP is now transferring data from data buffer 2500,
Via multiplexer 24x and drive 23x,
The transmission (to the main system 10) begins to be transmitted to the IOTlOt.

During this transmission, the output of multiplexer 27x also passes through multiplexer 24x1 to LPW circuit 24w. When the data buffer 2500 becomes empty, the LCP
sends a signal to 10T10t and vertical parity word LPW
is incoming, after which it passes through multiplexer 27x and driver 23x to IO
Gate the final LPW sum into TlOt. After transmitting the longitudinal parity word (LPW), the LCP communicates with the main system (
IOT) or if there is no further data, the LCP may store the result descriptor and proceed to the "idle" state.

In the operations described above, information data could be transferred between the LCP and the peripheral in the form of bits, characters, or words, depending on the type of peripheral involved.

The method of data transmission is typically controlled by the type of peripheral device used. Typically, information data is transferred between the LCP and the IOTlOt as "words";
In the case of character transfer, for example, the first or last character of the transmission.

These data transfers between the IOTIOt and the LCP of FIG. 6B are controlled by the exchange of strobe pulses and recognition by the IOTIOt of the LCP "state count" (described below). As introduced earlier, the state count (') of the LCP provides standardized information that is transmitted to the 0T10t and by which the IOT performs the following appropriate actions based on the state count information. be able to.

During the time the LCP is "connected" to the main system,
It follows standard communication procedures at JIOTlOt.

Sequence of dependent events in a communication procedure (') A particular event that occurs at any point in the sequence of a communication procedure ('all similar, numbered 0 to 15), even if not identical for all LCPs. The steps in the communication sequence (referred to as “state counts” and designated as “STC”). These state counts are transmitted to the
0T10t('), examines the state count (STC) each time it receives a strobe pulse from the LCP, and based on that state count, the IOT(') can take the appropriate action. Referring to the table, each state count (one that has a specific function and
It will be seen that the state count has different exits based on the type of LCP and descriptor involved.

The table below briefly explains the various LCP state counts.
can only be kept.

STC=111/O descriptor LPWOLCP is
I/O received at STC=2 or STC-3
Receive and check LPW for descriptor.

I/0 descriptor is converted by IOT command disk after It became known as Puta.

STC=12 break.

There is no more data to be transferred. LPW is transmitted and checked.

STC=13 break possible.

Data transfer is stopped: LCP is requesting a return to STC-8 (filling) or STC-4 (reading).

STC-14 character transfer.

The last transmission (') consists of one character instead of one word.

STC=15 Result descriptor LPWOLCP (d Send LPW to IOT for result descriptor.

Referring to FIG. 5C, processor 10p starts a chain of input/output operations by executing a start 1/0 instruction.

, in which case the processor sends certain information, including the desired number of LCP channels, to the 0T start module 10t of FIG. 5C.
Pass it to a. The channel number is decoded to determine the base module number and the address of the LCP, which are then passed to the connection module 10tb. Sends a signal (channel selection) to the appropriate distribution card for LCP 200, e.g. 200d, requesting that a connection attempt be made. means for the main system to be explored, which further includes the distribution card 200d
This method attempts to connect to a specific LCP in response to a connection request. Following the transmission of “channel selection”,
The IOT sends the address of the desired LCP to the distribution card in the selected base module (at the same time)1
0T sends "address selection" to all base modules of the system.

A distribution card that receives both address selection and channel selection initiates a "boring test" and responds to the IOT in an "LCP strobe", and a distribution card that receives only address selection (") signals it as an "in-use" signal. thoughts, and are prohibited from communicating with them (JIOT.10
When T10t receives the LCP strobe, it drops channel selection.

Distribution card is "address selection" and "channel selection"
When a signal is received, a signal is generated which enables the LCP address to be placed in the LCP address register of the distribution card.

The BCD (binary-coded decimal) output of the LCP address register (') is decoded to enable one of eight lines, each line (representing one LCP of the J base module). When it detects that a line is active, its LCP responds to the distribution card with a signal LCPCON, meaning "LCP Connected." When this connected signal is received in the distribution card, the connection flip-flop (CON ) is set.
I/0 transmission line (IOSND) from connected LCP
Based on the state of this (1) drive the control line to receive or transmit data as between LCP and IOT (Figure 6C), the distribution card selects the channel. If we detect the absence of
It responds to 0T in the state of LOP due to costrobe.
LCP is now connected to 10T and will remain connected until IOT drops address selection, distribution card is 0
It plays no further role in T-LCP communications. The above events indicate the steps leading to a successful ``connection'' attempt, which, however, would have failed for one of the following reasons. (The LCP at the false address storage location was offline.) (b) LC
P was in use, i.e. LCP state count was O.
It wasn't, it was (''2, and it was (''3).

(c) The boat was in use, ie the second distribution card in the base module was in use.

(d) A parity error was detected at the address.

Upon detection of any of these errors, the connection attempt is aborted and a result descriptor representing the type of failure is written and sent to the main system in memory 10mr (FIG. 3).

In subsequent discussions, reference may sometimes be made to specific flip-flops and signal levels not specifically shown in the process diagrams. The design and use of such elements is well known, and it would be redundant and overly complex to list all such elements.
After being connected to Ot and receiving the command descriptor and descriptor link, it may be "cut off" from the main system 10 to communicate with its associated peripherals, e.g.

If the LCP then needs access to memory 10m, it sends a request (LCPRQ) to the distribution card. [Polling request] (d1 distribution card is LC
This method attempts to connect the LCP to the IOT in response to a P request. A number of events occur during a "boring request" operation. Moshi base module 20
If several (7) 1, CPs in 0 request access at the same time, the distribution card 200d (J) determines which of them should gain access by checking their priority level. Therefore, the requesting LCP with the highest priority level (selected in the facility period) is given access to the distribution card.

This priority level (') is referred to as "base priority" because it includes which LCP has what level of priority as one of the eight LCPs in that particular base module. Once the ``base priority'' is determined, the distribution card assigns ``overall priority'' (which was also assigned and selected by the equipment period) to the requesting LCP.

"Overall Priority"('establishes a priority rank between different base modules in the overall system, rather than establishing a priority rank for LCPs in one base module. LC
Contains a series of pin or socket type connections connected to P. These pin-to-socket connections are routed (by the field engineer) to a priority encoder which assigns an internal base priority number from O (lowest) to 7 (highest) for each LCP. Therefore,
If several LCPs of the same base module request connection at the same time, distributed card control means ('LCP with highest priority)
Penetrate P. Another pin-socket on the distribution card
The set (J is connected to each LCP. These are "linked" and "bound" by the field engineer, so that each LCP ("[overall" and (") is given an external priority number, The input/output translator interface of the main system selects one of the LCPs on different base modules of the system.In this way, when an "overall" priority number is received by the IOP, and the other base module When there are simultaneous requests from other LCPs in Yule, the IOP(') selects the LCP with the highest overall priority number, but this only occurs after the internal base priority has been determined by the distribution card. Related Those distribution cards receiving requests from the LCPs each send an "interrupt signal" (IP+ST4) to 10T10t.

(See Figure 5E and Table Message Level Interface). When 10T10t detects signal 1P+ST4, it initiates a "reconnect" sequence and sends a signal (access granted) to all base modules of the system.

The "Access Allowed" signal allows IP+ST4 to
Those distribution cards sent to the OTlOt initiate their respective "Poll Request" algorithms. In response to the "access granted" signal, the requesting distribution cards send their respective global priorities to 10T10t.

0T compares the overall priorities of the requesting distribution cards (i.e., sends a channel selection signal to the requesting distribution card, which has the highest overall priority after one clock time). ) and the IOT sends an address selection signal to all distribution cards in the system.

A distribution card (that receives both “channel selection” and “address selection”) responds to the IOT with an LCP strobe,
It then sets its LCP address flip-flop, thus driving the particular address line of the LCP it is requesting. LCP('', when it detects that the address line it owns is active, it responds to the distribution card with a JLCP connected signal (LCPCON). When receiving an LCP strobe, the IOT
lOt('drops the 'Access Allowed' signal and 'Channel Selection' signal, and detects that the distribution card does not have 'Address Allowed' and 'Channel Selection', and the LCPCO
When it detects that there is an N, it accepts the connection to be completed and responds to the IOT with an LCP strobe with an LC'P status count and a descriptor link. Bowling request ('' now completed, distribution card ('')
It has no involvement in LCP-0T communication.

The LCP and 0T continue in a reconnection sequence until the LCP is connected, after which control is passed to the IOT data transfer module 10tc (Figure 5C). LCP is 0
It remains connected until such time as T drops its "address select" signal. Error Check OT and each transmission between specific LCPs is checked for errors.

The error checking method used is to (a) perform a vertical parity check on each transmitted word; and (b) perform a vertical parity check on each transmitted word.
) Checking vertical parity on each transmitted block. (a) Vertical Parity In a "read" operation, the LCP sends information to IOTlOt on the 16 Message Level Interface (MLI) data lines (Figure 5E), which is on the MLI parity line (Figure 5E). Accompanied by parity bits.

The data and parity line (') go to the parity generator checker on the IOT base driver card. In a 'read' operation, the parity generator checker is used to count the number of 1 bits on the MLI data and parity line. If the total number of 1 bits (including the parity bit) is odd, the parity is correct and a signal term from parity generator 48 (PAROKl Figure 6D) is generated. If is even, PAR
No OK signal is generated and the PA
The absence of RCK sets 10T (vertical parity error flip-flop (VPERRF)).

Similarly, in a "write" operation, the 16 data lines from the main system 10 are bussed to the parity generator checker on the 0T base driver card.

The data on 16 lines (1) are examined and if an even number of 1 bits is detected, the term PARGEN is generated.

This PARGEN signal (used to force a ``1'' bit onto the Message Level Interface parity line to accompany the parity data to the LCP).On the LCP-based distribution card, the state of the parity bit is The parity generator checker circuit (inspects the status of 16 data lines and generates PAROK if the total number of 1 bits (including parity) is an odd number. (b) Vertical parity check Vertical parity check A check is an error detection method in which a check word generated by a transmitting device is compared with a check word generated in the same manner by a receiving device.

These check words (') are generated by treating each word in a transmission as a 16-bit number and then performing an exclusive 0R operation (carryless binary addition) of each word in that transmission. When the sending or transmitting device (') has assembled a check word, it sends it to the receiving device. If there were no errors in the transmission, the check word from the transmitting device is added to the check word of the receiving device. “O
”. Thus, if the sum is not "O", the vertical parity error flip-flop is flagged (LPERRE).As discussed in connection with FIG. 6B, the LCP (false LPW circuit 24w) established.

Similarly, IOTlOt has a vertical parity check circuit. This circuit connects in parallel paths to the data buses shown as the 16 lines at the bottom of Figure 5E. A line control processor (LCP), e.g. element 2000, is
better understood with reference to Figure 6C, Figure 6C ('L
Figure 2 depicts a basic program diagram of the major elements involved, as well as certain detailed descriptions of RAM buffers such as the CP2OOO 2500.

The LCP buffer 2500 is a random access memory (R
AM), and this RAM (') is functionally 256 bits (0-255) wide and 18 bits deep.

It can therefore hold 256 words of 18 bits each. In one exemplary embodiment, it can hold 256 words of 18 bits each.
A section 25a designated by buffer A giving a vertical word of 0, another section designated by 25xi, and a command descriptor C/ designated by 25c.
D section, a buffer area B, 25b (i.e., from address 128 to address 218), which is typically ι190 words long, and another designated by 25x2.
a buffer area, a checker scripter R/D area 25r, and another area specified by 25x3,
It has a descriptor link D/L area designated by 25d. A RAM buffer 2500 ('') is addressed by a memory address register 36 having a system address register section 36s and a device address register section 36d;
and 36d communicate to buffer 250 via 8-bit address bus B8.

The RAM buffer 2500111 (1) consists of 16 bits in the vertical direction (Figure 6C), a parity bit, and an 18th bit called the "end flag bit", which is a storage section designated as 25e. It is in ``Data Bus Line'' 47
ι', data input and Gives an output channel. System interface logic 21si, device interface 22di
, and common logic 22c schematically illustrate the programs that refer to the more specific elements described with respect to FIG. 6D. Referring to FIG. 6F, a "message block" of the type used in the LCD buffer 2500 of FIG. 6C is shown.
is shown.

As mentioned in the discussion of FIG. 6C regarding the RAM buffer 2500, this is a message block typically (1 'n'words); 90) and also 3 words may be provided for the result descriptor R/D and 3 words for the command descriptor C/D.
A word memory location may be provided and there may be one word memory location for command message C/M.

Figure 6F ("also shows the basic word format,
In that format, one word consists of four digits,
The four digits ι' A, B, C and D, plus V
The parity bit is labeled PB (vertical parity bit), resulting in a total number of bits, typically 17 bits per word. As seen in Figure 6F, the 4 digits A, B, C and Dι1 each contain "8" bits and "4" bits.
It is organized from 4 bits, designated as bit, ``2'' bit, and ``1'' bit.

In FIG. 6C, buffer 2500 is also provided with an 18th bit, or "end flag" bit, which is placed in the memory location shown at 25e in FIG. 6C.

The central system also communicates with peripheral terminal devices via the LCP.

A command descriptor C accepted from the main system 10 provides a means for transmitting control information and data from the main system 10 to a peripheral terminal, e.g. 50, and vice versa. /
D and, if it is sensitive to that particular command, sets itself up to perform the required operation. It also transfers the same command descriptor C/D that is not changed to the peripheral terminal device.Peripheral terminal device I' command descriptor C
/D, and result descriptor R/D.
is returned to the main system 1ro via the LCP. The message block and word format are representative of the command descriptor C/D and result descriptor R/D (LCP) shown in FIG. Receives the command descriptor C/D. Because of the total number (4 digits per word), 4 digits are received per transmission, including the two least significant digits (''all O's).

In each word ('', there is a vertical parity bit (VPB) and every C/D ('' is subordinated by a vertical parity word (LPW). If a parity error is detected during the transmission of the C/D If so, the LCP(') results in a descriptor R/D mode and the descriptor error reports to the main system 10.The random access memory buffer 2500 (RAM of the LCP) is stored in the LCP, i.e., the line leg processor. Buffer all command descriptors, vertical parity bits and parity words. Examine the first word of the command descriptor C/D and determine whether it is ECHOOP, HOSTLOADOP,
Also, it is determined whether the (lie READNO time has expired 0P).

If it is one of these, it sets the appropriate flag.
L) Following reception of the command descriptor C/D, the line restraint processor LCP activates the descriptor link D/L.
Proceed to receive.

This is subordinated by the vertical parity word LPW to 2
It is a word transmission. If there is an error, the LCP branches to the Result Descriptor R/D mode and reports the descriptor error to the system 10. Batsuhua (
A random access memory RAM (eg 2500) serves as a buffer for all descriptor links D/L, vertical parity bits (VPB) and vertical parity words LPW. Shutdown mode descriptor link D
Following reception of /L, the LCP proceeds to "Shutdown Mode".

Reconnect Mode If it is ECHOOP, go to Line Control Processor LCP (''Reconnect Mode'' and ECHOOP
Start the operation based on the ECHO
OP involves receiving two buffers of data (180 bytes each and 90 words of 16 bits) and transmitting the same data back to system memory 10m.

If it is something other than ECHOOP, LCP
(1) Check the readiness of the peripheral device. If the peripheral device is in the "not ready" state, branch to the LCP (" result descriptor R/D mode and report this to the system 10. If it is 'ready', it begins communicating the LCP(' command descriptor C/D to the peripheral, while simultaneously branching to the 'idle' state and making itself available for a possible 'conditional cancellation 0P'. The line control cape process is stopped in this "idle" state until one of the following two states occurs.The two things are as follows: 1. Peripheral devices sets up the line control processor LCP to the "data transfer" state.

2. The system 10 communicates ``conditional cancellation 0P'' and (1 unconditional cancellation.

If it is a number greater than or equal to 2, it receives one word from the system 10 subordinated by the line parity word LPW, and the LCP ('
Determine whether it is a valid conditional cancellation OP.

In some cases, LCP (J communicates this to the peripheral device. If such a case contains a number greater than 1, L
The CP branches back to the "blocked" state, where the L
Data transfer between the CP and its peripherals can occur. After transmitting the command descriptor C/D to the peripheral, it is driven by the LCP (1 peripheral [state]), which state defines the mode of operation and memory requirements.

Data (1) is transferred in a ``message block'' with a 16-bit vertical parity word (LPW) following each block and with a parity bit for each word (except in the case of disk pack control devices). ” segment).If the line-based processor LCP detects an error in the data received from the peripheral and from the main system 10, it reports the information to the peripheral and then sends it to the result descriptor. Branches to the R/D mode and reports it to the main system 10. In the "read" mode, data transfer between the line control processor LCP and the peripheral (depending on the requirements of the peripheral).

On the other hand, the data transfer between the LCP and the main memory 10m depends on the memory access speed of the main system 10.
Because it operates in peripheral ('stream') mode, and because the LCP must compete with other LCPs for access to memory, the LCP uses its two buffer areas to match the transfer rate of the peripheral. The table below shows a certain form of command descriptor C/D, and this descriptor C/D ('
Used by and acted upon by LCP.

All other C/Ds (transparent to 1 LCP and passed to peripherals; table command descriptor LCP(', next determined by testing the first word of C/D) Transparent to all command descriptors except when:

1. ECH00P (bit A1 ('' is the truth value)2.
H0STL0AD (A4 and B8 are truth values) 3
．． READN0TA timeout) (A8 and B8 are truth values)4. Conditional cancellation 0P (A2 and B8 are true (b)) 5. The OP code digits of unconditional cancellation C/D are defined as follows.

Read (A8) Any operation in which data is transmitted from the LCP buffer to the main system.

(1000) Write (A4) Any operation in which data is transferred from main system memory to the LCP buffer.

(0100) Test (A2) Any operation that does not cause any data transfer between LCP and system memory, but results in R/D storage of system memory.

(0010) Echo (A1) An operation that receives a message block from system memory and transmits the same block back to system memory.

(0001) Typically (') Result Descriptor R/D is generated by a peripheral and received by a 1, 2 or 3 word LCP.

When the LCP generates an R/D, only one word is sent to the main system 10. The table shows the conditions for LCP to generate result descriptors. υ１ \Nono′
Referring to FIG. 6C with respect to the lines between the device interface 22di and the peripheral device, the peripheral device unit is provided with a port interface (denoted as a DDP or device dependent port interface 50d). , this interface 50d(') is adapted to suit the requirements of each particular type of peripheral device.

LCP communicates to peripherals via DDP in an asynchronous mode.

A ``write'' operation (defined as a J transfer, where (1, LCP is writing to a peripheral unit).
A "read" operation (1, defined as a transfer where the LCP is reading from a peripheral unit. Referring to FIG. Ori and LC
When P writes 1 to a peripheral unit, this signal (
' is an asynchronous level, which means there is data on the data line.

This level (') is deactivated by the peripheral unit sending DML/(peripheral message level) and by sending ('DINTL/(peripheral device interrupt level)) to the LCP. Scripter R
When reading data on /D, this HTCL
The / signal is an asynchronous acknowledgment that the data on the data line was being received by the line stopping processor LCP.

When receiving this level, peripheral device units (1DML
/also ('DINTL/ must be deactivated. When a peripheral unit causes deactivation of DML/ or ('DINTL/), the LCP deactivates 1ITCL/ (upper transfer control level). When driving the LCP into command message C/M mode, the upper transfer control level HTCL/ is sent to the peripheral unit when the LCP buffer is empty and no system termination is detected. A change in state must be responded to by the peripheral unit on the line labeled HINTL/ in FIG.
Used by the LCP to indicate to peripherals that the CP wants to interrupt operations.

This level of response by the peripheral (must be DINTL/ and a change of state, whereas the LCP (
' responds by deactivating its upper transfer control level HINTL/. Following detection of the trailing edge of HINTL/, a new mode of operation is illustrated by the status lines shown on FIG. 6C as LCP('', ST-4/, ST-2/, ST-1/). In response to an interrupt from the system 10 (') when driven in 'write' mode, the upper interrupt level HINTL/ indicates that the last word of data has been completed and that LPW is on bus 47.
This means that it is on the data line.

It is necessary to respond to the peripheral unit ('DINTL/) and its interrupt with a change in state. In the 'read' mode, when detecting the LCP (''read end command', the LCP (lie) upper interrupt level HINTL/ is driven to 1. do.

Command message In C/M mode, LCP (''
, drives the upper interrupt level HINTL/ if ``Read End'' is detected.The line in FIG. ('' Indicates "upper clear" indicating to peripheral units that a parity error has occurred during reading. Combination of upper transfer system level and upper interrupt level (HTCL/-
HINTL/)('' indicates that there is an upper load command descriptor C/D for the peripheral unit.

Peripheral unit ('', DINTL/(peripheral interrupt level)
Line and state counts ST signed as
=2 and LCP(is HTC
Acknowledge by deactivating both levels of L/HINTL/. Following the trailing edge of DINTL/, LCP
transfers data in "write mode". In FIG. 6C, a bidirectional data bus Bd is provided, and the bus Bd
It has 16 data lines and parity lines between the LCP and the peripheral units. When constrained by the LCP, these lines
It is active as long as CL/ is active. When control is held by a peripheral unit, these lines are active as long as peripheral message level DML/ is active. The direction of transfer is determined by the status of peripheral units. The line denoted by DML/ indicates the peripheral device message level and is a unidirectional line.LCP
When reading data from the peripheral unit to the LCP or (1 result descriptor R/D), the peripheral device message level DML/(' is used as a transient signal to indicate that there is decision data on the data line.
When the peripheral receives the command descriptor C/D or (' data from the LCP), this signal is used as an acknowledgment level for the DML/(' data. The peripheral (via its port interface) (' DINTL/(peripheral interrupt level) is used to request the LCP to change its mode of operation.

This ('', DINTL/ is driven 5 and the state line ST
This is done by presenting the correct state on -4/, ST-2/, and ST-1/. Status line ('', DINT
It must be stable during the time that L/ is active. DINTL/(' is the upper transfer control level in ``write mode'' and is the acknowledgment level for the HTCL/LPW data word, otherwise it (' is the command message H in C/M mode.
TCL/also('' is a response to HINTV.

DINTL/ causes a state change to occur in any of the above cases. When the LCP is writing to a peripheral unit, the peripheral interrupt level DINTL/('HTCL/
Also based on the leading edge of (JHINTL/; DINTL/ is deactivated by the trailing edge of these signals (HTCV-HINTL/). In "read mode" peripheral interrupt level DINTL/('', changes state DINT is a no-data transfer "strobe" used exclusively for
L/('' Upper transfer control level HT in read mode
Acknowledged by C.

When the LCP is reading from a peripheral unit, the peripheral outputs the peripheral message level DIN instead of DML/.
Drives the TV and deactivates DINTL/ when the peripheral unit detects the leading edge of the upper transfer control level HTCL/. In the upper load mode, this mode (') transfers data from a peripheral device such as 50 in Figure 6C to the LCP (upper) for the 'read mode', and also includes loading data (for the 'write mode'). (''Including the opposite.

Peripheral interrupt level DINTL/(' is the acknowledgment level for HTCL/-HINTLA as an upper load command.

Peripheral devices (1 DINTV driven 5 and state 2 (Table X)
Changes to The LCP acknowledges this by deactivating both HTCL/-HINTL/ and, if in "write mode", begins writing to the peripheral memory. To interrupt this mode, peripheral unit 50 drives DINTL/1 in the same manner as the regular ``write mode''. /,
ST-2/, ST-1/(false) Displays the status of the peripheral to the LCP and from this determines what kind of operation mode is required.

For example, in a typical embodiment, as seen in Table X, there may be eight states 0 through 7 for a peripheral device that may be used to indicate the following conditions: The above conditions (peripheral not online, read operation, write operation, result descriptor, command message (C/M), LCP timer reset (RT), command descriptor (C/D) are prepared or ( 'Writes the last word of the result descriptor and the vertical parity word (R/D-LPW
) should be transmitted next. A typical encoding system for status lines from a typical peripheral unit is shown in Table X below.

(DDP5Odl Figure 6C) interface discipline between LCP and peripheral units (see ``Read Mode'' and ``Write Mode'').

The read mode line control processor LCP is a peripheral unit (state-
1+7), and the peripheral device unit (50
, FIG. 6C) places the word on the data line and drives the peripheral message level DML/.

Acknowledge this by driving LCP(1, Upper Transfer Control Level (HTCL/) to 1. Peripheral Unit(') now de-energizes DML/, and then LCP
Deenergize TCL/. This process continues in state = 1 until the following 4 points: 1. LCP (J Upper Interrupt Level (HIN
TV).

The peripheral unit ('', if active, acknowledges by deactivating the peripheral message level (DML/) and asserts the peripheral interrupt level (DML/) with a change of state.
Drive INTL/). This indicates (1) for the peripheral that the LCP has a "command message" C/M to send to the peripheral.2. / drives the peripheral device interrupt level DINTV.

LCP('', acknowledges by driving the upper transfer control level (1ITCL/), and following deassertion of DINTL/, it (''upper transfer control level HTC)
De-energize L/ and proceed to the correct state. DINTL/ does not transfer data on the data line. 3. When the peripheral detects that it is transmitting the last word of the block, it responds to the peripheral with a state ST-Mo change with the leading edge of the peripheral (DML/) and the next transfer is in progress. Expect parity word LPW.

LPW is transmitted with peripheral message level DML/ and responded with upper transfer control level (HTCV). 4. If the LCP detects a vertical parity error, the LCP will not acknowledge the peripheral message level DML/ from the peripheral.

Instead, the LCP generates the upper Talia level (HCL/). In write mode, if the LCP is writing data to the peripheral (state=2+7), the following actions occur.

Place a word on the LCP(' data line and drive the upper transfer control level (HTCL/).The peripheral device:
Acknowledge by driving peripheral device message level (DML/). De-energize the LCP (' now the upper transfer control cape level (HTCL/), and then de-energize the peripheral device (1
Disable peripheral message level (DML/). This process continues in state ST=2 until the following two (Table X).

That is, 1. Peripheral equipment (changes the lie state to ST-Mo,
It then drives the peripheral message level DML/, which flags the LCP in which the last word of the block was received.

The next word on the data line is the upper transfer control level HT.
When CV becomes active again it must be vertical parity word LPW. The peripheral then sends a peripheral message level D that is accompanied by a change in the status line.
The peripheral interrupt level DINTL/ is driven instead of ML/. 2. At ST-2 or ST=7, the LCP sets the upper interrupt level H instead of the upper transfer control level HTCL/.
Drive INTL/.

In this mode, HINTL/(' means interrupt and vertical parity word LPW is on the data line. Peripheral device (drives peripheral interrupt level DINTL/ and state change to 1). The LCP is acknowledged by the upper interrupt level H.
Deactivate INTL/ and proceed to the correct mode after DINTL/ is deactivated. In another mode called "Result Descriptor R/D Mode", the LCP receives the Result Descriptor R/D from the peripheral (state = 3+7).
Read out.

When in R/D mode, the result descriptor on the data line is read from the LCP(' peripheral. The result descriptor R/D is 1 to 3 words long plus the length of the vertical parity word LPW. can be.3
- the first and second words of the word result descriptor R/D (' are read in state ST=3;

The last word of result descriptor R/D is in state ST-
7. Peripheral device message level DM
L/ means there is stable data on the data line. Each transferred result descriptor R/D word is acknowledged at the upper transfer control level HTCL/. If 1-word result disk R/D is LCP
, then the data transfer occurs after progressing from state ST=3 to state ST=7 with the peripheral device message level DML/, said level DML
/ means 1-word result descriptor R/D.
The next word on the data line (') is the R/D vertical parity word LPW strobed by the peripheral message level DML/. R
After finishing reading /D, the peripheral device (1) returns to state ST-6. It (1) can now receive the command descriptor C/D. Command message C/M mode This means that the LCP peripheral command message Device (state S
T=4).

When the LCP is in the [Read] mode and directed to the command message C/M mode (DINTL/+ST=4), the LCP ('', continues to send data to the main system 10 until the next two, i.e. 1. Drive the upper interrupt level HlNTL/ [Read-System End]
is detected, and (12. Data buffer areas A and B (buffer 2500, Figure 6C) are empty and "read-system end" is not detected. This causes the LCP to reach the upper transfer control level. HTCL/ is driven to 1 to indicate that the main system 10 expects more data. Reset Timer (R/T) Mode This ('' occurs when a peripheral resets the LCP timer. state ST=5).

A change in state for ST=5 resets the LCP timer. This state change occurs without strobes. Peripheral unit (remains ST=5 for at least 500+1 seconds. Second command descriptor (C/D)
mode In this case, the LCP uses the command descriptor C/
Writing D to the peripheral device (state = 6).

In this transmit command descriptor mode C/D, the LCP writes 3-words subordinated by the vertical parity word LPW. Upper transfer control level HTCL/(1 with C/D and LPW, acknowledged by peripheral interrupt level DINTL/ and change to appropriate state. Last word in block mode. This is the state = 7 (in Table X), and in ST-7 [
During a read operation, the LCP is reading the last word of the block of data (otherwise the result descriptor R/D) from the peripheral.

The next word (JLPW). During a "write" operation with ST=7, the LCP is writing the last word of the block to the peripheral. The next word is the vertical parity word LPW. Condition After the LCP writes the command descriptor C/D to the peripheral unit,
and the peripheral device is in state S at peripheral interrupt level DINTL/.
Before changing from T=6, the main system 10 terminates the operation (0P) by issuing a ``conditional cancel''.

In this case, LCP(!deactivates the upper transfer control level HTCL/ and then states ST=6 and DINTL/
The upper interrupt level HINTL/ is driven to 1 unless it is active.

Unconditional Cancellation Main System 10 () can generate an ``unconditional cancellation''.

This generates an LCP (1 upper clear level HCL/) to the peripheral device. No acknowledgment is required from the peripheral device. consists of a number of individual LCPs communicating to 10.

Each valley of several LCPs has essentially the same design and provides the same basic system functionality, but has different forms of LCP.
There are variations of such a non-trivial nature between CPs, since the valley LCP is tailored to the operational requirements of the particular peripheral terminal it serves. The following discussion includes a description of the operation of one preferred embodiment of a particular LCP, which is provided for peripheral terminals known as "monitoring terminals."

Necessary functional elements of LCP (registers, counters, encoders, decoders, buses, logic elements,
Including etc.

In addition, there are large scale integrated circuit (LSI) receiver/transmitters for implementing communication between the LCP and its peripheral terminal devices. Within the LCP there are functionally two divisions used for communication between the LCP and the main system 10, designated as the read module and the write module. module (′
Although they "functionally" exist, they are not separate components, since many of the logical levels of which they are composed are shared by both modules. "Module" converts data into LC
used for transferring from P to the main system 10, and L
The transmit flip-flop (XMITE) in the CP is active when set. "Writing module"
(' used to transfer data from the main system 10 to the LCP and receives flip-flop (RECVF)
is active when set. Functionally ('', LC
The components of P have three main sections: (,A) terminal control, I3) data flow, and (O
Contained in the system logical section.

For the purpose of understanding the means by which the LCP communicates with the main system 10 and associated peripheral end devices, such as 50, the following component functional characteristics will be described. A. Peripheral terminal control section 1. Universal Asynchronous Receiver/Transmitter (UART).

2. UART multiplexer.

3. Process check character register (BCCR)
.

4. Program check character decoder.

5. End code decoder.

6. Memory address register.

B. data flow section 1. Input multiplexer.

2.0P code register.

3.

Transformation register. 4. Valid 0P encoder.

5. LCP buffer (RAM).

6. Terminal busbar multiplexer.

7. Terminal busbar.

8. Vertical parity generator/Chietsuka.

9. Data latch register.

10. Vertical parity word (LPW) register.

11. LPW encoder.

12. End code decoder.

C. System logic section 1.

State count (STC) register. 2. STC decoder.

The above-mentioned functional components (Figure 6B, Figure 6C,
It will be understood with reference to FIGS. 6D, 6E and 6F, and with particular reference to FIG. 6D.

Examples of types of interconnections between peripheral devices and /O interface units are disclosed in U.S. Pat.
Seen in issue 78. An example of circuitry involved in communication between a remote unit and a corresponding buffer register in a typical manner can be found by reference to U.S. Pat. No. 3,390,379. Referring to FIG. 6D and the Peripheral Terminal Control (Section A) above, a universal asynchronous receiver transmitter (UART) 31 connects the asynchronous serial data channel of the terminal unit equipment interface 22di and the parallel data transmission channel of the LCP. It is used as an interface between

The transmitter section of UART3l has parallel data characters and their limiting levels as start bits, data,
Converts to serial information including parity bit and stop bit. The receiver section of UART 3l converts serial information, including start bit, data, parity bit, and stop bit, into parallel data characters.
UART3l (1 terminal unit device interface 2
It generates a parity bit for the information transferred to the UART 3l (or device interface terminal unit 22di) and checks the vertical parity of the information received from the UART 3l (also for various character lengths, odd or ()). Provision is made to select an even number of parity generation/checks, and a selection of 1 or 2 stop bits.

For use with a particular LCP, the UART3l(' has options selected to provide the following features: (a) a character containing 7 data bits; (b) even vertical parity generation/checking; c.
) 1 stop bit, UART multiplexer 27x
j! , from the AB (first two) digits of the terminal bus 47 again (
'Process check character register (BCCR) 3
Receives 3 to 8-bit characters.

The selected input (') is sent to the parallel data input bus of the UART 3l. Check Character Data Register (BCCR) 33 is a register consisting of eight separate flip-flops operated in a "toggle" mode with inputs connected to the AB digits of terminal bus 47.

While the LCP is transferring data to the terminal equipment interface 22d1, the BCCR 33 accumulates a program check character (BCC) to be sent to the equipment interface terminal unit 22di. When the LCP is receiving data from the equipment interface terminal unit 22di, the BCCR 33 is also checked for yet another "Program Check Character" (BCC) sent from the equipment interface terminal unit 22di. Accumulates one ``Program Check Character''.Program check character accumulation (for example, starts when the first character following the STX (Start of Text) or SOH (Start Heading) character is received, and the ETX (End of text) Continues until a character is received. Only messages and control sequences containing STX or SOH characters accumulate process check characters (BCCs). BC
The accumulation of C represents each character being transferred as BCCR3.
3 and performing a binary addition without a carry (exclusive 0R function).

Prior to each operation in which a BCC is accumulated in BCCR 33, the register is cleared. When the data transfer ends, the exclusive 0R function is again performed between the BCCs of the transmitting and receiving devices. If no errors occurred, both BCCs (one identical and the resulting BCCR
The value of 33 is "all O". Program check character decoder 34 (1, receives the output of BCCR 33.

When the transmission from the peripheral terminal device 50 ends, the BCC is
Received and checked for the contents of R33. 2
If the BCCs are the same, the BCCBf)I) output is
decoder 34 generates a BCCOK level (Process Check Character 0K) which is used for the BCC error logic.

Memory address register 36 is an 8-bit register that generates the address for 256 word LCP buffer 2500.

Register 36 ('') is controlled to provide selective or sequential addressing of buffers as required by the data transfer operation to be performed. When conditioned to receive data from a peripheral unit, e.g. 50, it provides a one second timer that is activated for operations only during "read" operations.

When the enable input is active, it allows the peripheral terminal a 1 second period to begin transmission or continue interrupting transmission to the LCP. If a period of one second elapses without a transmission from the peripheral terminal unit, the timeout flip-flop (TIMOUTF) is set and generates the timeout level (TIMOUTL), and the LCP then outputs the end flip-flop (TIMOUTF). Initiate termination for a read operation by setting ENDF). However, operation of this timer can be inhibited programmatically by placing an appropriate code in the variant-1 digit of the J1 command descriptor (Figure 4B). Figures 6B and 6D and LCP
Referring to the discussion of the data flow section (section B) in , input multiplexer 24x1 provides a selection of 17-bit words from three sources, namely, data input lines Bi, RAM data buffer 2500, Output line B25 also ('',
The peripheral device interface level 24m is generated on the maintenance card (eg 200m, FIG. 2) from the output of the pushbutton switch on the maintenance panel.

The selected level (1) received by the input multiplexer 24x1, as required by the operation to be performed, is transferred to the 0P code register 42 and the transformation register 43, to the terminal bus multiplexer 24x2 or to the appropriate 0P encoder 44. 0P code register 42 (') receives the digital 0P code of command descriptor C/D and, together with the output of transformation register 43, specifies the operation to be performed by the LCP.

Transformation register 43 (1) receives the transformation digits contained in the command descriptor C/D and, together with the output of the 0P code register 42, specifies further details of the operation to be performed by the LCP. Valid OP encoder 44
(1. A circuitry that receives command descriptor C/D information at its input, if the 0P code digits and variant digits 1, 2, and 3 match values representing a valid operation for LCP. , this encoder generates a valid 0P (VOP) level, which activates the command descriptor C/D to be loaded into the 0P code register 42 and the transformation register 43.LC
PR. AM buffer 2500 is made up of a network of 118 RAM devices, each of which has a capacity of 256 information bits.

Referring to FIG. 6C, more details of RAM buffer 2500 are shown. The buffer network can store 18-bits in each of its 256 address locations, 16 of which are 1 data bit and 1 bit (
' parity bit, and one bit is an end flag bit (25e in FIG. 6C) for identifying the word storage location containing the end code. Referring again to FIG. 6D, the terminal bus multiplexer network 24x2(',4
The four sources provide a selection of 17-bit words from four sources, the four sources being connected to input multiplexer 24x1 and U. ART3l and LPW24w
register output and result descriptor level 24rd. The output of the terminal bus multiplexer network 24x2 is directed to the terminal bus 47. Appropriate voltage levels are provided to those LCP components (e.g., data latch register 49, vertical parity generator/checker 48, buffer 2500, .LPW register). 24w,
decoder 52 and end code decoder 35) have inputs received from terminal bus 47. Terminal bus 47 (terminal bus multiplexer network 24x2)
Connect the output of the component to the next component, i.e., the data latch register 49, LC
PRAM buffer 25001 LPW register 24w1 vertical parity generator/checker 48, BCC register 33, end code decoders 52 and 35, and UART multiplexer 27x.

Vertical parity generator/checker 48 (') generates odd parity for each word transferred to the main system 10 by the LCP.

Generator/checker 48 also checks for odd parity of all words transferred from the main system to the LCP. Each word to be transferred from a particular LCP to main system 10 49 is placed in a 17-bit register.
The data latch register 49 ('' word is transferred to the main system 10
Transfer to. If you use a data latch register, LCP
- The speed of data transfer is increased by allowing faster access to data stored in RAM buffer 2500. A vertical parity word (LPW) register 24w is made up of 16 separate flip-flops operated in a "toggle" mode.

It receives its input from the terminal bus 47. When the main system 10 sends command descriptor C/D1 descriptor link D/L1 or data to LCP, L
PW register 24w accumulates LPWs (vertical parity words) to be checked against LPWs from system 10. When the LCP sends data or result descriptor R/D to the system 10, the LPW register 24
w also accumulates LPW to be sent to system 10. Accumulation of the LPW (') includes presenting each word being sent or received to the input of the LPW register 24w and performing a binary addition without a carry (exclusive 0R function). LPW register 24w is used before each operation in which LPW is accumulated in the LPW register.
All are initially set to 1.

When the data transfer from the main system ends, the exclusive 0R function is accumulated on the LPW and the LPW from system 10.
carried out between. If no error occurred, both LPWs would be identical and the resulting value in LPW register 24w would be "all 0s". In FIG. 6D, end code decoders 52 and 35 would Decoder 52 processes the AB digit and decoder 35 processes the CD digit. AB digit end code decoder 52 inputs the encoding code in the first character position of a word from the main system. This decoder (also known as the terminal unit equipment interface 22d)
Used to identify the ending code in any character sent from i. Moshi decoder 52
receives such an ending code, thereby generating levels EDCODE and SYSEND. CD digit decoder 35 (1 from system)
Used to identify the ending code at the last character position of a word. By receiving such a digitizing code by decoder 35, a voltage level SYSEND is generated. The above discussion (which included the second section B of the lie LCP; now the third section C, the system logic section of the LCP ('6)
This will be discussed with reference to Figure D. Status count register 5
3 (STC) ('' is a 4-bit register.

This register generates a state count level (STCnL) for use in the LCP and a level designated LCSTUn (LCP state level) for transmission to the main system 10. While giving a floating logic level, ST
C register 53 also controls the sequence of operations for the LCP. Each state count generated by STC register 53 identifies a different phase of operation in the execution of command descriptor C/D, as previously outlined with respect to FIG. 6A.
Decoder 54 (') is a Binary Coded Decimal (BCD) to decimal decoder that changes the BCD value of STC register 53 to the decimal value required by the LCP system. It is helpful to refer to FIG. 6E when reviewing the system interrelationships between the major LCPT-elements involved with respect to control signals.

Figure 6E (lie 10T (input/output translator) 10t.
The main logic and control lines between the distribution card 200d (relative to the base module 200), the specific line control processor LCP2OOO and the peripheral terminal device 50 are shown.
First, refer to the lowest group of the cape line, LCP2OOO, and its distribution card 200d, and select LCPREO (
n) (is a group of eight "request" lines where the letter (n) represents the number 0-7 for each particular LCP in the base module 200.

Each of these signals is driven to the distribution card 200d by a specific LCP.
used by the CP to "request" a connection to the system 10, and by this signal the distribution card 200
d sets up a "polling request". next LC
PCON is the designation for "LCP connection".

This Rhino (LCP connected to the distribution card 200d)
(0-7). This signal (') is driven to 1 by an LCP when it detects a particular LCP address in its possession and it is not in an ``offline'' condition. LC addressed to
It means the existence of P. LCPSTL means "LCP strobe level". This rhino ('' to the distribution card ``
connected' LCP. It ('' is the designation of a particular LCP for either ``send'' or ``acknowledge'' based on the data direction involved.

10SND('' Denies I/O transmission.

This line (“L” “connected” to the distribution card 200d
Driven by CP. This rhino is DATA (Xn
) (data) defines the direction of the bidirectional data line. When this line is active low (10w), the data line is driven 1 by the distribution card 200d to the main system 10 via IOTlOt. LCSTU(n)('', "n" indicates the status of a particular LCP, indicating any of the LCPO-7s.

This line (1) is driven by the LCP specifically connected to the distribution card 200d and is shown in FIG. 6A.
Represents the "state" of the CP.Referring to FIG.
It is provided between 0d and 0d.

DATA (Xn) (''Message level interface 1
(The lower 16 lines are the data lines for digit ABCD, shown earlier in Figure 5E). The next higher line (parity line) carries the parity bit. Transmissions may occur in either direction along these lines based on the logical control lines used to determine. EMRREQ in FIG. 6E stands for "Emergency Request" rhino.

This Rhino(') distribution card is driven by one or more LCPs to the card. The LCP drives the emergency request line at any time. means that access is required.LC for system access.
Missing only P would require operator intervention or difficult one-line regeneration to drive emergency requests along with those LCP requests. Those LCPs that are not emergency requests will Disable the request. By the distribution card detecting the urgent request, an overall priority of "7" is transmitted to the main system 10 during the "boring request". TERVl "End" in FIG. 6E. Indicates the voltage level, which is generated on the distribution card and
CP to terminate or terminate the operation. In Figure 6E, the LCPAD 'n'(') is used to indicate an individual LCP.
). One of these eight signal rhinos (1) is driven by the distribution card for each particular LCP. The receivers of the LCPs are connected by appropriate lines. is the connecting Rhino.The LCP (
Lie, "connected" to the main system 10 via the distribution card. STIOL('' in FIG. 6E means "strobe I/O level."

This Rhino(') is driven 1 by the connected distribution card. It(' represents the system's 'send' or (lies) 'acknowledgement' based on the data direction. ARQ in Figure 6E.
The OUT line (' is the output end of the distribution card with an input denoted by ARQIN).

These represent "access request manpower" and "access request output." These signals are driven and received only by the distribution cards and consist of short lines between adjacent distribution cards. They (are used during a "Bowling Request" to resolve distribution card priority. Lines DCRl and DCB2 represent the distribution card [in use] level. Generated on each active distribution card of the base module to resolve distribution card priority.
shows.

This is the bidirectional signal level between distributed cards on the same base module. A distribution card that performs a "Bowling Test" operation sends this level to other distribution cards so that they are "Polynog Test".
It is also prohibited to lead the "Bowling Request" sequence. Each base module (", its distribution card (20
0d, FIG. 2), multiple distribution cards are provided to cooperate and service other superordinate "main systems".Each of the base modules A distribution card ("capable of servicing different superordinate systems and subordinate to each superordinate system" the same basic organization shown in FIG. 3. REQACC
Rhino (J indicates "request access".

This line is driven and received by the distribution card only. line (is used by the distribution card to mean an "active" interrupt request. BU in Figure 6E)
SY line (indicates the base module ``in use'' level. This ('') indicates that the card is ``connected'' in the main system 10.
is the bidirectional signal level generated on the distribution card when 0T1 is sent to other distribution cards on the same base module to indicate that the LCP backplane is in use.
The relationship between 0t and distribution card 200d is discussed.

At the top left of FIG. 6E, LCPST indicates the LCP strobe pulse. This is generated on the distribution card from the LCP strobe level and sent onto the main system via IOTlOt. PB/ST2 (indicates "port in use" or LCP status 2 line.

This line ('' is on the message level interface as shown in Figure 5E. In the ``not connected'' state, this line ('' lies) indicating a port busy condition during the ``polling test'' algorithm. In the state ``('', this line ('') bit 2 of the LCP state
carry to system 10. IP/ST4 indicates an interrupt request or ('pollinog test parity 1 line) or (false) LCP status 4 line.

In the unconnected state ('', this line is used to carry an "interrupt request" from the LCP, or otherwise to indicate an address parity error during a "polling test" connection attempt. Interrupt Request (1, Indicates that the LCP is requesting access to memory. In the "connected" state, this line (or
Carry bit 4 of the CP state to the main system. ER/
ST8 indicates "urgent request" or ("LCP status 8 line.

In the "not connected" state (", this line ("L
Indicates an urgent request from the CP. "Urgent Request" indicates that the LCP requires direct access to the main system. In the ``connected'' state ('', this line ('' carries bit 8 of the LCP's state to the main system. Once connected, the LCP ('' indicates its system memory requirements due to its state.LCP state PARITY and DATA are continuously gated and considered valid by the system at LCP send/acknowledge times. With further reference to FIG. Connections denoted [Xn] ('' indicate the message level interface lines previously described.

CS/STl indicates "channel selection" or LCP status 1 line. In the ``unconnected'' state ('', this line ('' carries ``channel selection'' from the system 10 to the distribution card. ``channel selection''('') is used in conjunction with ``address selection'' in both connection algorithms.
However, in the ``connected'' state, this line carries bit 1 of the LCP state to the main system 10. This line is a bidirectional line. The receiver on the distribution card carries any standard TTL The driver on the distribution card is a 3-state driver, e.g.
97/8098 (National Semiconductor Cooperation)
or is equivalent to being active only in the connected state. TRM (J indicates "end" level.

This is sent from the raw system 10 to the distribution card when a data transfer operation is to be completed.
The ADDSEL line in FIG. 6E indicates "address selection." This signal line indicates that the main system is connected to a particular LCP and that it is attempting to connect. Once a connection to the LCP is achieved, the system and LCP remain connected until the signal line is no longer driven by the system. When the line is active, the system Referring again to FIG. 6E, AG/SIO('',
Indicates "access allowed" or "strobe I/0".

When the interface is in the "not connected state",
This line carries an "access allowed" signal. "Access Grant" is used to acknowledge an interrupt request for a connection and is used to start a "Balling Request" algorithm. With the interface in the "connected" state, this line ("" strobe I/
O” carries the signal. This signal (1 system 10 and LC
A system sends an "acknowledgment" when transferring information between P-base modules. The actual signal (100) sent from the system and latched by the distribution card
+1 second minimum pulse. Distribution card ('generally clips the first 50+1 seconds from the signal to account for cable stabilization time. With respect to Figure 6E, control signals ('RMDTL') such as between LCP2OOO and peripheral terminal equipment 50
The line indicated by N is shown.

This ('' indicates the remote data line level. This ('' is a bidirectional signal level, and this bidirectional signal level is determined by the LCP level in one direction and ('' in the other direction.
and allows serial data transfer of peripheral terminal devices. L
The operational sequence of the CP is discussed here and below.

Logical terms ('', denoted as either active or inactive, for the purpose of avoiding any ambiguity arising from the use of the term truth-value and negation-value, are instructions by a line-based processor. 6A, a state count (
The logic flow including STC) was discussed. Referring now to FIG. 7A, a simplified flow diagram illustrating the receipt of orders by the LCP is shown in more detail. This flowchart illustrates the basic operations of LCP during the receipt of instructions and also those operations that can occur based on changes in the original instruction, receipt of time-out levels, and occurrence of error conditions. . Before receiving any of the seven possible instructions from the main system 10,
The LCP is in the "idle" state with a normal state count of 3.

However, the LCP can also be in STC 3 during a "read" operation, waiting for a conditional cancellation command from the main system 10 and for data transmission from a peripheral terminal, e.g. While receiving instructions from system 10 and preparing to execute the instructions,
The action of LCP will be explained.

These effects are itemized as (a), (b), and (c). (a) System-LCP Connection: ST
At the LCP in C3, the system (') makes a connection with the LCP through the 'Pollinog Test' sequence, and the LCP (') establishes its unique address level (LCPAD) (n) as shown in Figure 6E. receive.

The reception of LCPAD(n) sends the LCP (JLCP Connection Level (LCPCON. Figure 6E) to the associated distribution card 200d and generates LCPADL (LCP Address Level), which is part of the LCP system logical section. “Activate” Address Level LCPA
D(n)(''Also, gate system level (GATSY
Activate the LCP backplane circuitry by generating S). Then, strobe (STIOL)
is received from the distribution card (200d, FIG. 6E), thereby setting the STIOF (synchronous strobe flip-flop). STIOF set is RECV
Drive the desired module of the LCP by setting F (receive flip-flop) and set the LPW register 2.
4w1 (FIG. 6D) to logic ``1'' and sets the selected flip-flop to the starting state. Command descriptor C/D (received in JLCP and carded into OP code register 42 and transformation register 43 (FIG. 6D). As a result of receiving C/D), LPW is placed in LPW register 24w. C
/D is checked for validity and a valid 0P flip-flop (VOPF) is set. LCP (steps from STC3 to STCll (Figure 7A) and receives LPW from system 10. (b) Receives LPW by LCP; received from the LPW register 24w and checked against the contents of the LPW register 24w,
Check the validity of vertical parity of C/D transfer.

Vertical parity is also checked and vertical level 0K (L
OK) and vertical parity 0K level (VPAROK)
is set. LCP buffer address (') is preset to 253 in memory address register MADR36 (Figure 6D), and logic ``1'' in LPW register 24w.
The set to LCP (Cosystem 10
STC to receive descriptor link D/L from
Step to 6. (c) Reception of descriptor link and descriptor link LPW: At STC6, LC
P(1) Receives two words of the descriptor printer D/L from the system 10 and LPW(1 is accumulated in the LPW register 24w.

LPW (1) then the system 10 receives and LP
The contents of the W register 24w are checked.
Descriptor links D/L and LPW are connected to memory address register M. as addresses 253, 254 and 255 (FIG. 6C). The buffer address memory location specified by ADR 36 is stored. from STC6 to LCP('' STC8 for a ``write'' operation.
Branch to STCl for a read operation, and branch to STC7 if descriptor link 1 occurs. (a) If a ``conditional cancel'' instruction is 10, and (1(b) a data transfer is received from a peripheral terminal device, e.g. 50, and (c) a time-out level is generated, and (d) a There are cases of alternating flow paths such as

To expand on the case of these alternating flow paths with respect to FIG.
At C3, if a conditional cancellation command is received from the system 10 and the LCP is waiting for a transmission from the peripheral terminal 50, the cancellation flip-flop (CANCF
) is set and LCP steps to STCll to receive the command descriptor vertical parity word, LPW. From STCll, LCP steps to STC7 and sends the result descriptor to system 10;
Indicates that the cancel operation has been completed.
(b) Receiving a transmission from a peripheral terminal unit: If the edge unused flip-flop (TRMBSYF) is set in STC3 during a ``read'' operation,
If the terminal unit indicates that it has started transmitting,
The LCP steps to STCl to receive data from the peripheral terminal unit. The LCP continues to receive data and completes the remainder of the read operation according to the instructions contained in the command descriptor C/D.
c) Receive time-out level: During a ``read'' operation, the LCP in STC3 receives a transmission from a peripheral terminal unit (and if the 11 second timer is not disabled) then receives a transmission. If there is a second delay, a time-out level (TIMOUTL) is generated. TIMOUTL is active, an end flip-flop (ENDF) is set, and an end not completed ('RMCNP) is set.
A level is generated and LCP steps to STCl. At STCl, requests for reconnection to the system are inhibited and LCP steps to STC5 (Figure 7B). ENDF is set at STC5, the read operation is completed, and LCP steps to STC7 to send the result descriptor R/D to system 10. Time-out level (' can also be received with LCP at STCl. (d) Receipt of test command; STCl
1 (Figure 7A), if TESTF (test flip-flop) is set to indicate that a test command has been received, the result descriptor is returned by stepping to LCP(', STC7). The test operation is completed by sending the R/D to system 10.

1 la 1 condition; 1 la 1 condition (Ea
) and (Eb) occur in two forms ('', as follows:
(Ea) Command Descriptor Parity 1ler activated by LCP: In FIG. 7A,
In the STCll, if the VLOK (validity level 0K) level is not active or the VOPF (validity operation flip-flop) is not set, the L
The CP steps to STC7 and sends the result descriptor R/D containing the descriptor string to the system.

(Eb) Descriptor link parity 1 layer; STC
6, if the VLOK level is not active, the LC
P steps to STC 7 and sends the result descriptor R/D containing the descriptor link error to system 10. WRITE OPERATION Referring to FIG. 7B, a sequential logic diagram is shown which is simplified to illustrate the steps involved in a "write" operation.

Assume that a buffer load of data is transferred from system 10 to peripheral terminal unit 50, followed by a specific buffer of data containing an ennoding code character in the last character position (CD digit) of the word. The following steps (a-i) describe the operation of the LCP, e.g. 2000, while transferring data from the system 10 to the LCP and from the LCP to the peripheral terminal device, e.g. 50. .

(a) Receiving data from the system; at STC6,
If a "write" operation is specified by command descriptor C/D, LCP(1, LPW
Enable register 24w to be set to logic ``1'' and then step to STC 8 to receive data from system 10.

A 10SF (1/O transmit flip-flop) is used and placed in reset at this time to enable the bidirectional data line for transferring data from system 10 to the LCP.

Multiplexer control levels SLAIN (selecting the A input multiplexer) and SLBIN (selecting the B input multiplexer) are provided. These (1) are both inactive and connect the data lines to the input multiplexer circuitry 24x1 of Figures 6B and 6D. (terminal bus multiplexer selection B level). Both of these are inactive, and the input multiplexer circuitry 24
x1 to the input of terminal bus multiplexer network 24x2. At STC8, receive flip-flop (CVF)
) is set to drive the LCP's write module.

Setting RECVF makes the write enable level (WESYS) for the LCP buffer active.
In this way, the data ('', one word at a time, via the terminal bus 47 of the LCP, the system main memo I) IOm
The data is transferred from the LCP buffer 2500 to the LCP buffer 2500. The asynchronous strobe (
Since the STIOL) involves the transfer of each word and each word is received by the LCP, the strobe level (LC
PSTL) to the system 10.

As each word is placed on terminal bus 47, it is further sent to buffer 2500 which is applied to the input of vertical parity generator/chicker 48, LPW register 24w and end code recorders 52 and 35. Vertical parity (') is checked and the vertical parity word is accumulated in the LPW register 24w. Word transfer continues until the next after the last data word address 251 is achieved in the memory address register 36.L
CP steps to STClO in Figure 7B to receive one final word from the system. In STClO, LC
P receives the final word to fill the buffer and then steps to STC 12 to retrieve the LP from system 10.
Receive W. (b) LPWO) Reception and System 1
Shutdown from 0: At STCl2, the LCP receives the LPW from the system 10 and checks it against the LPW accumulated in the LPW register 24w during the data transfer.

LCP(') enables setting the LPW register 24w to a logic '1' and steps to its STCl, disconnecting it from the system 10 for the purpose of transferring data to a peripheral terminal device, e.g. 50.
Levels SLARAM and SLBR, AM (A selection and 24x2 B selection) are both inactive, thus connecting the output of buffer 2500 and the input to terminal bus multiplexer network 24x2. The input multiplexer 24x2 has control levels SLAIN (manual multiplexer selection A level) and SLBIN (input multiplexer selection B level), which access characters alternately from the AB digit and CD digit of one word of the buffer 2500. (c) Data transfer to peripheral terminal equipment: With further reference to FIG. 7B, at STCl, the receive flip-flop (R
ECVF) is set, thus activating the LCP's receive module.

A terminal not yet started level (TERST) is generated to prepare the LCP for operation at the peripheral terminal device.
The TERST level enables a set of master clear UART flip-flops (MCUARTF) for the purpose of clearing UART 3l (Figure 6D). A terminal enable flip-flop (TRMACTF), a second flip-flop (SENDF), and a set of end unused flip-flops (TRMBSYF) are also enabled to drive the terminal control logic for write operations and to In use] state. M such that memory address register 36 (FIG. 6D) accesses the first word of buffer 2500.
Set to ADRO. In UART 3l, the ``receiver holds register empty'' (THRE) level is active, and a set of UART empty flip-flops (UARTETF) is activated to provide a strobe level to UART multiplexer 27x. U
ART 3l receives one character at a time from LCP buffer 2500.

An even flip-flop (EVNF) is used in conjunction with memory address register 36 to control character access. When loaded with a character, U
ART 3l serially transfers the character to a peripheral terminal device, eg 50. Since each character from the buffer 2500 is placed on the terminal bus 47, it is also applied to the input of the program check character register (BCCR) 33, which is the (STX/SOH, or "start testing/start testing" character). begins accumulating program check characters during data transfers (after the memory address level MADR 252 is received in the memory address register 36). is transferred to the terminal device 50 to indicate that the last word of the buffer has been accessed. (d
) Request for reattachment to system 10: Buffer transfer flip-flop (BFXFRF) is set by memory address level MADR 252 and buffer 2
500 requires service, and the LCP
initiates a request for reconnection to the system by activating the set of LCP request flip-flops LCPRQF.

A set of 10SF (/O transmit flip-flops indicating the direction of data flow on the message level interface) is enabled to condition the data lines to transfer data to system 10, and a set of MADR253 levels is enabled. Descriptor link D/L (
(Figure 6C).

The LCP steps to STC5 in FIG. 7B and sends the descriptor link D/L to the system 10. The LCP address bell (07), LCPADn, is received from the associated distribution card during the reconnection sequence, and the gate system (
When generating a level called GATSYS), LC
There is a floating logic level that generates PADL (LCP address level). Connected to that level LCP (LCPC
ON) is sent to distribution card 200d to indicate that the LCP is connected. (e) Transfer of descriptor link and descriptor link LPW: In FIG. 7B, the transmission flip-flop (XMITF
) is set to drive the LCP's "read" module. LCP is descriptor link D/L and L
Forward the PW (previously received at STC 6) to system 10. The LCP sets the LPW register 24w to logic “1”
If the main system has more data to send, the LCP will again set the ST
Step to C8 to receive additional data from system 10. (f) Receive additional data and encoding codes from system 10: at STC 8, system 1
While receiving a "second" buffer load of data from zero, the action of the LCP is the same as that performed during reception of the first buffer load, up to the point where the "ending code" is recognized by the terminal bus 47. be. When the ending code in the last character position (CD digit) of a word is placed on terminal bus 47, a system end level (SYSEND) is generated.

The SYSEND level makes the data input for end flag 25e (RAM18L) of FIG. 6C active, and both the end flag bit (ENDFG) and the ending code character are stored at the current buffer address. LCP then steps to STCl2 and receives the LPW from system 10. (g) LP
Reception of W and blocking from system 10: S of FIG. 7B
At TCl2, the LCP receives the vertical parity word LPW and checks it against the LPW accumulated in the LPW register 24w.

LCP then steps to STCl and system 10
The remaining data and ending code are transferred to the peripheral terminal device. (h) Transfer of Data and Ending Codes to Peripheral Terminals: In STCl, the operation of transferring the remaining data to peripheral terminals is such that up to the point that the "Ending Code" is recognized on the terminal bus 47,
The same as that done during the first buffer load transfer.

When the ending code is placed on terminal bus 47 from the output of buffer 2500, the ending code is transferred and the end flip-flop (ENDF) is set. The accumulated proc check character of BCCR 33 (if a BCC has not been generated) is transferred to a peripheral terminal, e.g. 50. Both SENDF (transmit flip-flop) and TRECF (terminal receive flip-flop) are in the set state, which causes the end incomplete (TMCMP) level to become active. The end incomplete level causes the LCP to initiate a request for a connection to the system 10. (1) Request for reconnection for terminated write operation: LCP
Request reconnection to the system by activating the PRQF (LCP request flip-flop) set.
Upon reconnection, the LCP steps to STC5 in FIG. The above discussion is
Having described the general flow path for a "write" operation, in which two or more buffer loads of data are transferred, and the operation is completed by receiving an "ending code". It was done. This describes the normal case. However, with reference to FIG. 7B, there are alternative flow paths and possible error conditions that may occur below. Next item (a)
to (c) when a "change" to the original write instruction is made by the system 10 or the LCP.
Explain the effect of (a) Request for emergency access to system 10: When LCP buffer 2500 becomes completely empty while transferring data from the LCP to peripheral terminal 50, flip-flop BFXFRF is set.

This is a buffer transfer flip-flop located on the termination terminal card; this flip-flop is
Set when the LCP buffer is filled with data from the terminal or becomes empty while transferring data from the LCP to a peripheral terminal.
When BFXFRF is set, this is LCPRQF
(LCP request flip-flop, which, when set, enables the LCP to access main system memory 10m). LCPRQ
A set of F initiates a request to reconnect the transmitted data to the main system or, if the buffer is empty, to the system 10 for normal data.
If the reconnection is not completed before the time when UART3l's transmission holding register is ready to receive another character, an emergency request level (EMR) is set by the LCP.
REQ) is generated. The EMRREQ level is sent to the associated distribution card 200d to initiate an emergency request to reconnect to the system. (b) Receiving an Ending Code (AB digit): If an ending code is identified in the first character position (AB digit) of a word from system 10, an EDCODE (end code level) is generated. EDCODE is generated on the terminal control card when the end code character is in the A and B digits of terminal bus 47. SYSEND (system end code level) is also generated. When active, the SYSEND level indicates that the end code character is on terminal bus 47. At STC8,
The EDCODE level enables the character end flip-flop set, and the SYSEND level:
18th bit write end flag level, RAM
Generates l8L. A "write" end flag level is generated on the terminal control card from the EDCODE level;
8 This is the end flag RAM of LCP buffer 2500
This is the data entry level for Ending code and ENDFG (end flag level is RAM18L)
When active, this level identifies the address of the end code of the LCP buffer) is stored at the current buffer address of the LCP, and the LCP is sent to STCl2 (Figure 7B). Step to receive vertical parity word LPW. At STCl2, the LCP receives the LPW from the system 10 and checks it against the LPW accumulated in the LPW register 24w. LCP steps to STC9 to begin decrementing system memory addresses. (From ΣSTC9, the address is decremented by two digits to exactly reflect the address of the ending code in system memory, LCP is ST
Cl to transfer the data and ending code to the peripheral terminal device 50. By recognizing the ending code on the terminal bus 47 when the data, the ending code, and the program check character are transferred to the peripheral terminal device 50 in the STCl, the LCP
performs the same actions described during the previous "write" operation in STCl, after which the LCP disconnects from terminal 50 and reconnects to system 10 and completes the "write" operation. (c) System 1
Receiving a termination signal from 0: A termination signal (TERM level, Figures 6C, 6E) is sent from the system 10 to the LCP whenever the designated system memory space for an LCP operation is to be exceeded. .

During a [write] operation, the TERM level is S.
It can be received with TC8, STClO, or STCl2 (Figure 7B). The action of the LCP when receiving a TERM level is based on the state count in which the LCP is active, and the reception of the TERM level is proceeded by receiving an [Ending Code] from a system such as: Based on what. (1) Receive termination signal before ending code: If TERM level is received by STC8 or STClO, LCP
Step to TCl4.

At STCl4, regardless of whether the TERM level remains active or is now inactive, the LC
P steps to STCl2 and vertical parity word LPW
It receives and checks it, then steps to STC 7 and sends the result descriptor R/D to system 10.
If the ending code is STC8 or STClO
If one word of CD digits (least character) is accepted, and the TERM level is also accepted, then the LC
P steps to STCl4. In STCl4, TE
If the RM level is still active, the ending gord is not placed in the LCP buffer 2500. Step to LCP STCl2, receive and check LPW, then step to STC7 and send result descriptor R/D to system 10. (2) Receive end signal at ending code 5: If the ending code is S
If received in the CD digit of one word at TC8 or STClO, LCP steps to STCl2 and LPW
receive.

In STCl2, if you can receive the TERM level now,
The ending code is transferred to LCP buffer 2500 and the LCP steps to STCll to transfer the remaining data and ending code to peripheral terminal device 50. ENDF is set by recognizing the ending code on terminal bus 47 at STCl. (
End Flip-Flop When preset, this flip-flop indicates that the terminal control section of the LCP has terminated its operation). END
A set of F indicates that there is no data to be transferred; after the data, ending code, and program check character have been transferred to the peripheral terminal, the LCP shuts off from the terminal 50 and the system 1
0 and complete the ``write'' operation. As shown below, in STCl, terminal bus 1,
By recognizing the ending code on 47,
ENDF (end flip-flop) is set.

A setting of ENDF indicates that there is no data to be transferred, and the LCP reconnects the system 10 after the data, ending code, and program check carrier 2 have been transferred to the peripheral terminal 50. hand[
Terminates the write operation. If the ending code is STC8 or STClO, one word of A
If the B digit is received and the 2 TERM level is also received, the LCP steps to STCl4.

In STCl4, if the TERM level is inactive,
The entire word including the AB digit ending code is LC
Transferred to P buffer 2500. The system memory address needs to be corrected. LCP steps to STCl2, receives and checks LPW, then STC9
Step to begin decrementing the system memory address. The LCP steps to STCl to transfer the data and the ending code to the peripheral terminal 50; if the TERM level is still active at STCl4, only the ending code character is transferred to the LCP buffer 2500 and the system No modification of memory addresses is required.

The LCP steps to STCl2 to receive and check the LPW, and then steps directly to STCl2 to transfer the data and ending code to peripheral terminal 50. No error condition: During a "write" operation, the following error conditions (A, b, c, d) are acted upon by the LCP.

(a) Access error: After transmitting the EMRREQ level to the associated Momoku card, if the LCP does not receive a reconnection to the system 10 before the time when UARP3l becomes completely empty, the LCP will receive an access error. Activate the flip-flop (ACCERF) set.

The ACCERF set is an end flip-flop (EN
DF) and the LCP is set in system 10.
Initiates a request for reconnection to the [write] operation and returns the error result descriptor R/
Send D to system 10. (b) System Vertical Parity Error While transferring data from system 10 to LCP, if vertical parity is not 0K and PA
If the ROK level is not active after each vertical parity check, the vertical parity error flip-flop (VP
ERF) is set to indicate that a vertical parity error exists.

If there is no VPAROK level, no vertical 0K level (VLOK) is generated, and in STCl2, LCP
Steps to STC7 and reads the error result descriptor R/
Send D to system 10. (c) Vertical parity error (Figure 7B): The vertical parity word is
When the data transfer to P is checked, if the vertical parity 0K level (LPOK) is not active, the vertical parity error flip-flop (LPERF) will now indicate that there is a vertical parity error. is set.

If there is no LPWOK level (LPWOK level: generated on the data flow card from the terminal bus 47 level,
When active, it indicates that LPW is correct for the sostem logic section of LCP), VLOK
level is not generated and at STCl2, LCP is ST
Step C7 and send the error result descriptor R/D to the system 10. (d) Terminal Vertical Parity Error While transferring data from LCP buffer 2500 to UART 3l, if the terminal vertical parity does not remain active due to the lower character not being transferred to the Vertical Parity 0K (PAROK) level, Error flip-flop (
TVPERF) is set to indicate that a vertical parity error exists.

When LCP reconnects to system 10 and completes the ``write'' operation, system 10 at STC7
The result descriptor R/D sent to indicates parity error. Read operation Referring to FIG. 7C,
A simplified logic chart illustrating a "read" operation is shown.

"Read" operations are generally accomplished in conjunction with some form of "write" operations. As an example, a "write" operation has been completed and the peripheral terminal device 50 responds with an acknowledgment character (ACK) to indicate that the peripheral terminal device 50 can now send information. Let's assume that. It is also assumed that there is no delay when receiving data from the peripheral terminal device 50, and that a certain buffer load of data is received subordinated by a partial buffer of data including the ending code. . It is also assumed that the ending code will be received in such a way that it is placed in the last character position (CD digit) of a word of LCP buffer 2500 (Figure 6C). General Flow Paths: The following paragraphs (a) to (l) describe the actions of the LCP during the transfer of data from the peripheral terminal 50 to the LCP and from the LCP to the system 10. explain. (a
) Shut off from main system 10: With reference to FIG. 7C, ST
At C6, when a "read" command is specified from the system in the command descriptor C/D, READF
(Read flip-flop: This is located on the data flow card, the logic state of the read flip-flop is controlled by the output level from the 0P code register, and the set state of READF is determined by the read operation performed by the system. ) is set.

The LCP enables setting the LPW register 24w to a logic ``1'' and then steps to STCl to disconnect from the system 10 and receive data from the peripheral terminal 50. Terminal busbar Marunaplexer 24x2 (Figure 6D)
Selection A level (SLARAM) is active and S
LBRAM,. SLAIN and SLBIN levels are inactive and UART3l to LCP buffer 250
Provides a path for data to 0. (b) Receiving and recording data from the terminal device: Referring to FIG. 7C, at STCl, RADF is set and end not started (TE
RST) level is active. This TERST level causes UART 3l to be master cleared and this TERST level is used by the TE to drive the terminal control logic.
RMACTF (This is a terminal active flip-flop, located on the terminal control card, the logic states of this flip-flop are TERST, .TRECFl and S
Controlled by ENDF, the set state of TRMACTF enables the set state of TRMACTF (indicating that the terminal control section of the LCP has been driven to 1 for a ``read'' or ``write'' operation). READF also
Activate the terminal receive flip-flop (TRECF) set to allow receiving data from peripheral terminal device 50. The buffer 2500 has an address preset to the buffer DR memory location 255, and if the even flip-flop (EVNF) is not already set, its setting is activated to begin controlling buffer addressing. Data characters are transferred serially from peripheral terminal 50 to LCP(7) UART 3l, and the UART checks each character for even vertical parity. (b-1) Reception of the first character and generation of vertical parity: The terminal reception flip-flop (TRECF) is set, the data store flip-flop (DATASTF) is in the reset state, and the first character is received. By doing so, the received data label (DR) is active.

DR level set UART flip-flop (RS
TUARTF) and end unused flip-flop (T
Activate the set of RMBSYF). The even flip-flop EVNF is set and the buffer address is MA.
Incremented to DR memory location 0. The data store flip-flops DATAASTF and EVNF are activated in preparation for storing the first character in the buffer. RSUARTF is set and a SLARAM level is generated which places the first character on the AB digit and also the CD digit of terminal bus 47 to form a complete word. Parity bits are not included in this word. The contents of the terminal bus 47 are the sixth
Vertical parity generator/checker 48 in FIG. For application to indicate parity, parity is generated for the word on terminal bus 47 until a second character from peripheral terminal 50 is received, and the flip-flop used to specify odd vertical parity is set or reset. (b-2)
Store the first character in the buffer: data store flip-flop DATAASTF is set and EVN
Buffer write enablement A (
ERWA) level is active.

The system write enable (WESYS) level is also active and these two levels provide the write enable inputs for the AB and CD digits of the buffer network.
The first character is then memory address register 3
6 MADR memory locations 00) are stored in both the AB and CD digit locations. The first character is UART
3l to buffer 2500, the reset UART flip-flop (RSUARTF) is reset. The data receive level (DR) is made inactive and the DATASTF (data store flip-flop) reset continues. This combination of logic is UART
3l receives a second character from the peripheral terminal device 50. (b-3) Receiving and storing the second character: When the second character is received by UART 3l, the data receive level (DR) is reactivated and RSUARTF is set.

This logic in combination with the even flip-flop EVNF reset state inhibits the buffer address from being incremented. Data store flip-flop DATAASTF
and a set of even flip-flops EVNF are activated in preparation for storing a second character in the buffer. Terminal busbar multiplexer selection A level SL
ARAM is still active and characters are placed on both AB and CD digits of terminal bus 47. The contents of terminal bus 47 are again provided to vertical parity generator/checker 48. Parity is generated for the word on terminal bus 47 and compared to the parity generated during reception of the first character. As a result of the comparison, one parity bit is generated for the first and second characters. Data store flip-flop DATASTE and even flip-flop EVNF are set and ER
The WB level (write enable level for the CD digit of the LCP buffer) is generated and a second character is stored in the last character position (CD digit) of the buffer 2500 in the address storage location MADRO and previously there. Write on the placed character.

The character on the AB digit of the terminal bus 47 is buffer 250.
0 because the ERWA level is not active (ERWA is the AB of the LCP buffer).
is the writable level for digits). The parity bit from the vertical parity generator/checker 48 is
MADRO is added to the complete word now contained in the memory address register. (b-4) Receive additional characters and process check characters (BCC)
Start of accumulation: Additional characters are received by the LCP.

In response to each character, an even flip-flop EVNF
The logic state of is complemented to control the incrementing of memory address register 36, thereby placing the data in word format into buffer 2500. From the peripheral terminal device 50, the “Heading start/Text start” character (S
In response to SOH/STX), the program check character register 33 in FIG. 6D is activated and SOH/ST
Each character following the X character is applied to BCCR 33 to accumulate the process check character BCC for the message being received. BCC accumulation continues through the reception of the first buffer load of data and through the reception of successive buffer loads of data until the ending code (ETX character) is received.
The effects that occur when the ending code is received will be discussed later. (c) Filled buffer: LCP buffer 2
When 500 is completely filled with data, even flip-flop EVNF and memory address MADR252
A level is set to enable the setting of the buffer transfer flip-flop (BFXFRF). BFXFRF
A set of indicates that LCP buffer 2500 service is required, and LCP indicates a request for reconnection to system 10. (d) Request for reconnection to system 10: After shutdown, STCl, LCP:
Initiate a request to reconnect to the system by activating the LCP request flip-flop LCPRQF set. /O transmit flip-flop (0SF)
The set of is also activated to condition the data lines for transferring data to system 10 and the set of memory address MADR 253 (FIG. 6C) is activated to allow access to descriptor link D/L. be converted into LCP then steps to STC 5 and sends descriptor links D/L and LPW to system 10. Item MADR indicates the memory address level. These are generated on the terminal control card from the output of memory address register 36. These levels, as shown in Table M, represent address storage locations in LCP buffer 2500 (Figure 6C), which storage locations are reserved as follows. 8 LCP address levels L
The LCP address level LCPADL is active when one of the CPADn is received from the associated distribution card 200d during a reconnection sequence.

LCPADL address level is applicable to LCPAD
Generated on the terminal control card when the n level is active. The LCPADn level is also the gate system level CA
Generate TSYS to enable the LCP backplane circuitry.

The LCP CONNECTED (LCPCON) level is sent to distribution card 200d to indicate that the LCP is reconnected. SLAIN level is active and SLBIN. S
The LARAM and SLBRAM levels are inactive for the purpose of allowing descriptor link D/L to be transferred to latch register 49 (Figure 6D). (e) Transfer of descriptor link D/L and descriptor link LPW: In FIG. 7C, a transmission flip-flop (XMITF) is set at STC5.

A transmission flip-flop is located on the system logic card and set to the LCP to transfer data to system 1.
0 and therefore the LCP “read”
Indicates that the module is being driven. The LCP transfers the disk scriber link D/L and the vertical parity word LPW (previously received at the STC 6) back to the system 10. At that time, LCP is LPW register 24w
to logic [1] and STC4
Step 3 to transfer the data to system 10. (f
) Transfer data to system 10: At STC4 of FIG. 7C, transmission flip-flop XMITF and I/O transmit flip-flop IOSF are still in the "set" state from operation at STC5.

An asynchronous strobe flip-flop (ASYNCF) is set to enable asynchronous transfer of data to system 10. The data is stored in the data latch register 49 (
from the LCP buffer 2500 to the system 10 (system interface 22 in FIG. 6C) via the LCP buffer 2500 (FIG. 6D).
si). Transfer is one word at a time (
plus parity bits) will be achieved. Since the LCP strobe level LCPSTL accompanies the transfer of each word, and each word is being received by the system 10, the system sends a strobe pulse to acknowledge the reception of a word. Each word placed on terminal bus 47 of FIG. 6D for transfer to system 10 is simultaneously applied to latch register 49 and LPW register 24w.
LPW register 24w accumulates vertical parity words LPW during data transfer. LCP Batsuhua 2500 (MA
When the last data word address of the DR (DR252) is achieved, the synchronous flip-flop (SF, which is located on the terminal control card and is set when the LCP is also transferring data to the peripheral terminal) is set. is applied, resulting in a synchronization level SFL, and LCP
steps to STCl2 and sends the LPW to system 10. (g) Transmitting Vertical Parity Words to System 10: In FIG.

The LCP then enables setting the LPW register 24w to logic ``1'' and steps to STCl to retrieve additional data from the peripheral terminal device 50 (via the terminal unit interface 22di in FIG. 6C). After this, the LCP steps to STC5 and sends the descriptor printer to the main system 10.(h) Receives additional data and ending codes from the peripheral terminal: on the second entry to STCl: Both the terminal active flip-flop (TRMACTF) and the terminal receiving flip-flop (TRECF) are in the set state from the previous operation at STCl.

A terminal receive flip-flop TRECF is located on the terminal control card and is set when the LCP is receiving data from a peripheral terminal, and a terminal active flip-flop TRMACTF is located on the terminal control card and in its set state. indicates that the terminal control section of the LCP has been driven 1 for a ``read'' or ``write'' operation. The LCP buffer address is also set in MADR 255 in preparation for receiving data from peripheral terminal 50. In STCl, the operation of LCP while receiving the second buffer load of data from peripheral terminal device 50 is as follows.
To the extent that the ending code is received on the terminal bus 47, it is identical to that which takes place during the reception of the first buffer load. Assume that the following two conditions exist before receiving the end code in STCl: (1) EVNF is reset and the next character to be received is the last position character of one word ( (2) RSUARTF (reset UART flip-flop) and data store flip-flop (DATAASTF) are reset.

When the ending code character is received, the RS
UARTF is set to provide the logic level necessary to generate the write enable (ERW18) level for the Ending Code RAM. Receipt of the ending code is recognized by the LCP when the character is on the terminal bus 47. By recognizing the ending code,
An end code level EDCODE is generated, which is the data input level (R
AMl8L) and end flag bit (END
FG) is stored at the current buffer address of buffer 2500. The EVNF and DATAASTF sets are then activated, which conditions the LCP to store the ending code in buffer 2500.

EVNF is set, the ERWB (write enable level for CD digit) level is active and the character is stored in the last character position of the same word address where the end flag level ENDFG is stored. (1) Request to check BCC and reconnect to system 10: DATAASTF is set and EDCODE level is set to end flip-flop (EN
DF).

The LCP now receives the program check character BCC from the peripheral terminal device 50 and checks it against the BCC accumulated in the program check character register 33. The setting of the end flip-flop ENDF causes the terminal receive flip-flop TRECF to be set, and the end incomplete level (TMCMP) is active, terminating the operation of the terminal control section of the LCP. The LCP then initiates a request to reconnect to the system and steps from STCl to STC5 to send the descriptor link D/L to the system 10. (j)
Transfer of descriptor links D/L and descriptor links LPW: As in the previous reconnection to the system, at STC5 the LCP sends descriptor links D/L and LPW to the system, and then transfers the descriptor links D/L and LPW to the STC4 (
Read) to transfer the data to system 10. (k) Transfer data to system 10: at STC4,
The operation of the LCP is the same as described above for STC 4 until the word containing the ending code character is placed on the transfer bus for transfer to system 10.

Upon recognition of the ending code, a system end level (SYSEND) is generated and the LCP
Step 2 and send the LPW to the system 10. (1)
LPW and result descriptor R/D as system 1
Transmit to 0: LCP sends the LPW accumulated in the LPW register 24w to the system 10.

After the LPW is sent, the Termination Completion Level (TMCMP) is now active, indicating that there is no more data to be transferred, so the LCP steps to STC7 and writes the result descriptor R/ Send D to system 10. At STC7, LCP sends the result descriptor R/D to system 10, then steps to STCl5 (Figure 7D) and sends LPW, returns to play at STC3 and waits for another command from system 10. The above discussion includes a general flow path for a "read" operation in which a buffer load of data 2 or more is transferred from a peripheral device to the main system, and in which the operation involves receiving an ending code. It was then terminated.

However, other cases may occur during a "read" operation that result in alternative logic flow paths and handling of possible error conditions.

The following sections (a) to (d) are the original [readout]
Changes to the instructions are made by the system 10 or by the LCP.
It shows the action of LCP when it is done either by. (a) Reception of time-out level: Referring now to Figure 7E, consisting of two sheets 7E-1 and 7E-2, the STC
At l, if the operation of the 11 second timer is not inhibited and data is being received by the LCP from the peripheral terminal 50, and the transmission of data is prevented for 1 second, then the timeout level (TIMOUTL) is reached. is generated.

TIMOUTL is active and the end flip-flop (
ENDF) is set and the end incomplete level (TMC
MP) is generated. A request to reconnect to system 10 is initiated and LCP steps to STC5.
At STC5, the end flip-flop (ENDF) is set, the read operation is completed, and the LC
P steps to STC7 and writes the result descriptor R/D.
is sent to the system 10.

The time-out level is also set at STC3 in Figure 7E.
STC so that it can be indicated as "idle state"
3 can be taken along with LCP. (b) Transmissions still expected from the peripheral terminal: In FIG. 7E, at STCl, the LCP is conditioned to receive data from the peripheral terminal 50, and if no data is received, the LCP directly There is a condition such that the system 10 steps to STC3 and receives a conditional cancellation instruction from the system 10 as a result.

If data transmission starts, LCP returns from STC3 to STCl. (c) Request for emergency reconnection: During LCP transfer of data from the peripheral terminal device 50, when the buffer 2500 is completely filled, the buffer transfer flip-flop (BFXFRF) is set to store the data. initiates a request to reconnect to system 10.

(The buffer transfer flip-flop (BFXFRF) is set when the LCP buffer 2500 is filled with data from the peripheral terminal 50 or is empty while transferring data from the LCP to the peripheral terminal). If the reconnection is not completed before the time UART 3l receives another character, an emergency request level (EMRREQ) is generated. EMRREQ
The level is sent to the associated distribution card 200d to initiate an emergency request for reconnection to the system 10. (d
) Receipt of the Ending Code (AB digit): The action of the LCP on the reception of the Ending Code (which is placed on the AB digit (first character) of one word) is that the Ending Code to be placed on the CD digit of one word more than what is included in the reception of.

This condition exists because the transmission from the peripheral terminal consists of data subordinated by an encoding code, or because it naturally consists only of an encoding code. Additionally, decrementing the system memory address may or may not be required when storing the ending code to reflect the exact storage location of the ending code in system memory 10m. in this way,
The following behavior of LCP for these various conditions is discussed in paragraphs d1 and D2. (d1) Reception of Ending Code Following Data: If the Ending Code follows a row of data characters and the even flip-flop (EVNF) is set, the terminal bus 47
If the character is stored,
It is placed in the AB digit position of one word of the LCP buffer 2500.

When a character is received, the end code level (E
DCODE) is generated, thereby causing RAMl8L(
Write end flag level) is active and end flag level (ENDFG) is stored at the current current buffer address. (End code level (EDCO)
DE) is A whose end code character is terminal bus 47.
and is generated on the terminal control card when in the B position.
The end flag level ENDFG is generated on the data flow card from RAM 18L, and when active, this level identifies the address of the end code of LCP buffer 2500. Write end flag level (RAMl
8L) is the end flag RAM of LCP buffer 2500
data entry level). The set state of the even flip-flop (EVNF) increments the buffer address to the next word address. The data store flip-flop (DATASTF) set and even flip-flop (EVNF) complementation are enabled. EVNF is set and write enable A (ERW
A) The level is generated and the ending code is stored in the AB digits of the buffer address following the one where the end flag level (ENDFG) was stored. LCP
then initiates a request for reconnection to the main system and forwards it to the data and ending code system 10. STC4 final data to LCP buffer 25
During transfer from 00 to system 10, the 1-word AB digit ending code is recognized when the ENDFG (end flag level) level is active and the system end code level (SYSEND) is inactive. be done. This logical combination indicates that the next word to be transferred will contain the ending code in the AB position. In Figure 7E, the LPC steps to STCl4 to accomplish the transfer of one character. STCl4
A set of word transfer control flip-flops (WTCF) is enabled unconditionally. Specifies that the Character Transfer Flip-Flop (CTSF) is activated to enter the Character Transfer State. The ending code is stored in the system memory 10m, and the LCP first steps to STCl2 to send the vertical parity word LPW to the system 10, and then steps to STC7 to send the result descriptor R/D to the system 10.
send to (D2) Reception of only the ending code: Regarding FIG. 7E, if the transmission from the peripheral terminal device 50 consists of one character (end code) in STCl,
It is received on terminal bus 47 with even flip-flop EVNT in the set state and LCP buffer 2
It is placed on the AB digit position of one word in 500. The character is stored and the LCP initiates a request to the system to reconnect and transfer the character, as indicated by STC5 in the third block of Figure 7E. This steps to STC4 and when the end code level (EDCODE) is active, a set of character end flip-flops (CHARENF) are activated. The character is transferred to system 10 (STCl4) and the LCP steps to STCl2 to send the vertical parity word (LPW) to system 10. At STCl2, depending on the set state of CHARENF (character end flip-flop), LCP is directly connected to S.
Step to TC9 to start decrementing system memory address 10m. The LCP then steps to STC 7, which sends the result descriptor R/D to system 10. (e) Receiving a termination signal from the system: Whenever the available system memory space specified for an LCP operation is to be exceeded, a termination signal (TERM level) is received from the system during a read operation. Sent to LCP.

During read operations, the TERM level is STC
4, STCl4, or STCl2 (FIG. 7E). The action of the LCP when receiving the TERM level is based on the state count and at that state count, the LC
P is active when a TERM level is received, and the action is further based on whether reception of the TERM level is proceeded by receiving an ending code character from the peripheral terminal device 50. Under these conditions, the operation of LCP is explained in paragraphs e1 and E2 below. (e1) Receive termination signal before ending code is received: If the LCP receives a TERM (termination signal) level from the system before it has had enough time to receive and store the ending code, the LCP has the following effect.

e1(a) The termination flip-flop (TERMF) is set by receiving the TERM level at which the LCP is transferring data to the system at STC4, and the LCP
CP steps to STCl2. Vertical parity word L
The PW is sent to the system 10 and terminated at the termination level (TERM
The set state of F) causes the LCP to complete the read operation and step to STC 7 to send the result descriptor R/D to system 10. e1(b) 7th E
In the figure, after transferring one word containing the ending code in the CD digit to system 10, the LCP steps from STC4 to STCl2.

If TERM level can be received at STCl2 now,
The word transfer control flip-flop (WTCF) set is enabled and LCP remains at STCl2 for an additional strobe time. During the second strobe time, if the TERM level is still active, this
Indicates that the ending code was not transferred. The TERMF (termination flip-flop) is activated and the LCP steps to STC 7 to send the result descriptor R/D to system 10. e1(c) When the last word of buffer 2500 is transferred, LC
P steps from STC4 to STCl2. If T
If the ERM level is now taken at STCl2, the LC
P remains STCl2 for an additional strobe time. Regardless of the logic state of the TERM level when the word transfer control flip-flop (WTCF) is set and during the second strobe time, the LCP completes the read operation and steps to STC7 to transfer the result descriptor R/D to the system 10. send to e1(a) Moshi S
The LCP is in STCl4 if the last data word transferred in TC4 is to be subordinated by the ending code of the AB digits of the next word. If the termination (TERM) level is now received at STCl4, the ending code is not stored and the LCP steps to STCl2, which sends the LPW to the system and then sends the STC
Step 7 and send the result descriptor R/D to the system 10. (E2) Receive end signal after ending code is received: If LCP receives termination signal from peripheral terminal device 50, system 1
Upon receiving the termination level (TERM) from 0, the LCP operates as shown in paragraphs E2(a), E2(b), and E2(c) below.

E2(a) In FIG. 7E, after transferring one word containing the ending code in the CD digit to the system 10, the LCP
steps from STC4 to STCl2.

If TERM level can be received at STCl2 now,
The word transfer control flip-flop (WTCF) set is enabled and LCP remains at STCl2 for an additional strobe time. During the second strobe time, if the TERM level is no longer active, this indicates that the ending code has been transferred.
LCP steps to STC7 and writes result descriptor R.
/D to system 10. E2(b) Moshi STC4
LCP
steps from STC4 to STCl4.

If TCP does not receive TERM level and STC
Proceeding through I4, the ending code is transferred to system 10 and LCP steps to STCl2 to send the vertical parity word LPW. If a TERM level is now received at STCl2, LCP takes no action upon its reception, but steps to STC7 and sends the result descriptor R/D to system 10.
E2(c) If the transmission from the peripheral terminal device 50 consists of one character (ending code), then S
At TC4, LCP activates the character end flip-flop (CHARENF) and sets STCl
Step 2 to send the vertical parity word LPW.

If TERM level can be received now in STCl2, LC
P remains in STCl2 for an additional strobe time. During the second strobe time, if the TERM level is still active, this means that only the first half of the word containing the ending code is transferred and the system memory address is not incremented to the next word address. Indicates that LCP steps to STC 7 and sends the result descriptor R/D to system 10. If the TERM level is inactive during the second strobe time, this indicates that the system memory address has been incremented to the next word address and requires decrementing. Character end flip-flop (C
HARENF) set state and termination level (TER
The inactive state of M) causes the LCP to step to STC9 and begin decrementing the system memory address. S
From TC9, LCP steps to STC7 and sends the result descriptor R/D to system 10. Construction conditions:
While a [read] operation is in progress, certain error conditions arise that will be acted upon by the LCP as follows.

(a) Access Error: After transmitting the emergency request (EMRREQ) level, if the LCP does not receive reconnection to the system 10 before receiving the second character at UART 3l, the UART 3l transmits the overrun error level ( 0E).

Access error flip-flop (
ACCERF) and end flip-flop (END
Activate F).

LCP then initiates a request to reconnect to system 10 to complete the read operation and send an error result descriptor R/D to system 10. (b) Terminal vertical parity error data to UART3
If a parity error level (PE) is generated by UART 3l during a transfer from UART 3l to LCP buffer 2500, a terminal vertical parity error flip-flop (TVPERF) is set to detect the vertical parity error. indicates the existence of

This flop (T'VPERF) has a logic state controlled by the output from LCP vertical parity generator/checker 48 or the parity error output of UART 3l (Figure 6D). The set state of the flip-flop is such that the vertical parity error is LC.
This indicates that the occurrence occurred during data transfer between P and the peripheral terminal device 50. This flip-flop is located on the terminal control card. (c) Transfer the program check character error data (Figure 6D) to the UART3l.
If the program check character 0K level (BCCOK
), if the program check character is not active after being checked, the program check character error flip-flop (BCCERF) is set to indicate the presence of the program check character error.

The BCCOK level is provided by decoder 34 of program check character register 33 in FIG.
Write flip-to-flip operation: This operation is essentially a write operation subordinated by a read operation.

Basically, the previous discussion regarding the "write" and "read" operations of FIGS. 7B and 7C is applicable here. The ``write'' operation is initiated and the ``write'' operation is initiated by the reception of the 0P code and the command descriptor C/D for the ``write flip read'' operation to the transformation registers 42 and 43 (FIG. 6D). ) is generated.

Data is transferred from system 10 to peripheral terminal device 50 during the "write" portion of the operation. When an ending code is recognized on the terminal bus 47 during data transfer from the LCP to the peripheral terminal device 50 in the STIC (FIG. 7C), the end code level (EDCODE
) is generated.

The EDCODE level is an end flip-flop (END
F) is activated to indicate that the data transfer is complete. The set state of the end flip-flop (ENDF) and the generation of the FLIP level are determined by the read flip-flop (READF) and the terminal receive flip-flop (
TRECF), and even flip-flop (EVNF
), write flip-flop (WRITF),
Enables setting of unused flip-flop (TRMBSYE) and presetting buffer address to MADR 255. In these states of action, LC
P is conditioned to receive data from peripheral terminal 50 without reconnecting to system 10 to receive additional instructions. The LCP does not reconnect to system 10 to initiate the "read" portion of the write flip read operation.

Referring to FIG. 7E, from STCl, LCP steps to STC3 and waits for a transmission from peripheral terminal 50. By receiving the first character from the peripheral terminal device 50, the DR level (received data) of the UART 3l is active and the reset UART flip-flop (R
SUARTF) and unused flip-flops (T
Activate the set of RMBSYF). The setting of the unused flip-flop causes the LCP to return to STCl to receive data. A ``read'' operation proceeds to completion subject to the same conditions previously stated for an orderly read operation. Test Operation: "Test Operation" provides the system 10 with the ability to determine the operational state of the LCP without the need to transfer data to or from the system memory 10rT1.

A test flip-flop (TESTF) is located on the data flow card. The logic state of this flip-flop is controlled by the output level from OP code register 42 (FIG. 6D). The set state indicates that a test command has been received from system 10. In FIG. 7E, with the test flip-flop (TESTF) set at STCll, the LCP has no request to step to STC6 to receive the descriptor link D/L.

Step to STC7 instead of that person and return the result descriptor R/D to the system 10. From STC7, L
CP steps to STCl5 and then STC3
(play), where it remains until another command descriptor C/D is received. The result descriptor R/D sent to system 10 for a 1-test operation under normal conditions has all bits equal to zero. System 10 recognizes that the LCP is operational due to this condition. Test Enable Operation: Receipt of a command descriptor C/D containing a "test enable" instruction conditions the LCP so that peripheral terminal device 50 can begin communicating with system 10.

The peripheral terminal device 50 sends the inquiry character (ENQ) to the LC
Initiate a request for communication by sending to P.
When an inquiry character (ENQ) is received, the "enable test" operation is completed and the system initiates a "read" operation to receive data from the peripheral terminal 50. If the terminal sends any other character than the ENQ query character, the character is not recognized and the LCP takes no action. The “testability” operation works as follows (Section 7E
(see figure). When STC3 receives a "test enable" instruction, change register flip black 3 (VAR3F) is set.

"VAR(1-4)F" represents the four variant register levels. These are generated on the data flow card by the output of the transformation register 43 (Figure 6D). The logical states of these levels are determined by the command descriptor C/D.
Depends on the number contained in digit 1. Setting VAR3F inhibits setting the test flip-flop (TESTF) but does not allow the read flip-flop (READ) to set.
F) is allowed to be set. LCP is STCll
step to receive the command descriptor vertical parity word LPW from the system 10, and then receive the STC
Step 6 to descriptor link D from the system
/Receive L. At STC 6, the "read" flip-flop (READF) is set so that the LCP disconnects from the system 10 and steps to STCl to receive an inquiry character (ENQ) from the peripheral terminal 50. S
At TCl, the LCP steps to STC3 and waits for a transmission from peripheral terminal 50 [unless an inquiry character (ENQ) is immediately received. When a terminal transmits, the edge unused flip-flop (TRMBSYF) is set, causing the LCP to step to STCl to receive an inquiry character (ENQ). When ENQ is received, the test state of the transformation register level VAR3F inhibits the LCP from stepping to STC4 and also inhibits the transfer of system 10 characters. Instead, the LCP steps to STC7 and returns the result descriptor R/D to signify to the system 10 that the ``testable'' operation is complete. Conditional Cancel Operation: A "conditional cancel operation" provides the system 10 with the ability to cancel a previously sent command descriptor C/D, including a "read" operation.

Referring to FIG. 7E, if the LCP inhibits a "read" or "write flip read" operation, but no expected data transfer from peripheral terminal 50 is in progress, then the LCP Possible with “
It is still awaiting an order for "conditional revocation." If the conditional cancel command is received now, the ``read'' operation is canceled and the cancel flip-flop (CA
NCF) is set. This cancellation is performed by LCP
It cannot be completed unless it is on C3. At that time LCP
steps to STCll and receives one command descriptor vertical parity word LPW from system 10. The set state of the cancel flip-flop CANCF is LCP.
is prohibited from stepping to STC6. Instead, L
CP steps to STC7 and writes result descriptor R/
D back to system 10 to indicate that the conditional cancel operation has been completed. Echo Operations: ``Echo Operations'' assist in maintenance of LCP failures.

In this operation, the data is stored in 10m of system memory.
"Write" is transferred from to LCP buffer 2500.
Start with an operation. This is subordinated by a "read" operation in which the same data is transferred to system memory 10m and back. For example, suppose less than the entire buffer load of data is transferred and the operation is terminated by the reception of the ending code in the last character position of the S1 word, and the "echo operation" is essentially a read Since it is a "write operation" that is subordinated by the echo operation, the following discussion will focus on the echo operation. - Contains only those LCP effects that are unique to the (Read and write operations were previously discussed with respect to Figures 7B and 7C). Now, referring to FIG. 7E, at STC 6 and with the echo flip-flop (ECHOF) set, the LCP steps to STC 8 and receives data from system 10. Starting with STC8,
The LCP operates as described above during a regular "write" operation up to the point where the LCP receives the ending code and then steps to STCl2. Although no data should be transferred from the LCP to the peripheral terminal 50 at STCl2, the LCP disconnects from the system 10 by momentarily stepping to STCl2. When blocked in STCl, by activating the LCP request flip-flop (LCPRQF), I/O send flip-flop (IOSF) set and presetting the buffer address to MADR 253 (descriptor link, Figure 6C). By enabling the LCP to initiate a request to reconnect to the system 10. LCP steps to STC5 and sends descriptor link D/L to system 10. At STC5, the LCP transfers the descriptor link D/L to the system 10. At this time, depending on the set state of the echo flip-flop (ECHOF), the LCP steps to STC4 and returns the data in the buffer 2500 to the system memory 10r11. Starting at STC4, data is transferred from the LCP to the system 10. The actions performed by the LCP are the same as described above during a regular "read" operation, up to the point that the LCP identifies the ending code on the terminal bus 47 and then steps to STCl2. With STCl2,
Upon completion of the read operation and with the echo flip-flop (ECHOF) set, the LCP steps to STC 7 to return the result descriptor R/D to system 10. Return of result descriptor R/D:
FIG. 7D is a simplified logic flow diagram for the return of result descriptor R/D. LCP is S
Step to TC7 and write the result descriptor R based on any of the conditions posted as A, b, c, d below.
/D back to system 10. A. STCl2 or S when a “read” or echo operation is completed
TC9Ob. STC5 when a "write" operation is completed.

c. STCll when any one of the following conditions occurs.

(c1) A descriptor error occurred.

(C2) The test operation is specified by the command descriptor C/D being executed.

(C3) Conditional Cancellation Flip-Flop (CANCF)
) is set.

D. STC6 if a vertical or longitudinal parity error occurs.

In STC7, if transmission flip-flop (XMITF
) is not set, it is set at this time to drive the LCP read module.

Terminal busbar multiplexer selection A level (SLARAM)
and terminal busbar multiplexer selection B level (SLBR
AM) are active, which allows the terminal bus multiplexer network (24x2 in FIG. 6D) to select one word organized from the result descriptor level for transmission to system 10. When the result descriptor word is placed in data latch 49, it is also applied to LPW register 24w to generate the LPW for result descriptor transfer. LCP is then STC
Step 15 and send R/DLPW to system 10. At STCl5, the terminal bus multiplexer select A level (SLARAM) is inactive and the terminal bus multiplexer select B level (SLBRAM) is active, which is connected to the terminal bus multiplexer circuitry (2 in FIG. 6D).
4x2) is sent to the LPW register 2 for transmission to the system 10.
Allows selection of 4W output.

(The SLBRAM is used to select one of the four inputs to the terminal bus multiplexer network.
used with ) are generated on the system logic card from the output of the STC decoder 54 of FIG. 6D. LCP transfers LPW, resets the selected logic level to the starting state, and then steps to STC3. LCP remains at STC3 until another command descriptor C/D is received. To summarize, LCP has two "modes": "offline"
mode and "online" mode. OFFLINE MODE Operation of the LCP/terminal combination in offline mode is for the purpose of performing maintenance functions.

(Herein, various operations can be performed to verify the condition of an LCP or for simple troubleshooting. These operations are similar to the normal operation of other LCPs on the same base module.) The two basic operations controlled by the LCP in online mode operation are: (1) data received from the system by the LCP; a write operation in which data is transferred to a peripheral terminal; and (2) a read operation in which data is received from the terminal by the LCP and transferred to the system memory.

In addition to these basic operations, the LCP can change from "write" to "read" operations with one instruction, and can also perform selected test operations.

The next item (person) represents a specific operation that the LCP can perform by means of program instructions from the main system 10.
) and here follows a brief overview accomplished by each operation. The table is here, LC
We summarize the specific operations that P can perform.

Command Descriptor A command descriptor (C/D) is a main system 1 for an LCP related to an operation to be performed.
This is a command from 0.

The following item briefly summarizes the command descriptors associated with each of the instructions (tables) from main system 10. (a
) Write: The "write" command descriptor is an instruction that causes data to be transferred from the system memo I01T1 to a desired peripheral terminal device, eg, peripheral terminal device 50.

LCP Buffer 2500 Power The LCP receives data from the system 10 until it is satisfied, for example, or until data transfer is stopped by receiving an "ending code" or "termination" signal from the main system 10. When the LCP buffer of 2500 is filled, or when the Ending Co. Ichimoku is received,
The “write” command descriptor for transferring the contents of the LCP buffer 2500 to the peripheral terminal device 50 is shown in Table X below.
Identified as shown in (b) Read: The [Read] command descriptor transfers data from a peripheral terminal device, such as device 50, to the system memo
This is an instruction to transfer to.

LCP Batsuhua 25. . The LCP initially receives data from the peripheral terminal 50 until either is satisfied or data transfer is stopped by receiving an "ending code" from the peripheral terminal. LCP Batsuhua 25. . is satisfied (or an ending code is accepted), the main system 10 sends a "termination" signal and stops the read operation because the system memory space is not available to store any more data. Unless you do, LCP is a battle 2
5. . Transfer internal use to system memo January 0rn. If the LCP does not receive any data for a period of one second after a read operation is initiated, the LCP "times out" and sends a result descriptor (R/D) to the main system 10. 1 second timing period (bit (B1) of modified digit 1 of the command descriptor equal to 1)
can be prohibited by setting .

Table XIV below shows the "read" C/D. (c) Write flip read: The “write flip read” command descriptor is
Instructions to the LPC to accomplish a write operation so that a direct read operation is also free of interference from the main system 10.

Data is received from the main system 10 and transferred to the peripheral terminal device until an ending code is received.
The LCP transfers the ending code to the peripheral terminal and then changes to read mode. The LCP then receives data from the peripheral terminal and transfers it to its system memory 10n1 until an ending code is received from the peripheral terminal or a termination signal is received from the main system 10. If the LCP does not receive any data for a period of one second after the start of the read portion of the operation, the LCP "times out" and sends a result descriptor (R/D) to the main system 10. Of course, the one second time period can be inhibited, if desired, by setting bit B1 of the command descriptor variant digit 1 equal to one. Table XV below shows the "Write Flip Read" command descriptor. Table XV: (Write flip read C/D
) Note: If B1 is equal to 1, the 1 second timeout period allowed before the terminal responds is prohibited.

(d) Test: The "Test" command descriptor is an instruction to the LCP to indicate its "operational status" by returning a Results Descriptor (R/D) to the main system 10.

If LCP is present and available, all result descriptors are equal to 'O'. Table X below
VI represents a test command descriptor. Table XV
I: (Test C/D) (e) Test Enable: The "Test Enable" command descriptor monitors incoming data from a peripheral terminal device and, when receiving an inquiry character (ENQ), sends a result descriptor to the result descriptor. (R/D
) and transmit it to the system 10.
This is a command to CP.

This command is used to allow the peripheral terminal device to initiate communication with the main system 10. Table X below
WI indicates this command descriptor. Table XVII
:(Testability C/D) (f) Conditional Cancellation The "Conditional Cancellation" command descriptor allows one or more . This is an instruction to the LCP to initiate cancellation of one command descriptor.

When a conditional cancel command descriptor is received by the LCP, and if data has not been received from the peripheral edge cooler during the applicable portion of the read operation, the previous command descriptor is canceled. This C/D is shown on the front page. Table XVII: (Conditional Cancellation C/D) (g) Echo: The "echo" command descriptor is
is an instruction to the LCP to receive the entire buffer (or less) of data from the LCP and then return the same data to the main system 10 where it is to be stored.

This provides a maintenance check and troubleshooting diagnostic cycle for system LCP operation. Table XIX shows this echo command descriptor. Table XK:
(Echo C/D) A digital device that includes multiple I/O subsystems for managing data transfer operations and that includes certain modular units, such as line leg processors, base modules, input/output translators, and their interrelationships. A data processing system is described and the following claims are made.

[Brief explanation of drawings]

FIG. 1A is a schematic diagram of a central data processing system having two different types of I/O subsystems;
The /O subsystem consists of (a) input/output controllers (IOCs);
b) a central control subsystem (CC) with a) line control processor (LCP) input/output subsystem. Figures 1B, 1C, 1D and 1E are 1/
FIG. 2 is a schematic diagram illustrating various components of a centrally controlled form of the O subsystem. FIG. 2 is a schematic diagram of the modular unit of the LCPI/O subsystem, known as the LCP base module, showing its relationship to various peripheral devices. FIG. 3 is a schematic diagram of the main system central processing unit of the line control processor I/O subsystem.
FIG. 4A is a simplified schematic diagram showing the basic connections between the main system, line control processor and peripheral units within the line control processor I/O subsystem. FIG. 4B is a chart showing the various codes for various instructions that can be executed by the line control processor LCP. Figure 4C shows how four information digits (A, B, C,
D) is a chart showing how the line control processor can be organized to communicate operational results to the main system via a "result descriptor". FIG. 5A is a chart of a digital descriptor used by an input/output translator (IOT) to generate command messages (C/M). FIG. 5B is a schematic diagram showing the data field boundaries of the descriptor of FIG. 5A. Figure 5C shows the main system (
input/output translators (I/O processors and memories) and line control processors (LCPs).
This is a program diagram of OT. Figure 5D shows IO
2 is a chart showing the information array of the T descriptor register. FIG. 5E shows the message level interface between the distributed card units of the 10T and LCP base modules. FIG. 5F is a sketch of the IOT scratchpad memory. FIG. 5G is a sketch showing an address memory clutch pad of an IOT (input/output translator). FIG. 6A is a logic flow diagram of the interface between the main system and the line control processor (LCP). FIG. 6B is a generalized block diagram of the line control processor. FIG. 6C is another generalized program diagram of the line control processor in detail with respect to its data buffer memory.
Figure 6D is a detailed functional block diagram of the line control processor. FIG. 6E is a diagram showing the interworking logic and control signals between the distribution cards for the main system input/output translator (IOT) and the line control processor in the base module. FIG. 6F is a chart showing the structure of the message block and the composition of the digital words. FIG. 7A is a logic flow diagram of a line control processor that processes peripherals and shows a "state count" for "receiving commands." FIG. 7B is a flow diagram illustrating how the line control processor handles "write" operations. FIG. 7C is a flow diagram illustrating how the line control processor handles "read" operations. FIG. 7D is a flow diagram showing how the line control processor logically processes result descriptors. 7E-1 and 7E-2 together form a logic diagram showing the overall logic flow of the line control processor. In the figure, 10rr1 is a memory, 10p is a processor, 100 is a memory control, 101
IOTllOl is a PCC interface, 12 is a central control, 13a and 13b are I/O controls, 14a and 14b are peripheral devices, and 100 is an I/O channel.

Claims (1)

Claims: 1. includes a plurality of remote peripheral terminal devices 50-57, each of which peripheral terminal devices 50-57 is connected to its own specific peripheral controller 20_0_0-20_0_7; The devices 20_0_0 to 20_0_7 are designated as base modules to groups 20_0 to 20_.
7, each base module 20_0~20_
7 has its own message level interface bus 15, said message level interface bus 15 is connected to a central system with a main processor 10p and a main memory 10m via a main system interface device 10t designated as input/output translator. The base modules 20_0 to 20_7 are connected to the main system 10, and the output translator 10t is a means for connecting and disconnecting the main memory 10m and the selected peripheral controllers 20_0_0 to 20_0_7 without interrupting the main processor 10p. and further provides means for formulating I/O data transfer task commands and formulating descriptor links to identify each particular data transfer task for each particular peripheral controller. In such a system, a line control processor for operation in said system comprises: (a) means 24x_1 for receiving information and command data from peripheral devices 50-57 or said main system 10; and (b) means 24x_1 for receiving said information. Buffer memory means 25 for temporarily storing data and the instruction data
0_0, the buffer memory means 25_0_0
(b1) memory spaces 25a, 25b for storing at least one complete block of message data;
(b2) a memory space 25c for storing the instruction word received from the main system 10, and (b3) a memory space 25c for storing the descriptor link identification word generated from the main system 10 and for storing the peripheral controller 20_0_0~. a memory space 25d identifying each data transfer operation task initiated by the main system 10 associated with the peripheral controller 20_0_7; processor logic means 53p for (d) producing state condition signals for controlling the sequence of instruction steps to be executed by said peripheral controller according to a predetermined sequence and completed in the execution of said instruction data; (e) flow logic means 53f for providing signal information to said register and decoder means 53, 54, said flow logic means 53f , a line control processor in a digital system which detects each operational step in the execution of an instruction and sends the detected signals to said register and decoder means 53,54. 2 the peripheral controllers 20_0_0 to 20_0_7 are disconnected from the main system 10 and the peripheral devices 50 to 5 are disconnected from the main system 10;
means 2 for exchanging data with peripheral devices 50-57 at the speed possible of said peripheral devices 50-57 while connected to 7;
8x_128r and the peripheral controllers 20_0_0 to 20
means 23x, 23r for exchanging data independently with the main system 10 at the speed possible of the main memory 10m while the _0_7 is disconnected from the peripheral devices 50-57 and connected to the main system 10; A line control processor in a digital system according to claim 1, further comprising a line control processor. 3 means for receiving and storing an instruction word from said main system 10 and for sending said instruction word to said processor logic means 53p for execution without any other attention from said main system 10; further comprising means for generating a result descriptor signal for transmission to said main system 10 when executed, said means for generating a result descriptor signal responsive to a block message end character sent upon completion of each data transfer block. A line control processor in a digital system as claimed in claim 1, including logic. 4. The descriptor link identifier award stored in the buffer memory means 25_0_0 contains (i) information data regarding the position in the input/output translator that stores the memory address to be used by the peripheral controller, and (ii) the code. information data regarding whether translation is required at the input/output translator; (iii) information data regarding the directional flow of the data transfer to be achieved; and (iv) information regarding whether the data transfer of the memory is to be inhibited. A line control processor in a digital system according to claim 1, comprising data. 5. Said information data regarding the location of storing the memory address to be used may include (V) unique address data identifying the particular peripheral controller and (vi) unique address data identifying the base module to which the particular peripheral controller belongs. A line control processor in a digital system according to claim 4, further comprising address data. 6 Signals from the main system 10, the peripheral device 50
~57 or the peripheral controller 20_0_0
20_0_7, further comprising means for aborting the execution of a command word or data transfer and informing the main system 10 of the aborted transfer in response to a signal from . processor. 7. The buffer memory means 25_0_0 further comprises a memory space for storing result descriptor words generated by the result descriptor logic for later transfer to the main system 10. Line control processor in digital systems.