JPS5942505B2 - Data signal detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection circuit for time diversity reception.

In signal transmission systems where signal errors occur intermittently,
The possibility of errors is reduced by transmitting the data signal multiple times and then receiving it with diversity in the time axis direction on the receiving side.

Conventionally, in order to detect a signal with a low error rate, the same data signal is sent multiple times and the receiving section
For data signals that have passed through a filter, a method has been used in which the signal levels are compared in the center of an l-bit interval, stored in a shift register or memory, and a majority vote is taken to determine which signals represent the same signal. However, with this method, the value stored in the shift register or memory is determined to be either high level or low level with low accuracy, so taking a majority vote from this result is not suitable for data extraction. It has the disadvantage that sufficient accuracy cannot be obtained, and if the data signal is sent twice, discrimination by majority vote is impossible if the first and second received signals are different. It was hot. SUMMARY OF THE INVENTION An object of the present invention is to provide a data signal detection circuit that detects and reproduces data signals with higher accuracy while eliminating the above-mentioned drawbacks.

The present invention converts a data signal repeatedly sent multiple times into a high-speed pulse train having a number of pulses proportional to the pulse width, counts the high-speed pulses representing the same data signal, A data signal detection circuit detects data from this count value information.

Thereby, data signals can be detected with high accuracy, and signals can be discriminated and extracted even when the number of data transmissions is two.

Next, details will be explained with reference to the drawings.

FIG. 1 is a block diagram of a conventional signal detection circuit. Port 1 is a filter, into which the received signal S is input.

102 is a comparator for converting the output of filter 1 port 1 into a digital signal, and 103 is a shift register, which shifts the output of comparator 102 bit by bit.

Ck is a clock pulse for shifting a signal in the first port 3 of the shift register.

al, a2, . . . , a1O, all, .
Reference numeral 104 is a majority circuit for making a majority decision regarding signals representing the same signal from among signals sent repeatedly.

FIG. 1 shows a case where a 10-bit signal is repeatedly transmitted, and the ]th bit, 11th bit, etc. represent the same signal. for example,
When sending three times, if the number of high level signals among Al, all, and a2l is greater than the number of low level signals, the output of the majority circuit 104 becomes high level. That is, 3
In the case of forwarding, even if one bit is mistaken, if the other two bits are received correctly, the received signal will not be mistaken. However, in this method, since the outputs compared by the comparator 102 are input to the shift register 103, the signal value stored in the shift register 103 is determined to be either a high level or a low level. From the information of this shift register, it is necessary to make a majority decision on the incoming signal (well, there is a drawback that sufficient judgment accuracy cannot be obtained,
In addition, when the data signal is sent twice, if the received signal value is different from the first time and the second time, it is determined by majority vote (which was impossible.
The figure is an example of a block diagram of the circuit of the invention.

This is a case where a signal consisting of 10 bits is repeatedly transmitted.

31 (a comparator for comparing whether the input signal is high level or low level; 32 is a gate circuit for passing or cutting off pulses Ch faster than the comparison output of the comparator 31; 1;
2 . . . 10 are gate circuits each of which opens the gate for one bit in a period of 10 bits.

That is, the gate circuit 36 consisting of 31, 32 and 1, 2, . Ml, m2,・
..., is output as MlO. 11, 12...
- 20 is a counting comparison circuit, which uses a counter in this case.

If the count value of the counter is greater than a certain reference value, the counter output rises. Counter 11, 12...
..., 20 is a reset pulse for clearing each counter before the signal is sent.For example, when the signal is sent twice, the gate circuit 1 The gate will open twice, but the counter 11
is the sum of the number of high-speed pulses proportional to the pulse width of the first received signal and the number of high-speed pulses proportional to the pulse width of the second received signal. 21, 22
...30 and 33 are gate circuits for sequentially opening the gates for the output of each count comparison circuit; 34;
(This is a timing extraction circuit for extracting data from the output of the gate circuit 33.

38 is the counter 11, 12, . . . of the received data signal.
In .

For example, from the first bit of the last signal sent, G becomes high level, and detection data is sequentially output.
Each count comparison circuit 11, 12...
・The results of the comparison of the count value information by 20 are extracted and output bit by bit.

35 are respective gate circuits 1, 2...10
and 21 to 30 are gate signal generation circuits that generate pulses gl to GlO for opening the gates for one bit time in a 10-bit period.When each gate receives the first bit, the gate circuits 1, 21 opens, and when the second bit signal is received (well, gate circuits 2 and 22 open, and furthermore, the first bit), gate circuit 1 is opened again.
, 21 will be held.

35 (Well, as shown in the block diagram of Figure 3, the final output QlO of the shift register consisting of 10 stages is fed back to the input D1, and a high level signal is preset only to the first stage shift register. They are shifted in order and gl to GlO are taken out from the output of each shift register 38 to 47.

FIG. 4 is a time chart for explaining FIG. 2. At the output of the gate circuit 1 which is opened for l bit period in a 10-bit period (well, when the signal S is positive, the pulse train ml which is the output of the gate circuit 2 is generated.

nl is the count value of the counter 11, and by counting the pulse train of m1, a certain reference value Nc
If it is larger, the output of the counter 11 rises. For example, Nc is the waveform Xl, XIl, . . . at the 1st bit, 11th bit, . . . of the input waveform S.
..., the value that the counter 11 counts when the sum of the times that become positive and the sum of the times that become negative are exactly the same. In this case, the data waveforms X1 and Xll of the 1st and 11th bits are severely distorted, but since the third data waveform X2l is at a sufficient level, as a whole,
The count value of the counter 11 exceeds the reference value Nc, and the output of the counter 11 becomes high level.
Data can be detected without any effort. With traditional means,
For example, if the number of data transmissions is only 3, X1 and
, , are completely distorted, no matter how sufficient the waveform of X2, is, Xl,
When taking a majority vote of the results obtained by sampling at the center of the waveform of 2l, the error probability was 1/4, which was a large error, but according to the present invention, X1 and X,l are Even if it is completely distorted, if X2l is a sufficiently ideal waveform, the data will be accurately reproduced as long as the sum of the times when X1 and Xll are positive is less than half the pulse width of one bit interval. As a result, the reception error T (is very small).

In addition, when the number of data transmissions is only two, the results obtained by sampling at the center of the waveforms of X, and X, using the conventional method (or However, in the case of the present invention (well, X1 and
Since the detection is based on the sum of the times during which the waveform of ll is positive, the data can be determined. Although the above description is based on the case where the data length of repeatedly sent information is 10 bits, the present invention can be implemented with a similar circuit configuration even in the case of any general data length.

As explained above, the present invention can be used to transmit the same information several times in a data transmission system where the S/N ratio deteriorates intermittently and errors occur.
Data signals can be extracted with high accuracy, and even when information is sent only twice, it is possible to detect each received signal.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional data signal detection circuit, and Figure 2 is a block diagram of a conventional data signal detection circuit.
Figure 3 is a block diagram of an embodiment of the data signal detection circuit according to the present invention, Figure 3 is a block diagram of the gate signal generation circuit used in the present invention, and Figure 4 is a time chart for explaining Figure 2. In the figure, 1, 2...10, 21, 22...
...30,32,33,36,38...Gate circuit, 11,12...20...Counter, 31,102...Comparison Vessel, 34...
...Timing extraction circuit, 35...Gate signal generation circuit, 37...Signal extraction circuit, 38,3
9...47, 103...Shift register, 101...Filter, 104...
It is a majority voting circuit.

Claims (1)

[Claims] 1. A gate signal generation circuit that forms a gate corresponding to a predetermined number of bits in synchronization with a data signal of a predetermined number of bits that is repeatedly transmitted multiple times, and a high-speed pulse train when the input signal of the data signal is at a predetermined input level or higher. each gate circuit corresponding to each of the bits inputted, each counter circuit that counts high-speed pulses of the output of each gate circuit and outputs an output when the count exceeds a predetermined number, and the output of the counter circuit is input to each of the gates. and a signal extraction circuit that extracts the data signal as a data signal.