JPS5942514B2 - Recorded signal playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is designed so that when a video signal is recorded on a rotating recording medium, the rotational speed of the rotating recording medium can be appropriately controlled during reproduction.

An example of the recording signal reproducing apparatus according to the present invention is shown in FIG. 1 below.
The figure will be explained along with its operation. 1 is a video signal source, ie, a television camera in this example, and a vertical synchronizing signal VD obtained at an output terminal 5a of an oscillator 5 and an output terminal 5b.
The camera 1 is driven by the horizontal synchronization signal HD obtained in FIG.
A video signal 51 shown in is obtained and supplied to the mixer 26.

Note that B in the same figure shows the vertical synchronizing signal VD, and C in the same figure shows the horizontal synchronizing signal HD. Both of the above-mentioned synchronizing signals VD and HD are supplied as trigger signals to the bistable circuit 8 through the AND circuit 7, respectively.

Signals VD and HD are synchronized every 2 fields, i.e. 1
Since it is frame by frame, this bistable circuit 8 is triggered every frame before the vertical synchronization signal VD, that is, at its leading edge, it is inverted as shown in FIG. 2L, and thus the output terminal Ba
The output states (1 and 0) of 8b and 8b are also inverted every frame. Now, assuming that the output of terminal Ba is 1 and 8b is o, the first gate circuit 3a is turned on by the output 1 of the output terminal Ba of the bistable circuit 8, and the audio signal from the microphone 2 is transmitted through this. First audio signal storage circuit (
(hereinafter abbreviated as CTD0) 4a. This CT
The DI 4a is configured to sequentially accumulate audio signals corresponding to one frame period in accordance with the inversion period of the bistable circuit 8 described above. This CTDI can use a well-known charge transfer circuit, and the repetition frequency obtained at the output terminal 5c of the oscillator 5 is a long-period clock pulse (hereinafter simply referred to as C pulse Pl) of several MH2 or more than ten MH2. , which can be sampled and written to the capacitors constituting the . CTD
2 has a similar configuration and is designated as the second. Note that 3b is a second gate circuit, which is controlled by a signal from the output terminal 8b of the bistable circuit 8. Now, since the output of the output terminal Ba of the bistable circuit 8 is 1, the AND circuit 9 is opened.
The C pulse Pl obtained at the output terminal 5c of the oscillator 5 passes through the AND circuit 9 and the OR circuit 13 to the first CTD 1, 4.
A is supplied to the clock pulse input terminal of C pulse Pl, and writing is performed as described above using this C pulse Pl.

On the other hand, the C pulse Pl obtained at the output terminal 5c of the oscillator 5 is supplied to a frequency multiplier 6, and the output side thereof is a short-period clock pulse in which the repetition frequency of the C pulse Pl obtained at the terminal 5a is multiplied by N times. (hereinafter simply C pulse Ps
) is obtained. The outputs from the output terminals 8a and 8b of the bistable circuit 8 are supplied to the monostable circuit 16, and the output Sl6 remains unchanged for several H (1H is one horizontal period) from the time the output of the output terminal 8a or 8b becomes 1. is set to 1 (see FIG. 2D).

In addition, the horizontal synchronization signal HD is transmitted to the first, second, and third counters 1
For example, the first counter 17 counts eight pulses, the second one 18 counts seven pulses, and the third one 19 counts one pulse. It is assumed that the output of the counter 17 is 1. Now, the bistable circuit 8 is inverted by the leading edge of the vertical synchronizing signal VD, and the terminal 8
When the output of b becomes 1 (8a is O), the gate circuit 3b opens, and the C pulse Pl goes through the AND circuit 11 and the OR circuit 1.
4 to the second CTD 2, 4b, the audio signal from the microphone 2 is supplied to the second CTD 2, 4b.
written to b.

At the same time, as mentioned above, the monostable circuit 16 outputs Sl.
6 is obtained, and the counters 17 and 18 each start counting. 2E shows the output of the counter 17, and FIG. 2F shows the output of the counter 18 supplied to the inverter 21. Both of these output signals Sl7 and S2l are supplied to the AND circuit 22. Therefore, in this example, the AND output S22 becomes a pulse having a width of 1H as shown in FIG. 2G. This pulse S22 is further supplied to the monostable circuit 20, and the output side of the monostable circuit 20 has a pulse S22 as shown in FIG. 2H.
Output AS2O triggered on the trailing edge of 2 and having a predetermined width
is obtained and supplied to the third counter 19. Therefore, this counter 19 counts, for example, one horizontal pulse within the period of 1 of this output S2O, and the output S,9 of the counting period becomes 1 as shown in FIG. This is supplied to AND circuits 10 and 12, which are opened during the period of output 1 of this output signal Sl. Therefore, after the first counter 17 finishes counting, the third counter 19 operates, and during this operation period, the above-mentioned first counter 19 is Reading from CTD, , 4a is performed at a speed N times the writing speed. Therefore, as is clear from FIG. 2, the readout from the first CTD1, 4a is compressed within the count determined by the counter 19 from a position delayed by the count of the counter 17 from the leading edge of the vertical synchronizing signal VD. It is sent to the mixer 15. Further, the output S, 6 of the monostable circuit 16 is selected to be longer than the counting period of the counters 17, 18, and the output S, 6 of the monostable circuit 20 is selected to be longer than the counting period of the counters 17, 18.
2O is selected to be longer than the counting period of the counter 19. On the other hand, the output S22 of the AND circuit 22 is further supplied to, for example, a monostable circuit 25 as an audio synchronization circuit, and this output S25 (see FIG. 2 J) is used to generate a horizontal synchronization signal following the output S22 of the AND circuit 22 For example, one item is deleted.

This missing portion of the horizontal synchronization signal serves as a cue signal for reading during playback. In this way, the composite signal S26 shown in FIG. 2K is obtained at the output side of the mixer 26. Note that Ss in the figure is a compressed audio signal for one frame. The above operation is repeated every time the bistable circuit 8 is inverted, that is, every frame. Therefore, in this example,
The audio signal is compressed and inserted into one frame in the vertical blanking period following either the odd or even field, for example, the even field. Such a composite signal S26 is supplied to a modulator 27 at the next stage, where it is subjected to frequency modulation, for example, and this is further supplied to a cutting device 28 and recorded on a disk 31.

29 is its substrate, 30 is a cutting arm, and 32 is a motor.

3 and 4 regarding this cutting device 28.
This will be explained using figures.

The arm 30 is configured to be sent along the extending direction of the guide 32 by a guide 32 and a feed screw 33,
Inside the arm 30 is a light source such as a semiconductor laser 34, a KDP
A deflector 35, a half mirror 36, and a photosensitive element 37 are housed therein. However, the modulator 27 explained in FIG.
By supplying the output from the semiconductor laser 34 to the semiconductor laser 34, the laser beam emitted from the semiconductor laser 34 is modulated. This laser beam is horizontally deflected by a deflector 35 in synchronization with the horizontal synchronizing signal HD. The direction of this horizontal deflection is the radial direction of the disk 31. The laser beam thus horizontally deflected is directed toward the disk 31 by the half mirror 36, focused by the focusing lens 38, and reaches the disk 31. In this way, a record as shown in an enlarged form in FIG. 5 is made on this disk 31. That is, a large number of recesses 39 whose widths are modulated according to the signal to be recorded are arranged in a horizontal direction (approximately in the radial direction of the disc 31). In order to facilitate understanding of this figure, the video signal SH for 1H is shown in the horizontal scanning direction, and the signal Sv of the vertical blanking period of the video signal is shown in the moving direction of the board 31. In addition, 1 is on the left end of such a record.
A recess 40 is formed for each H to provide a synchronization signal for speed servo. In this way, one unit period (1H period) of the video signal is recorded as a time axis modulated signal in a direction crossing the spiral recording track T. Next, reproduction from such recording will be explained.

During reproduction, by emitting an atonal light beam from the light source 34, the light beam irradiated onto the disc 31 is reflected by the half mirror 36, passes through the half mirror 36, and enters the photosensitive element 37. be done. Therefore, by deflecting the light beam with the deflector 35 in the same manner as during recording, it is possible to scan the light beam on the record shown in FIG. Can be picked up. The reproducing device will be explained below using FIG.
3, the signal is demodulated, and output as a video signal to an output terminal 46 through an amplifier 44 and a video output circuit 45 (see FIG. 7A).

A part of the demodulated video signal is supplied to a synchronization signal separation circuit 47, and its output terminal 47a outputs a vertical synchronization signal VD, and its output terminal 47b outputs a horizontal synchronization signal H shown in FIG. 7B.
D is taken out respectively. This figure shows a place where one pulse of the horizontal synchronizing signal HD indicating the cue of the above-mentioned audio signal compression recording position is missing. Horizontal synchronization signal HD is AFC
It is supplied through a circuit 48 to an oscillator 49 from which a horizontal synchronizing signal D having a continuous pulse train as shown in FIG. 7C is obtained. This horizontal synchronizing signal 1rD and the above-mentioned horizontal synchronizing signal HD with the deletion are supplied to the first bistable circuit 51 through the AND circuit 50, and the signal S5l shown in FIG. 7D is obtained at its output side. On the other hand, the horizontal synchronizing signal H'D without deletion is supplied to the second bistable circuit 52, and the signal S52 shown in FIG. 7E is obtained at its output side. Incidentally, both bistable circuits 51 and 52 are supplied with a vertical synchronizing signal D, and are configured to operate respectively only during the arrival time of this signal. Output signals S5l and S52 of these first and second bistable circuits 51 and 52
is supplied to the AND circuit 53, and a pulse S53 shown in FIG. 7F is obtained at its output side.

This pulse S53 becomes a cue signal indicating the audio compression recording position. On the other hand, the vertical synchronization signal VD is transmitted to the third bistable circuit 5.
4, and on its output side there is an output signal S shown in FIG. 7G.
54 is obtained, which is further supplied to a fourth bistable circuit 55.

Therefore, an output signal S55 shown in FIG. 7H is obtained from the output terminal 55a. Note that an inverted signal of the above-mentioned signal S55 is obtained from the output terminal 55b. The horizontal synchronizing signal D is supplied to the counter 56 and set at the output S53 (FIG. 7F) from the AND circuit 53 mentioned above, and after this output signal S53 arrives, the counter 56 outputs the signal I D. It is counted.

This count value is selected for the period during which the audio is compressed and recorded (1H in the above example), and therefore one pulse is counted, during which the output S56 from this counter 56 is 1H.
(Figure 7). This output signal S56 is supplied to an electronic switch 57, which is switched, for example, every frame by the output from the fourth bistable circuit 55, and is converted and supplied to AND circuits 59 and 60, respectively. The signal is converted to the first and second gate circuits 64a and 64b and supplied as a gate signal. Further, a part of the video signal is supplied to a clock pulse generation circuit 68, and, for example, a horizontal synchronizing signal H
A pulse is obtained at its output in synchronization with D.

This pulse has the same cycle as the short cycle used during recording, that is, the C pulse Ps, and will be described below as the C pulse Ps. A part of this C pulse Ps is supplied to the frequency down-down circuit 69, and has the same period as that of the long period used during recording, that is, the C pulse Pl.
This will be explained as 1. Therefore, if the output of the output terminal 55a of the bistable circuit 8 is 1 and the switch 57 is in the solid line state, the output S56 of the switch 57 (FIG. 7)
The AND circuit 61 and the gate circuit 64a are opened, and C
The pulse Ps is supplied as a clock pulse to the first CTD1 through the AND circuit 61 and the OR circuit 63,
As a result, the audio signal compressed and inserted next to the cue signal S53 is written to the first CTDl at a high speed. On the other hand, since the output of the terminal 55a is 1, the AND circuit 58 is open during this one frame period, and the C
The pulse Pl is supplied as a clock pulse to the second CTD 2 through the AND circuit 58 and the OR circuit 62,
In this CTD2, the audio signal accumulated during the previous one frame period is read out over one frame period, and this is obtained through the mixer 66 to the output terminal 67.

Similarly, when the bistable circuit 8 is inverted, the switch 57 is switched to the dotted line state, and contrary to the above, reading is performed from the first CTD1 for one frame period, and the second CTD1 is read out for one frame period.
Writing is done to D2. Therefore, it is possible to reproduce a signal compressed and recorded in a 1H or several H period of the vertical blanking period at the speed at which it was recorded. Note that the first and second CTDs and CTD2 have the same configuration as that explained at the time of recording. Next, a tracking servo system for the KDP deflector 35 during reproduction will be explained using FIG. 8.

In this example, parts corresponding to those in FIG. 6 are designated by the same reference numerals. In this figure, 71 is a reference signal oscillator, from which the repetition frequency as shown in FIG. 9A is the above-mentioned horizontal synchronizing signal H. It is assumed that a reference signal Sa equal to . This reference signal Sa is supplied to the sawtooth signal generation circuit 72, and an output Sb shown in FIG. 9B is obtained on its output side.This is supplied to the peak value holding circuit 73, and the peak value Retained. On the other hand, the horizontal synchronization signal HD (FIG. 9C) obtained at the output terminal 47b of the synchronization separation circuit 47 is also supplied to the sawtooth wave signal generation circuit 74, and the sawtooth wave signal Sb shown in FIG. is obtained, which is supplied to the peak value holding circuit 75 and held at the peak value Ed. Both voltages Eb and Ed obtained in this way are supplied to a voltage comparison circuit 76, respectively. That is, the comparison circuit 76 compares the frequencies of the reference signal Sa from the oscillator 71 and the synchronization signal HO in the reproduced video signal. Thus, the error signal (voltage) Ee (FIG. 9E) is obtained. In addition, both signals S
b (5Sd) are selected so that they are the same. This error signal Ee is supplied to the KDP drive sawtooth wave generation circuit 77, and the KDP deflector shown in FIG. 10 is generated by the reference signal Sa. The slope of the 1 drive signal Sh of 35 is changed as shown by a dashed line or a dotted line.This controls the deflection width (width) of the laser beam by the KDP deflector 35.Thus, the reference signal When Sa matches the horizontal synchronization signal HD to be reproduced, the deflection width of the laser beam matches that during recording.Furthermore, the above-mentioned sawtooth wave signal S
b is supplied to a sampling circuit 78, where it is sampled by the reproduced horizontal synchronizing signal HD, and supplied to a hold circuit 79 to obtain a voltage Eh.

On the other hand, when the output of the voltage comparator circuit 76 becomes O, that is, the error signal Ee becomes 0, an output of 1 is obtained from the coincidence determination circuit 80, the gate circuit 81 is opened, and the voltage Eh obtained from the hold circuit 79 becomes the bias setting. It is supplied to a circuit 82, and its output is given to the KDP deflector 35 as a bias as shown in FIG. 10, so as to set the deflection position of the laser beam. Therefore, since the amplitude of the laser beam is controlled as described above and its phase is controlled by the output of the bias setting circuit 82, the recording on the disc 31 can be accurately tracked. Therefore, the sampling circuit 7
Reference numeral 8 compares the recording position on the disk 31 and the phase of the laser beam. The determination circuit 83 determines that the phases match and that the output from the hold circuit 79 has reached a certain set value, and the output opens the gate circuit 84 and supplies the video signal to the receiver 85. A reproduced image can be obtained. Furthermore, during reproduction, by rotating the half mirror 36 back and forth around its center P within a certain range in synchronization with the vertical synchronization signal D, the laser beam is vertically scanned (in the direction of movement of the disc 31 in FIG. 5). Therefore, if the above-described operation is performed with the rotation of the disc 31 stopped, a so-called still image can also be reproduced.

In this case, a KDP deflector may be further provided in the arm 30 without rotating the half mirror 36, thereby allowing the same vertical scanning as described above. Furthermore, as is clear from FIG. 5, a synchronizing signal 40 is recorded along the track T in correspondence with, for example, the period of the horizontal synchronizing signal, and although not shown, this is recorded on a photosensitive element 37 provided separately from the photosensitive element 37. The detection signal is detected by the element, and the motor 32
It is also possible to apply a speed servo to.

Therefore, in this case, the rotation is at a constant linear velocity. Incidentally, if the synchronization signal 40 is not recorded, it is also possible to configure the line shown in FIG. 11.

This will be explained below. Demodulator 43 as described above
It is demodulated by A, and synchronously separated by a synchronous separation circuit 47.
The oscillator 86 is triggered by the horizontal synchronizing signal H/D, which is supplemented by the missing horizontal pulse for cueing in the FC circuit 48, and the oscillator 86 is generated by N times the horizontal synchronizing signal (N is a positive integer). A pulse PN having a repetition frequency of is generated and counted by a counter 87. On the other hand, a vertical synchronization signal V from a vertical synchronization signal oscillator 88 is used as a reference signal. is supplied to the counter 87 described above as a set signal (counting start signal), and counting of pulses PN is started from this. It is assumed that this counter outputs 1 after counting (525-X)N. Note that X is a positive integer, preferably about 5, for example. The output from the oscillator 88 is supplied to the inverter 89, and its output (output for one vertical period 1)
and the output from the counter 87 are supplied to an AND circuit 90. Therefore, if X is now 5 and N is 1, the counter 87
After counting 520 pulses, the pulse PN from the oscillator 86 is passed through the AND circuit 90 to the counter 9 at the next stage.
1 and counting starts. This counter 91 counts the number of pulses equal to or greater than NX. Therefore, in the above example (when N=1), this counter 91 counts 5 pulses during normal rotation of the board. . This count value is supplied to the DA converter 92, and a voltage corresponding to the above-mentioned count value is obtained from the output terminal 92b.
On the other hand, it is assumed that the same voltage as 525 pulses counted in the converter 92 is obtained from the output terminal 92b, and both of these output voltages are supplied to the voltage comparison circuit 93, and the error voltage is supplied to the motor 32 as its speed servo. be done.
Therefore, since this servo is performed only by the count of the counter 91, the total number of pulses within 2 vertical periods in the reproduced signal is compared with 525 pulses, and the motor is controlled by the comparison output. This has the advantage that the sensitivity is greatly improved compared to the case where 32 is servoed. In this case, the horizontal synchronizing signal is multiplied by N by the oscillator 86, and accordingly, the counter 87 counts (525-X)N, and the counter 91 counts NX. Therefore, it is possible to perform servo with even higher precision. In this example, the horizontal synchronizing signal HD is further supplied to a frequency discriminator 94 to detect frequency fluctuations, and its output is supplied to a capacitor 96 through a detector 95, which is then input to a mixer 97 from the above-mentioned comparison circuit 93. The output is mixed with the output of the servo and used for the servo, and therefore it is also possible to correct differential velocity unevenness.

FIG. 12 shows another embodiment in which the horizontal synchronization signal I D separated by the horizontal synchronization separation circuit 47 is sent to the AFC circuit 98.
is supplied to the oscillator 99 through the oscillator 99 to obtain a horizontal synchronizing signal from which the equivalent pulse has been removed and which has been supplemented with the cueing pulse described above.

On the other hand, the vertical synchronization signal VD as a reference signal is supplied to the phase inversion circuit 100, and an output that becomes 1 except for the vertical synchronization signal is obtained on the output side, and this output and the output from the oscillator 99 are supplied to the AND circuit 101. be done. Therefore, the oscillator 9
A horizontal synchronizing signal HD from 9 is supplied to a counter 102. Further, the count value of this counter 102 is reset every time the vertical synchronizing signal VD is received; counting is started again from the beginning. The output of this counter 102 is sent to a DA converter 103.
The output from the phase inversion circuit 100 is sent to the triangular wave signal generation circuit 1.
04, and their outputs (voltages) are compared in voltage by a voltage comparison circuit 105, and the error signal (voltage) is used for servoing the motor 32. In the example shown in Figure 1, the audio signal is compressed and recorded within the vertical blanking period, but it is also possible to similarly compress and record the audio signal within the horizontal blanking period. You can also do it.

Further, although the case where recording is performed on a disk has been described, it is also possible to record on a cylindrical surface in the same manner. In this case, the vertical blanking periods can be selected so that they are aligned on a line along the axial direction of the cylinder on a part of the cylindrical surface. According to the present invention as described above, the rotating recording medium can be rotated at a prescribed speed using the output from the reference signal oscillator, and thus the rotating recording medium can be rotated at the same speed as when recording. It has the characteristic that it can be

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a rotational recording device according to the present invention, FIG. 2 is a waveform diagram used to explain its operation, and FIG.
The figure is a plan view of a device that can be used in the present invention, FIG. 4 is a side view of the device, and FIG. 5 is an enlarged view of a part of the recording part.
Figure 6 is a block diagram of the playback device, Figure 7 is a waveform diagram used for its explanation, Figure 8 is a control circuit diagram for the KDP deflector, and Figures 9 and 10 are waveform diagrams for its operation. ,
FIGS. 11 and 12 are block diagrams for speed servo during reproduction, respectively. 1 is a video signal source such as a camera, 2 is a microphone, 3a,
3b is a gate circuit; 4a and 4b are charge transfer devices; 5 is an oscillator for horizontal signals, vertical signals, and clock signals; 6 is a clock signal repetition frequency multiplier; 8 is a bistable circuit; 9, 10, 11, and 12. are AND circuits, 13 and 1, respectively.
4 is an OR circuit, 15 is a mixer, 16 is a monostable circuit, 17
, 18 and 19 are counters, 25 is a circuit for removing one horizontal pulse, and 27 is a time axis modulator.

Claims (1)

[Claims] 1. Reproducing and separating a horizontal synchronization signal from a video signal recorded on a rotating recording medium, and supplying this horizontal synchronization signal to a counter that obtains an output whose state changes when a predetermined count value is reached;
The counter is set by the output from the reference signal oscillator, and the output of the reference signal oscillator is compared with the output of the counter, and the rotational speed of the rotating recording medium is controlled by this comparison output. A device for reproducing recorded signals.