JPS5942986B2 - semiconductor memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory cell suitable for forming an IIL logic gate circuit.

In recent years, in order to improve the degree of integration of integrated circuits, separation is not required.
IL (Integrated Injection Log)
ic) Logic gate circuits are being used.

A semiconductor memory cell using such an IIL logic gate circuit is described in, for example, Japanese Patent Laid-Open No. 49-24329. Here, reading and writing of a large number of flip-flop type memory cells arranged in a matrix is performed selectively for each cell. In the case of reading, power is temporarily cut off for cells other than the selected memory, but the memory contents of those cells are retained by the inherent capacitance of the bipolar transistors that constitute the cells. However, since the retention time of the stored contents by such capacitance is very short, reading and writing to and from cells must necessarily be performed at high speed. Therefore, it is necessary to design the circuit configuration and structure of the memory device including the memory cells such that it is suitable for increasing the speed.

Furthermore, a complicated sensing circuit is required to sense the signal read from the memory cell, which increases the area occupied by the memory device. When reading and writing from memory molecules arranged in a matrix, it is often required to process not in bit units but in word units consisting of multiple bits, but with the memory cell configuration described above, such word units are cannot read or write.

The present invention was made in view of the above circumstances, and its purpose is to eliminate the need for a complicated sensing circuit, occupy a small area, do not necessarily require high speed for reading and writing, and write data in word units. The present invention provides a semiconductor memory cell that can read and write data.

Therefore, according to the present invention, first and second cross-connected first and second conductivity types constituting a flip-flop type memory cell are provided.
The current rises of the transistors are set unbalanced, and the collector of the first or second transistor is connected to the first conductivity type transistor connected to the data line and the second conductivity type transistor connected to the data line.
By connecting a load, such as a transistor of the second conductivity type, to the column selection line of the column selection line and operating these circuits for reading, a complicated sensing circuit is not necessarily required, low-speed operation is possible, and word-by-word processing is possible. The present invention provides a semiconductor memory cell that can be read and written.

The details of the present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The first and second transistors Tl and T2 of the first conductivity type (NPN type in the figure) are cross-connected by wirings 2 and 3, the base of one is connected to the collector of the other, and the emitters are commonly connected. There is. Each of these transistors Tl,
Between the collectors of T and the first column selection line (word line) W, there is a load impedance, for example, the collectors and emitters of transistors T3 and T4 of the second conductivity type (PNP type in the figure) whose bases are commonly connected. It is connected.
The collector and emitter of a transistor T5 of a second conductivity type (PNP type in the figure) are connected between the base of one of the pair of transistors Tl and T2 and the data line D, respectively. The base of this transistor T5 is grounded, and the first
and the common emitters of the second transistors Tl, T, are held at the same potential. The transistor T2 of the first conductivity type is 2
One collector region is connected to the collector of the transistor T4, and the other collector region is of the first conductivity type (NPN type in the figure) through the wiring 4.
is connected to the base of transistor T6. The emitter of this transistor T6 is grounded, and the collector is connected to the data line D. The base of the transistor T6 has an impedance, for example, a second conductivity type (PNP in the figure).
The collector of the transistor T7 (type) is connected to the base of the transistor T7, and the base of the transistor T7 is grounded, and the emitter of the transistor T7 is connected to the second column selection line R.

FIG. 2 shows how the memory cell thus configured is constructed and patterned using IIL logic gate circuits.

In the figure, the shaded area is a P-type region, the other areas are N-type regions, and the area surrounded by a dotted line is one memory cell 5. In the figure, I
An IL logic gate circuit is constructed, and transistors Tl, T
4 constitutes another IIL logic gate circuit, and transistors T6 and T7 constitute yet another 11L logic gate circuit.

FIG. 3 shows a cross section taken along line A-A' in FIG. 2. FIG. 4 shows how a large number of memory cells configured in this manner are arranged in a matrix of N rows and M rows.

(1, 1), (1, 2), . . . (M, N) indicate each memory cell, each having the same structure as the cells shown in FIGS. 1 to 3. D1~DN are data lines, W1~
WM is a first column selection line, and R1 to RM are second column selection lines.

Next, the operation of the above-mentioned memory cell will be explained.

It is now assumed that each memory cell holds predetermined storage contents. In this state, the first column selection lines W1 to WM
is set to a high potential, for example ~0.7V, and one of the cross-connected transistors Tl and T2 is conductive and the other is non-conductive. When reading memory contents,
While the first column selection lines W1 to WN are held at a high potential (~0.7V), the second column selection line Ri connected to the memory cell column to be read is set to a high potential, and the other column selection lines 2
Set the column select line to a low potential. Then, the transistor T6 of the selected cell column becomes conductive or non-conductive in accordance with the conductive or non-conductive state of the transistor T1 constituting the cell.

For this reason, from the data line D, 05
In this case, since the transistors T6 and T7 constitute an IIL logic gate circuit, the signals obtained from the collector of the transistor T6 are ``0'', ``'1''''. The memory contents of the cell can be sufficiently sensed even without a particular sensing circuit. When the data line D becomes ゜゜0゛'', there is a possibility that current flows into the data line D through the transistor T5 of the cell in another column, but if the current amplification factor β of the transistor T6 is large, it is sufficient to D can be set to the ゜゜0'' level. Note that reading may be performed by connecting the collector of the transistor T6 to a data line provided separately from the data line D. Next, write to a desired memory cell. When performing this, the first column selection line Wi connected to the memory cell column to be written is set to a low potential, and the other first column selection lines are set to a high potential.

Then, the second column selection lines R1 to RM are set to a low potential, and the data lines D1 to DN connected to each memory cell are set to a high or low potential according to the information to be written, and then the first column selection is performed again. Bring the line Wi to a high potential. For example, if the data line D is set to a high potential, the memory cell (1, i
) through the transistor T5 constituting the transistor T
A current is supplied to the base of transistor T2, and transistor T2 becomes conductive, and transistor T1 becomes non-conductive. In other words, ゜゜1″″ is written. This state is the first column selection line Wi
is retained even after being returned to a high potential. Conversely, if the data line D is set to a low potential, the initial transistors Tl and T2
are both non-conductive, but then when the first column selection line Wi becomes a high potential, the transistor T1 becomes conductive, and the transistor T1 becomes conductive.
, becomes non-conductive. In other words, "0y" is written.As is clear in FIG.
Since the base area of the transistor T1 is larger than that of the transistor T1, the capacitance is large, and current flows from the transistor T2 to the data line D via the transistor T5.
This is because the base potential of , rises faster. In this way, desired information is written into the memory cell column to be written. Thereafter, by setting the first column selection line Wi to a high potential, the stored contents are retained. During such a write operation, since the first column selection line connected to many memory cell columns is held at a high potential, there is no risk of erroneous writing to these cells. Thereafter, writing to other memory cell columns can be performed in the same manner.

In the read operation described above, the first column selection lines W1 to WM
are all held at a high potential, so there is no need to hold the memory contents with the capacitance of a bipolar transistor as in the conventional case.

Therefore, it is not necessary to read and write cells at high speed. Moreover, since the read signal obtained from the data line D is the output of the IIL logic gate circuit composed of transistors T6 and T7, clear ゛1゛, ゜゛0゛ signals can be obtained, and therefore a complicated sensing circuit is not required. . In addition, a large number of cells can be formed on the same chip without separation, and cell readout and
The wiring necessary for writing is the first and second column selection lines W, R.
and data line D, and therefore the area occupied by the cell becomes very small. Moreover, if the collector region of the transistor T6 is configured to cross the first and second column selection lines W and R as shown in FIG.
It can also function as a so-called zipper to cross over the second column selection line, eliminating the need for multilayer wiring, simplifying the process, and reducing the occupied area.

A storage device including such a memory cell is formed on the same chip as, for example, another frequency dividing circuit, and is therefore suitable for cases where it is desired to reduce the occupied area (stereo frequency synthesizer, etc.). In addition to being able to read and write in word units, when writing, by shortening the time that the first column selection line W is at a low potential,
It is also possible to write only to a specific cell by giving a signal to the cell. In this case, the storage contents of other unwritten cells in the same column are held by the capacitance of the bipolar transistors forming the cells. In the embodiment described above, a logic gate circuit composed of transistors T6 and T7 is connected to the collectors of the transistor T of the pair of cross-connected transistors Tl and T2, but such a circuit is connected to the collector of the transistor T1. It is also possible to configure the memory contents of the cell to be read out from a data line connected to the circuit.

Furthermore, the transistors T3, T4, and T7 can be replaced with resistors to operate satisfactorily. In the above embodiment, the emitter areas of the transistors Tl and T2 are made unbalanced to enable ゜゜0'' writing, but in addition, the element constants of the transistors T1 to T4 constituting the cell are made unbalanced. From transistor T3 to transistor T
, the same "O" writing can be performed even if the current supplied to the base of transistor T4 is made smaller than the current supplied from transistor T4 to the base of transistor T1.

In order to still ensure 'O'' readout, it is effective to make the current supplied to the base of the transistor T6 larger than the current supplied to the base of the transistor T2.

Furthermore, the same effect can be obtained by increasing the current supplied from the first and second column selection lines W and R to each cell. Note that similar operations can be performed even if the PNP type is replaced with an NPN type, and the NPN type is replaced with a PNP type in each of the transistors in the above-described embodiments. According to the present invention detailed above,
It does not necessarily require a complicated sensing circuit, can operate at low speed, and can read and write in word units.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a cross-sectional view taken along line A-A' in FIG. 2, and FIG. 4 shows how memory cells according to the present invention are wired in a matrix arrangement. FIG.

Claims (1)

[Claims] 1. First and second transistors of a first conductivity type whose emitters are commonly connected and whose bases are connected to the collectors of the other, the collectors of these transistors, and a first column selection line. a pair of load impedances connected between;
a second conductivity type transistor having a collector connected to the base of the first or second transistor, a base connected to the commonly connected emitters of the first and second transistors, and an emitter connected to the data line; a first transistor whose base is connected to the collector of the first or second transistor, whose collector is connected to the data line or another data line, and whose emitter is connected to the common emitter of the first and second transistors; a transistor of one conductivity type, an impedance connected between the collector of the first or second transistor and a second column selection line, and means for setting current rises of the first and second transistors to be unbalanced. A semiconductor memory cell comprising: 2. Claim 1, characterized in that the means for making the current rise unbalanced is to make the element constants of a circuit made up of the first and second transistors and a pair of load impedances unbalanced. Semiconductor memory cell described in section. 3. The semiconductor memory cell according to claim 2, wherein the means for making the current rise unbalanced is to make the base area of the first transistor smaller than the base area of the second transistor. . 4. The load impedance connected to the first column selection line and the impedance connected to the second column selection line are each a transistor of the second conductivity type, as described in claim 1. semiconductor memory cell. 5 A first transistor of the first conductivity type, a transistor of the second conductivity type connected to its base, a second transistor of the first conductivity type, and a transistor of the second conductivity type connected to its base each have IIL logic. A transistor of a first conductivity type whose base is connected to the collector of the first or second transistor of the first conductivity type and a second conductivity type transistor whose emitter is connected to the second column selection line, constituting a gate circuit. 5. The semiconductor memory cell according to claim 4, wherein the transistor constitutes an IIL logic gate circuit. 6. Claim 5, wherein the first or second transistor of the first conductivity type has at least two collector regions, and each second conductivity type transistor is connected to each collector region. The semiconductor memory cell described in .