JPS5943011B2 - Preset tuner - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a preset tuner, and more particularly to a preset tuner equipped with a memory for digitally storing information corresponding to a broadcast station.

A preset tuner is known that presets a plurality of stations and selects and receives one of the preset stations by pressing a selection button.

Usually, such preset tuners are mechanically operated, which has many disadvantages in terms of lifespan and external dimensions.

The present invention provides a memory for digitally storing information corresponding to a broadcast station, a memory set button for setting the memory to a writing standby state, and an address designation selection button for designating a predetermined address of the memory. The present invention aims to provide a preset tuner in which the entire tuner does not respond to tuning operations during the period from the suppression wave of the memory set button to the suppression of the selection button. It is effective.

Embodiments will be described below with reference to the drawings.

In FIG. 1, 1 is a memory for storing information corresponding to a preset station, 3 is a plurality of selection button groups, and 3 is a selection button 2a, 2b, 2b, 3, and 3 for each of the selection button groups.
Light emitting diodes 3a, 3b, corresponding to...
4 is an address selector that responds to the operation of the selection button group 2, and 2 is a control that supplies control signals to the memory 1 and the address selector 4. 1 is a display buffer that generates an open signal to the preset indicator L; L is an up/down counter; 10 is a memory set button, 11 is a manual automatic changeover switch, and 12 is a comparison circuit for comparing the DC output voltage of the DA converter and the DC output voltage obtained from the DC voltage generator 13. It is.

The following operation will be explained.

First, in the case of manual preset, manual automatic changeover switch 1
1 manually.

Then, the inside of the control unit enters a manual tuning state, and manual tuning operations can be performed by operating the DC voltage generator 13.

Manual tuning operation [Here, a comparison circuit 12 is used, which compares the output DC voltage A of the DC voltage generator 13 and the output DC voltage B of the DA converter, and calculates the difference voltage (A-
B) generates a signal and applies it to control section i.

Now, if the differential voltage (A-B) is positive, the up/down counter L (in response, an up command U is issued together with the clock signal CL, and the up/down counter I starts counting up). I do.

Therefore, the value of the digital signal sent from the up/down counter I to the DA converter 1 via the buffer 1 becomes a dog, and therefore the DC voltage B that is the output of the DA converter 1 also becomes a dog, and the difference voltage (A, -B) approaches the output DC voltage A of the DC voltage generator 13 to zero.

When the amplifier counting continues and the output DC voltage B of the DA converter l becomes equal to the output DC voltage A of the DC voltage generator 13, the output signal of the comparator 12 becomes zero, and the controller outputs up. Stop instruction U.

These operations are performed instantaneously.

If the differential voltage (A-B) is negative, the antibacterial control unit issues a down command to the up/down counter I, and the up/down counter I performs down counting.

When the differential voltage (A-B) becomes zero, the down command from the side part stops.

Reception at a desired station is performed using the principle described above.

The DC voltage generator 12 corresponds to the tuning knob of a normal radio receiver, and by operating the DC voltage generator 13, it is possible to receive a desired station.

When you operate the DC voltage generator 13 while observing the tuning indicator or listening to the sound from the speaker, the output DC voltage B of the DA converter instantly changes to the output DC voltage A of the DC voltage generator 13. Follow.

The output DC voltage B of the DA converter 1 is applied to the comparator 12 (since it is applied from the output terminal 14 to a varicap diode (not shown) which is a tuning element of the nayuna, the DC voltage B is The generator 13ζ can thus perform six synchronized operations.

When the desired station is received, press the memory set button 10.
Press.

The memory set button 10 is connected to the control unit 5,
When the memory set button 10 is pressed, an address designation standby command SE is issued from the sterilization section to the address selector.

When the address specification standby command SE is issued, the DC voltage generator 13 is operated (Nayuna does not respond to this,
This is a feature of the present invention.

That is, when the memory set button 10 is pressed, the state of the control is changed, and the control section 5 no longer operates in response to the output signal of the comparison circuit 12.

This may be done by providing an input prohibition circuit on the signal path from the comparator circuit 12 to the control section 5I and setting the input prohibition circuit to the prohibition state, or by using an up-down command (U) applied from the control section j to the up-down counter. /D) Alternatively, a circuit for prohibiting the generation of the clock signal CL may be provided in the control section 5.

The desired station is preset by pressing one button of the selection button group 2, for example, the first selection button 2a, in the above-mentioned state.

When the first selection button 2a is pressed, the first selection button 2a is pressed.
A first address corresponding to a is stored in the address selector 4, and this first address is supplied to the memory I as an address signal, and an addressing completion signal AS is applied from the address selector A to both controllers. .

When the address selector A issues an address designation completion signal As to the sterilization section 1, a write command W is issued from the control section 1 to the memory 1.

Then, memory 1 specified by address selector 4
The information stored in the up/down counter L is stored in the first address of the up/down counter L.

The first selection button 2a also applies to the second selection button 2b and below.
The same operations as above are performed to complete the presetting.

In parallel with the presetting of the desired station, the progress of the presetting operation is displayed on the display device.

That is, when a desired station is received and the memory set button 10 is pressed, the control section 5 issues a signal to the display buffer indicating that the memory is set.

The signal notifying the memory set state is a set signal A.
It consists of ON and display signal DISP.

The set signal AON is a signal as shown in FIG. 2A,
The state of "1" is maintained after the memory set button 10 is pressed until the selection button 2 is pressed.

The display signal DISP is a signal as shown at the beginning of FIG. 2, and is a rectangular wave with a predetermined period.

Thus, the display buffer has a circuit configuration as shown in FIG.

In FIG. 3, 15a, isb, 15c, 15d and 15e are input terminals 16a-16b and 16c.

A signal from the address selector 4 is applied to 16b and 16e, respectively, and the other input terminal 1γa.

17b, 1γc, 1γd and 1γe (this set signal AO
First to fifth OR circuits, 18a, in which N is a rigid force of 1;

18b, 18c, 18d and 18e are one input terminal 1
The first to fifth OR circuits 15a are respectively 9a, 19b, 19c, 19d and 19e.

15b, 15c The output signals of 15d and 15e are applied to the other input terminals 20a, 20b, 20c.

The first one to which the display signal DISP is applied to 20d and 20e.
to fifth AND circuits; 21a is a first light emitting diode that lights up in response to the press of the first selection button 2a of the selection button group; 21b, 21c, 21d and 21e are second, third, fourth and fourth AND circuits; 5 selection buttons (there are corresponding second to fifth light emitting diodes).

When the memory set button 10 is pressed and a set signal AON and a display signal DISP are issued from the control section 5, the set signal AON is transmitted to the first to fifth OR circuits 15a to 1.
5e is applied to the other terminals 17a to 17e.

At that time, no signal from the address selector 4 is applied to one terminal 16a to 16e of the first to fifth OR circuits 15a to 15e.

When the set signal AON is applied, the first to fifth O
The output signals of the R circuits 15a to 15e become "1".

On the other hand, when the memory set button 10 is pressed, the other input terminals 2 of the first to fifth AND circuits 18a to 18e are
A display signal DISP is applied to 0a to 20e.

Since the display signal DISP is a rectangular wave signal as shown in FIG. 2, the outputs of the first to fifth AND circuits 18a to 18e are as shown in FIG. 21e, the first to fifth light emitting diodes 21a to 21e blink to indicate the memory set state.

The display of the memory set state of the preset display appliance continues until one of the selection buttons in the selection button group is pressed.

As mentioned above, for example, when the first selection button 2a is pressed, the address selection completion signal A is sent from the address selector 4.
S power 1] instantaneous part 5 (this is applied.

The address selector 4 issues an address designation completion signal As to the sterilization unit, and at the same time issues a write position display signal WS to the display buffer unit.

Now, it is assumed that the first selection button 2a is pressed with a force), and the write position display signal WS is applied to only one terminal 16a of the first OR circuit 15a.

Therefore, only the output signal of the first OR circuit 15a is generated and applied to one input terminal 19a of the LAND circuit 18a.

When the addressing completion signal As is applied, the control unit 5 stops the set signal AON and changes the display signal DISP from a rectangular wave state to a "1" state.

Therefore, only the output signal of the first AND circuit 18a is generated, and the outputs of the second to fifth AND circuits 18b to 18e are "
0".

The first light emitting diode 21a continues to light up due to the output signal Q of the first AND circuit 18a.

The write position display signal WS or the display signal DISP is set on a timer (therefore, is set) so that the write position display signal WS or the display signal DISP becomes "0" after a certain period of time has elapsed after the address specification completion signal As is generated.

Therefore, the first light emitting diode 21a is turned off when a predetermined time T has elapsed after the address selection button 2a is pressed, as shown in FIG. 2C.

As the preset operation progresses, the preset stations are sequentially displayed in a similar manner.

Thus, the presetting operation is completed when all addresses are preset or a desired number of stations are preset.

To roughly describe the display method, when the memory set button 10 is pressed, all the display light emitting diodes flash to indicate the memory set state, and in that state, one of the selection button group 2 is pressed. When you press , all the other light emitting diodes except the one corresponding to the pressed selection button go out and display the selected address, and after a predetermined period of time, the light emitting diode corresponding to the selected selection button is pressed. This means that three displays can be made: the light emitting diode that is displayed is also turned off to indicate that the next preset is possible.

Next, automatic presetting will be explained.

The automatic channel selection operation is performed by switching the manual automatic changeover switch to automatic and operating the search switch 22.

When the search switch 22 is operated, the control unit issues an up/down counter rrt, for example, an up command U.

Therefore, the up/down counter J performs up counting,
The output digital signal of the up/down counter L is applied to the DA converter via a buffer.

The digital signal is converted into a DC signal by the DA converter and applied from the output terminal 14 to a variable capacitance element (not shown) of the Nayuna.

When a DC signal is applied, the capacitance of the variable capacitance element changes, thereby changing the tuning frequency.

Then, a certain station is received and the tuner's intermediate frequency stage (
When a normal intermediate frequency signal is generated at the terminal 23 (not shown), the intermediate frequency signal is transmitted from the terminal 23 to the sterilization unit 5 via the buffer 24.
is applied as a stop signal STP.

The stop signal STP stops the generation of the clock signal CL applied from the sterilization section 5 to the up/down counter I, so that the up/down counter L stops counting up.

The stop signal STP is set to a timer (not shown) so that it automatically disappears after a predetermined period of time (for example, 2 seconds) has elapsed.
bacteriostatic.

Therefore, after a predetermined period of time has elapsed, the clock signal CL is generated again from the controller, and the up-down force counter J starts counting up again.

Therefore, a stepped DC voltage as shown in FIG. 4 is generated at the output terminal 14.

In FIG. 4, the horizontal part shows the signal reception state, and the subject part shows the search state.

Now, in the reception state at time t1, when the memory set button 10 is pressed for presetting, the up/down counter I stops counting up and is fixed.

That is, time t. The period from t2 to t2 is the reception state of a certain station, and the up-down counter I has stopped counting up, but if the memory set button 10 is not pressed, the next search state will be entered after a predetermined period of time has elapsed. Put it away.

However, when the memory set button 10 is pressed, the up/down counter I continues to stop in the state corresponding to the certain station, as shown by the dashed line in FIG. 4, and does not shift to the next search state. The preset standby state is maintained.

The operation after Nayuna enters the preset standby state is the same as in the case of manual preset, and the explanation thereof will be omitted.

Therefore, one of the selection buttons λ (for example, selection button 2)
When a) is pressed, the up/down counter I is released from being fixed by the memory set button 10, and the up/down counter I receives the up command U from the control circuit 5 again and starts counting up.

Even when a down command is issued to the up/down counter I from the control unit 5, the same presetting as when the above-mentioned up command U is issued can be performed.

Then, when all or an arbitrary number of selection buttons in the selection button group 2 are preset, the preset writing operation is completed.

FIG. 5 is a circuit diagram showing an example of a specific circuit of the lock control section 5 of FIG. 1, and 25 and 26 are set priority R879717071.
circuit (hereinafter abbreviated as set F-FJ), 2γ and 2
8 is an RS flip-flop circuit (hereinafter referred to as R8F-FJ), 29 and 30 are monostable multivibrators, 31 is an OR circuit, 32 and 33 are AND circuits, 34 and 35 are inverters, 36 is an oscillation circuit, Said set F
-F25 and 26 and R8F-F27 and 28 have truth values shown in Table 1 (a) and (b).

Therefore, at the S input terminal of the first set 1-F-F25,
An up search signal SR from the search switch 22 is applied, and a down command signal SL from the search switch 22 is applied to the S input terminal of the second set I-F-F 26.

Also, the stop signal STP is input to the input terminal of the first monostable multivibrator 29, the memory signal MRY is input to the S input terminal of the first R8F-F27, and the R input terminal of the second R8F-F1a is input to the stop signal STP.
An addressing completion signal AS from the address selector A is applied to each input terminal.

Then, an up or down command signal (U/D) is applied to the Q output terminal of the first set F-F25, a clock signal CL is applied to the output terminal of the first AND circuit 32, and a clock signal CL is applied to the Q output terminal of the first set F-F25.
Address specification standby command signal SE is applied to the Q output terminal of 1a.
The second monostable multivibrator 30 is configured so that a write command signal W can be obtained from each output terminal.

Now, when trying to perform automatic presetting, the first set) F
- When the up search signal SR is applied to F25, the first
A signal of "1" is generated at the Q output terminal of the set 1-F-F25, which becomes an up command.

At that time, the stop signal STP, memory signal MRY, and address specification completion signal As are all "0", so the output signal of the first monostable multivibrator 29 is "0".
1'', the Q output signal of the first R8F-F2γ becomes ``0'', and all three input signals of the second AND circuit 33 become ``l'', so the output signal of the second AND circuit 33 becomes ``l''.

Since the output signal of the second AND circuit 33 and the output signal from the oscillator 36 are applied to the first AND circuit 32, the output terminal of the first AND circuit 32 receives a clock signal CL corresponding to the oscillation frequency of the oscillator 36. is obtained.

In the up search state, when a certain station is received, the stop signal STP is transmitted to the first monostable Maruna vibrator 29.
I is applied.

Therefore, the output signal of the first monostable multivibrator 29 changes from "1" to "0", and remains at "0" for a period determined by the time constant of the first monostable multivibrator 29,
After that, it is reversed to "1" again.

The output signal of the first monostable multivibrator 29 is "
During the period when the second AND circuit 33 is "0", the output signal of the second AND circuit 33 is "0", so the generation of the clock signal CL is stopped and the up-counting is also stopped.

When the output signal of the first monostable Maruna vibrator 29 becomes "L" again, the output signal of the second AND circuit 33 also becomes "L", the clock signal CL is generated again, and up counting is restarted.

Regarding down search, the circuit of FIG. 5 operates in a similar manner.

That is, in the down search state, the second set F-
A down search signal SL is applied to the S input terminal of F26, and a signal "1" is generated at the Q output terminal of the second set F-F26.

Therefore, the output signal of the OR circuit 31 becomes "1" as in the up-search, and the other circuits operate in exactly the same manner as in the up-search, so that the same operation as in the up-search is achieved.

When a certain station is currently being received in the up search state,
When the memory signal MRY is applied, the first R8F-F27
The Q output signal of becomes "l", and the input signal of the second AND circuit 33 becomes "0".

Therefore, the clock signal CL, which is the output signal of the first AND circuit 32, is no longer generated, and up-counting is stopped.

At the same time, the memory signals M and RY are supplied to the second R8F/F1.
a, and the Q output signal of the second R8F-F1a is
1".

This is applied to the address selector 4 of FIG. 1 as the address designation standby command signal SE.

After the address designation standby command signal SE is applied, when any one of the selection buttons 2 shown in FIG. 1 is applied, the address selector A sends an address designation completion signal AS to the controller. The completion signal AS is applied to the R input terminal of the second R8F-F28, and the completion signal AS is applied to the R input terminal of the second R8F-F28.
Reset F-F28.

Therefore, the addressing standby command signal SE is no longer generated.

The completion signal AS is further applied to the second monostable multivibrator 301 to generate a write command signal W at the output terminal of the second monostable Maruna vibrator 30.

The second monostable Maruna vibrator 30 operates at the falling edge of the completion signal AS, and keeps the output signal "L" for a predetermined period.
This is used as the write command signal W.

Also, the write command signal W is applied to the R terminal of the first R8F-F2γ to reset the first R8F-F2γ.

Therefore, the output signal of the first R8F/F2γ becomes "0", and all the input signals of the second AND circuit 33 become "1" again, so that the clock signal CL is generated.

As described above, the memory signal MRY is applied to the second AND circuit 33 with the highest priority.

Therefore, as soon as the memory signal MRY is generated, the generation of the clock signal CL is stopped, and up counting is no longer performed.

This is the same in the case of down counting, and also in the manual presetting.

Since this state persists unless any one of the selection buttons is pressed, reception of the desired station can be ensured, and missing of the desired station due to malfunction Q is completely prevented.

As described above, the preset tuner according to the present invention has
By providing a special memory set button and giving priority to the memory signal generated by pressing the memory set button over all other signals, it is possible to completely prevent erroneous operation when selecting a channel, and to ensure that the desired channel is not selected. This is an excellent system that allows reliable channel selection, and is particularly effective when applied to a preset tuner having an automatic preset mechanism.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a preset tuner according to the present invention, FIG. 2 is a characteristic diagram for explaining the present invention, and FIG. 3 is a diagram of a display device of a preset tuner according to the present invention. FIG. 4 is a characteristic diagram for explaining automatic tuning, and FIG. 5 is a circuit diagram showing a specific example of the antibacterial section shown in FIG. 1. Explanation of main figure numbers, 1...Memory, 2...
・Selection button group, A...address selector, 5.
...Institutions Department, I...Up-down counter, 10...Memory set button.

Claims (1)

[Claims] 1. In a preset tuner configured to preset a plurality of stations and to select and receive one of the preset stations by operating a tuning member, the preset device is set to a write standby state by operating a memory setting member. , so that information is written to the preset device by operating the channel selection member, and the automatic tuning mechanism or manual tuning member is operated during the period from the operation of the memory set member to the operation of the channel selection member. A preset tuner characterized in that the preset device is configured such that the preset device is not activated by an operation.