JPS5943526A - Manufacture of resin sealed type electronic part - Google Patents
Manufacture of resin sealed type electronic partInfo
- Publication number
- JPS5943526A JPS5943526A JP57154106A JP15410682A JPS5943526A JP S5943526 A JPS5943526 A JP S5943526A JP 57154106 A JP57154106 A JP 57154106A JP 15410682 A JP15410682 A JP 15410682A JP S5943526 A JPS5943526 A JP S5943526A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- die
- lead frame
- sealed
- type electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は電子機器、電気機器等に用いられる樹脂封止型
電子部品の!!!!造方法に関するもので、その目的と
するところは生爪多品種生産、連続生産を可能ならしめ
且つ不良発生率を低下せしめることKある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to resin-sealed electronic components used in electronic equipment, electrical equipment, etc. ! ! ! This relates to a manufacturing method, and its purpose is to enable the production of a wide variety of raw nails, continuous production, and to reduce the rate of defects.
従来の樹脂封止バlJ電子部品の製造方法は第1図に示
すようにリードフレームlに素子2をダイボンディング
してからインナーボンティング8し次にバンシベーショ
ン4してカラトランスファー成1囮1.で素子を樹脂5
で封屯して樹脂封止型電子部品を得るもので、大量少品
種生ρ4、バッチ生産に好適であるが少1牧多品種生産
、連続生産に不向きで且つ不良発生率も6〜7%と高い
ものであった。The conventional manufacturing method for resin-sealed electronic parts is as shown in FIG. .. The element is made of resin 5
It is suitable for high-volume, small-variety production, ρ4, batch production, but is unsuitable for small-scale, high-mix production, continuous production, and has a defect rate of 6 to 7%. It was very expensive.
本発明t」上記欠点を解決するもので、リードフレーム
の士「面金成形材料で挾み複合タブレットに一体化して
から成形後、該成形品に素子をダイインナーボンディン
グしてから素子2 ボンディングで封1にするため少量
多品種生産、連続生産をMl能ならしめ且つ不良発生率
を1〜2%に低下させることができだものである。The present invention solves the above-mentioned drawbacks.The lead frame is sandwiched with a metal molding material and integrated into a composite tablet, and after molding, the element is die-inner bonded to the molded product, and then the element 2 is bonded. In order to reduce the number of seals, it is possible to make small-lot, high-mix production and continuous production more efficient, and to reduce the defect rate to 1 to 2%.
以下本発明の一実施例を第2図のIW+而にまり貯〜明
する。1 )」金属製リードプレー1・で、リーじフV
−ム1の上F 而’s) 7エフール樹11if、エポ
キシ樹脂、不飽和ボリエヌデル樹脂、ジアリルフタレー
トζ91脂、シリコン樹脂、・′ラミンj+・・1脂、
ポリアミド、ポリイミド、ボリフ゛タジ]ニン、ポリス
ルフォン、ボリウレクン等の単独又Qj混合物又t」y
;4性物からなる成形材料で挾み複合タブレアトロ(で
一体化してから圧縮成形等で成形後、J々+:′i、形
品7に素子2f6:ダイインナーボンディング8してか
ら素子2全フ丁ノール樹脂、エボギシ樹脂、イ< +j
i・(「[Jポリlステル11!Il 脂、ジアリルフ
タレ−1−+ηl 脂、シリフン(6寸1i旨、53ミ
リアミド、ポリイミド、−1!すブタジェン、ポリスル
フォン、ポリウレタン等の中独又は91.41物又は研
・l’l□ ’h+からなる注形材でボッティング9で
封1トして(I71脂封+、lx型1F、子部品を得る
ものである。なりぶ了、q゛イインリーボンデイングり
−l−′7レーム表面に!戊形材判や注形材との接着f
1を・向上させるだめの−II処理、]−ティング処+
IJ1等(7)活性化処理音節し2−C棧くこともでき
るものであン)、以ト1?h!明したように本発明の+
、:1+脂封1に型7(f、子部品の製造方法によれば
少FfL多品挿生産、連続生戸C全実現することができ
且つリードフレームの変形が全くないため不良発生率を
従来方?Jξより5%低[さすることができたものであ
る。An embodiment of the present invention will be explained below based on IW+ in FIG. 1)"Metal lead play 1, leaf V
7 Efur resin 11if, epoxy resin, unsaturated Boriendel resin, diallyl phthalate ζ91 resin, silicone resin, Lamin j+...1 resin,
Single or mixture of polyamide, polyimide, polyvinyl, polysulfone, polyurecne, etc.
; Sandwiched with a molding material consisting of four properties, integrated with a composite table atro (and then molded by compression molding etc.), J+:'i, molded product 7, element 2f6: die inner bonding 8, then element 2 Futonol resin, Ebogishi resin, i < +j
i. Seal with botting 9 using a casting material consisting of 41 parts or 1'l□'h+ (I71 fat seal +, lx type 1F, to obtain the child parts. Iinri Bonding - l-'7 On the surface of the frame! Adhesion with molded materials and cast materials f
-II processing to improve 1, ]-ting processing +
IJ1, etc. (7) Activation processing syllables can also be used as 2-C. h! As explained above, the +
,: 1 + Grease seal 1 to mold 7 (f) According to the manufacturing method of the sub-components, it is possible to achieve low FfL multi-item insertion production, continuous raw door C, and there is no deformation of the lead frame, so the defect rate is reduced. 5% lower than the conventional method?Jξ.
牟jliン1に従来の1.’、’1指封(ト型重了部品
の1Lfu I!!i方法の簡略T1(−図、:’n
21図+1本発明による+Yf1脂封+ト’!1シ゛取
子部品の叫++’j ]J法の簡略工程図である。
■(・Jリードフレーム、2は素子、8はインナーボン
ディング、41・Jバ、シベー・・4ン、 51:1
j’pJ II?(,6は複合メブレ、ト、7 kJ、
Ij’j ’lジ品、8 ifダイインナーボンディ
ング、9 ):j +1r 、、フ゛イングである。
特W「出願人
松ト11.工(′1式会社
代用1人)「却下 竹 元 倣 九
(に1か2名)
ェ)”t 1 j、J
第2rり1
1
7
/The conventional 1. ',' 1 finger seal (1Lfu I!!i method of 1 finger seal (-Fig., :'n
Figure 21+1+Yf1 fat sealing +to' according to the present invention! This is a simplified process diagram of the J method for 1-shield lever parts. ■(・J lead frame, 2 is element, 8 is inner bonding, 41・J bar, side...4, 51:1
j'pJ II? (, 6 is a composite mesh, 7 kJ,
Ij'j'lji product, 8 if die inner bonding, 9): j +1r, . Special W "Applicant Matsuto 11. Eng ('1 type company substitute 1 person) "Rejected Takemoto imitation 9 (1 or 2 people) e)"t 1 j, J 2nd rri 1 1 7 /
Claims (1)
合タブレットに一体化してから成形後、該成形品に素子
をダイインナーボンディングしてから素子をボッティン
グで封止することを特徴とする樹脂封止型電子部品のm
進方法。(1) A resin characterized in that the upper and lower surfaces of a lead frame are sandwiched between molding materials and integrated into a composite tablet, and after molding, an element is die-inner bonded to the molded product, and then the element is sealed by botting. m of sealed electronic components
How to proceed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57154106A JPS5943526A (en) | 1982-09-03 | 1982-09-03 | Manufacture of resin sealed type electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57154106A JPS5943526A (en) | 1982-09-03 | 1982-09-03 | Manufacture of resin sealed type electronic part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5943526A true JPS5943526A (en) | 1984-03-10 |
Family
ID=15577049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57154106A Pending JPS5943526A (en) | 1982-09-03 | 1982-09-03 | Manufacture of resin sealed type electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5943526A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6464254A (en) * | 1987-09-03 | 1989-03-10 | Toshiba Corp | Solid-state image sensor and manufacture thereof |
| JPH09213826A (en) * | 1996-02-01 | 1997-08-15 | Nec Corp | package |
-
1982
- 1982-09-03 JP JP57154106A patent/JPS5943526A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6464254A (en) * | 1987-09-03 | 1989-03-10 | Toshiba Corp | Solid-state image sensor and manufacture thereof |
| JPH09213826A (en) * | 1996-02-01 | 1997-08-15 | Nec Corp | package |
| US5905301A (en) * | 1996-02-01 | 1999-05-18 | Nec Corporation | Mold package for sealing a chip |
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