JPS5943780B2 - Data transfer signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for generating a data transfer signal applied to a latch that stores the contents of a counter circuit.

An object of the present invention is to prevent malfunction of the latch circuit by synchronizing the data transfer signal entering the latch circuit with the input pulse of the counter, and to prevent chatter of the data transfer signal.

In a counter circuit as shown in Figure 1, counter 1
It is assumed that the content of is stored in Latchy 2.

Thereafter, the flip-flop circuit that constitutes counter 1 advances at the falling edge of the input clock pulse, and the latch circuit is composed of a half-bit D type flip-flop, and the clock (CL
) terminal is at H level, the signal applied to the D terminal passes through as is, and the output Q becomes Q=D. When it is at L level, it is held and the D level is just before the CL terminal changes from H to L.
Suppose we want to store the state of and output it to Q. In the conventional counter circuit shown in Fig. 1, the data transfer signal applied to the latch circuit is not synchronized with the counting pulse entering the counter, so as shown in Fig. 2, the falling edge of the pulse to be counted and the falling edge of the data transfer signal Malfunctions may occur if the downlinks coincide in time. In other words, if the pulse to be counted and the data transfer signal are input at the same time when the flip-flops in the counter are inverted in several stages (timing at which a carry occurs), even if the flip-flops in the lower digit are inverted, HOLD may become stuck when the upper digit flip-flop is not inverted. This causes a value that is completely different from the value counted by the counter to be held, which has a serious adverse effect on the operation of the system. In conventional counter circuits, in order to prevent this malfunction, a synchronous counter is used for the counter, or a gate circuit 13 is provided in front of the counter as shown in Figure 3 to prevent the pulse to be counted from entering when the data transfer signal is input. He used methods such as: The former method requires a complicated counter. The latter also has the disadvantage that pulses to be counted cannot be input to the counter successively. Furthermore, in both cases, if the data transfer signal contains noise such as chatter, it cannot be removed. The present invention is a data transfer signal generation circuit designed to eliminate such drawbacks, and FIG. 4 shows its connection diagram, and FIG. 5 shows its time chart. The data transfer signal generation circuit according to the present invention is a three-stage half-bit flip-flop circuit.
FI-4, FF2-5, FF3-6, NOT circuit-7, and AND circuit-8 are used.

A half-bit flip-flop is usually called a latch.
When the clock terminal CL is logic 1, the same signal as the data input terminal D appears on the output Q, and when the clock terminal CL is logic 0, the output Q shows the input terminal that is about to change the logic of the clock terminal CL from 1 to O. A flip-flop that has the property of holding and outputting the state D. Flip-flop is the fourth
As shown in the figure, three stages are connected in cascade, and a pulse having the same phase as the pulse to be counted is applied to the staged and subsequent stages FF1 and FF3, and a pulse having an opposite phase to the middle stage FF2 is applied as a clock. When connected in this manner and a data transfer signal is applied to the D terminal of FF1, this signal is transferred to the Q terminal of FF3 with a delay of half a clock cycle as shown in FIG. Here, 1 in FIG. 5 is the clock waveform in FIG. 4, and 2 is the D of FF1-4.
Terminal input waveform (data transfer input signal, below 3,
4 and 5 represent output terminals Q1, Q2, and Q3 of FF14, FF2-5, and FF3-6, respectively. By negating the Q terminal output of FF2 and ANDing the Q terminal output of FF3, a signal is obtained in which the rising edge and the falling edge of the pulse to be counted coincide, as shown in FIG. 5. When this signal is input as a data transfer signal to the data transfer signal input terminal DT of the latch circuit 9 that latches the data of the counter 10, the falling edge of the data transfer signal and the falling edge of the pulse to be counted will no longer coincide. It is possible to eliminate the drawbacks of the conventional method. In this circuit, there is a delay of one pulse to be counted before the data transfer signal is applied to the latch circuit, so the number of pulses to be counted increases by one. This drawback can be eliminated by inputting the logical sum of the pulses to be counted FF2 to the input of the counter. As described above, when this circuit is used as a data transfer signal generating circuit, malfunction of the latch circuit can be prevented.

Another advantage of this circuit is that even if a thin pulse such as a chatter signal is input as a trigger for the data transfer signal, the data transfer signal will not enter the latch. In particular, this chatter is likely to occur when the counter is inverted, that is, at the falling edge of the pulse to be counted, but at this point, FF1 does not transmit data to a1, so it may be triggered by noise generated due to power line impedance, etc. There is no. The data transfer signal generating circuit according to the present invention is resistant to noise and does not cause malfunctions in the latch circuit.

The above example uses a counter whose clock advances and a latch that holds the clock in the L state, but Q2 and Q3 can also be used as data transfer signals in other cases.
Instead of taking the following, a circuit that operates in the same way can be constructed by taking the logical sum or logical product of any two of Q2, Q2, Q3, and Q3.

[Brief explanation of the drawing]

1 and 3 are diagrams showing a conventional counter circuit and a data transfer signal generation circuit. In FIG. 2, a time chart 1 is a pulse to be counted and 2 is a data transfer signal in a case where there is a risk of malfunction of a conventional counter circuit. FIG. 4 is a diagram showing a data transfer signal generation circuit according to the present invention. Figure 5 is the time chart, (1) φ, (2) D, (3) Q1
, (4) Q2, (5) Q3, (6) AND output waveforms. 1... Counter circuit, 2... Latch circuit, 3... Gate circuit, 4, 5, 6...
...Half-bit flip-flop circuit, 7...
・Negation circuit, 8...Logic product circuit, 9...
・Latch, 10...Counter.

Claims (1)

[Claims] 1. In a counter mechanism consisting of a counter that counts input pulses, a latch circuit that stores the contents of the counter, and a data transfer signal generation circuit that supplies the latch circuit, three D-type half-bit flip-flop circuits are used.
The stages are connected in cascade, and clocks φ, @φ@, and φ synchronized with the pulses to be counted are applied to the first, middle, and second stages as clocks for the three flip-flop circuits, respectively, and the input terminals of the flip-flops in the latter stage are negated and output. A data transfer signal generation circuit characterized in that a logical product of terminals Q is used as a data transfer signal.