JPS5943782B2 - Maximum value detection circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a maximum value detection circuit device that detects maximum level data from a plurality of digital data groups.

Conventionally, in microcomputers that have only one interrupt level, an interrupt generation circuit is provided externally so that multiple interrupts can be executed.

When multiple interrupts occur at the same time, this interrupt generation circuit determines priorities according to their importance and processes the interrupts in order of priority so as not to interfere with the operation of the microcomputer. Generally, a priority encoder is used to determine the interrupt priority order, and a plurality of interrupt request terminals are provided, and interrupts are prioritized by selecting a higher interrupt request terminal. However, since such interrupt requests are uniquely connected to each terminal, they may be used, for example, to detect a momentary power outage and save the data being processed to memory to prevent the program from being destroyed. It is suitable for cases where the priority is determined absolutely, but it is suitable for cases where you want to interrupt a certain data value of a signal whose data value changes every moment, or when you want to interrupt multiple terminals arbitrarily. A maximum value detection circuit device that can detect the maximum value of a plurality of data in a short time when a selection is desired has been desired.

The present invention has been proposed in view of the above problems, and provides a maximum value detection circuit device that can detect maximum level data from a plurality of data groups. The present invention will be explained below with reference to the drawings.

FIG. 1 shows a basic circuit of a maximum value detection circuit device, and FIG. 2 shows a plurality of basic circuits shown in FIG. 1 connected in parallel to set a plurality of inputs.

In the figure, A is the basic circuit of the maximum value detection circuit device, and U
1 to U4 are exclusive OR circuits (EX-OR), U
5 is a latch circuit that latches 4 bits of data by setting terminal E to O level, U6 to U9 are open collector NAND circuits, U10 to U13 are exclusive NOR circuits (EX-NOR), and U, 4 to Ul7 are In the open collector AND circuit, Ul8 is an R-S flip-flop, and RO is the load resistance of the AND circuits Ul4 to U,7. One input of EX-0RU1 to U4 is connected to data input terminals E8, E4, E2, and El, respectively, and the other end is connected to maximum/minimum selection terminal H/L, respectively. Then, each output of EX-0RU1 to U4 is connected to a latch circuit U.
5 inputs 14, 13, 12, 11, and each output 04
, 03, 02, and 01, respectively.
This is connected to one input of NAND circuits U6 to U9 and EX-
It is connected to one input of NORU and O-Ul3. Furthermore, the latch terminal E of the latch circuit U is connected to the terminal LATCH. Then, NANDU6 to U9 are connected to data output terminals D8, D4, D2, and Dl, respectively, and also connected to other inputs of EX-NORUIO-Ul3. The outputs of EX-NORUIO-Ul3 are connected to the inputs of AND circuits Ul4 to Ul7, respectively, and the respective outputs are connected in common to the set input S of an R-S flip-flop Ul8, and further connected to a resistor R. Connected to power via. Then, the Q output of flip-flop Ul8 is NANDed.
The output terminal D is connected to the other inputs of the circuits U6 to U, respectively, and detects the Q output. and connect the reset input R to terminal RE.
Connected to SET. Also, AND circuit U, 4 to U, 7
The other inputs of are connected to terminals S8, S4, S2, and Sl, respectively. And each data output terminal D corresponding to a plurality of basic circuits A, for example, three basic circuits Al, A2, and A3.
8, D4, D2, Dl and terminals S8, S4, S2, Sl
are connected to each other, and the terminal RESET and terminal H/L are commonly connected. A single search pulse is sequentially applied to terminals S8, S4, S2, and Sl. Rl, R2, R4, R
8 indicates the load resistance of the NAND circuits U6 to U. The operation will be explained below. Keep terminal H/L at 1 level and terminal RE
Apply a set pulse to SET to set the initial state. And suppose that each basic circuit Al, A2, A3 has 2
Input data in decimal format (1001) (1010) (010
0) is applied, EX-0RU1 to U4
Since one input is at level 1, each EX-0RU1~
The same data as the input data appears at the output of U4, and by applying a latch signal to the terminal LATCH, the latch circuit U5 of each basic circuit Al, A2, A has (1001)
(1010) (0100) are stored. Since the output of the latch circuit U5 is that flip-flops U and 8 are in the set state, the Q output becomes 1 level, the NAND circuits U6 to U9 become active, the output level of the latch circuit U5 is inverted, and each basic circuit Al, The levels of data output terminals D8, D4, D2, and Dl of A2 and A3 are respectively (0
110), (0101), (1011). This signal forms a wired AND circuit because each output of the open collector NAND circuit is commonly connected, and when the level of each data output terminal of the three basic circuits Al, A2, and A3 is all other than 1, it is O level. becomes. Therefore, the level of the common connection line of each data output terminal D8, D4, D2, Dl becomes (0, 0, 0, 0). This level is also EX
-NORU, O-Ul3, but if we focus on EX-NORUlO corresponding to the most significant bit, the input levels of each EX-NORUlO of each basic circuit Al, A2, A3 are (1, 0), ( 1,0), (0,0), the respective output levels are 0,0,1. Therefore, when only EX-NORUIO of basic circuit A3 generates an output and a search pulse is applied to terminal S8, AND
A level 1 output is generated at the output of circuit Ul4, inverting flip-flops U and 8 and setting the Q output to O level. Then, the NAND circuits U6 to U become inactive, and the levels of the data output terminals all become 1. At this point, the levels of the data output terminals of each basic circuit Al, A2, and A3 are (0, 1, 1, 0) (0, 1, 0, 1) (1, 1,
1, 1), and the level of the common connection line is wired AN.
D gives (0, 1, 0, 0). This level is simultaneously applied to EX-NORUlO-Ul3, but EX
- Focusing on NORUll, each basic circuit Al, A2, A
The input level of each EX-NORUll of 3 is (0
,1)(0,1)(1,1), and each output level is 0
, 0, 1, but even if a search pulse is applied to terminal S4, flip-flop Ul8 of basic circuit A3 has already been inverted, so there is no change in state, and the level of the common connection line becomes (0).
, 1, 0, 0). And then EX-NOR
Focusing on Ul2, the input level of each EX-NORUl2 is (0,0) (0,1) (0,0),
Since each output level is 1, 0, 1, when a search pulse is applied to the terminal S2, the output level of the AND circuit Ul6 of the basic circuit A1 becomes 1, and the flip-flop Ul
8 is inverted, the NAND circuits U6 to U9 are disabled, and the level of all data output terminals is set to 1. At this point, the levels of the data output terminals of each basic circuit Al, A2, and A3 are (1, 1, 1, 1) (0, 1, 0, 1) (
1, 1, 1, 1), and the level of the common connection line is (0,
1,0,1). Next, the least significant bit EXNORU
Focusing on l3, each E of each basic circuit A, , A2, A3
The input levels of X-NORU13 are (1, 1) (
0,1)(0,1), and each output level becomes 1,0,0, and even if a search pulse is applied to terminal S1, the basic circuit A,
Since flip-flop Ul8 has already been inverted, there is no change in state, and the level of the common connection line is (0, 1, 0,
1). The level of this common connection line is for each basic circuit A,
, the maximum value of the input given to A2, A3 (1, 0, 1, 0)
Since it is the inverted value of , the maximum value can be detected by inverting the output level of the common connection line. To detect the minimum value of input data, keep the terminal H/L at O level, apply a set pulse to the terminal RESET to set the initial state, and then use the same procedure as for detecting the maximum value to detect the data output terminal D.
The minimum values are obtained at 8, D4, D2, and Dl.

However, the minimum value obtained in this way is not inverted and the input data is obtained as is. In Figure 3, the data output terminals shown in Figure 2 are connected to each common connection line, and the maximum and minimum values can be arbitrarily selected.
-NORU, . . . - is connected to one input of U22, and the other input is connected to terminal H/L.

The output of each EX-NORU1, -U22 is connected to the input of a 4-bit latch circuit U23. A latch pulse may be supplied to the latch terminal E of the latch circuit U23 after a search pulse is supplied to the terminal S. As a result, in the case of the maximum value, the level can be inverted and latched, and in the case of the minimum value, the level can be latched as is without inverting the level, and the maximum value and minimum value can be arbitrarily selected and latched. As described above, according to the present invention, the maximum value of the data input can be determined by comparing the levels of many data inputs sequentially from the most significant bit to the least significant bit, and removing bits whose levels are determined to be low for each bit. Because it is detected, it is for n-bit data.

Since the maximum value can be detected simply by searching for 2 pulses, the detection speed is fast and the circuit configuration is extremely simple. It should be noted that the present invention is not limited to the above-mentioned embodiments, but includes, for example, 4
It can be applied not only to bit data but also to data with an arbitrary number of bits.

Furthermore, instead of just three pieces of data, any number of pieces of data may be used by adding a basic circuit. If only the maximum value is to be detected, EX-0RU1 to U4 can be omitted, and if only the minimum value is to be detected, an inverter may be used in place of EX-0RU1 to U4. Furthermore, if the input data holding time is sufficiently longer than the time for sequentially applying search pulses to the terminals S8, S4, S2, and Sl, the latch circuit U5 can be omitted. Also, the Q output D of flip-flop Ul8. can also be used to indicate the status of basic circuits. Furthermore, when used as an interrupt generation circuit for a computer, after processing the interrupt, the contents of the latch circuit U can be cleared to allow interrupt processing to be performed in order of interrupt priority. As described above, according to the present invention, the maximum value or minimum value of multiple input data can be detected at high speed with a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a basic circuit diagram of the maximum value detection circuit device according to the present invention, Fig. 2 is a connection diagram for setting multiple inputs, and Fig. 3 is an additional device for arbitrarily setting the maximum value and minimum value. It is a circuit diagram showing an example.

Claims (1)

[Claims] 1 Connect one input of the 2-input type exclusive NOR circuit to the data input signal and one input of the 2-input type NAND circuit, and connect the other input to the data output terminal and the output of the above NAND circuit, respectively, and connect the exclusive NOR circuit. Connect the output to one input of a 2-input type AND circuit, and
ND circuits with other inputs connected to the search pulse terminal are provided corresponding to the number of bits of input data, the logical sum of the outputs of each AND circuit is obtained, and this is connected to the set input of the RS flip-flop. , RS flip-flop @Q@
The outputs are connected to the other inputs of each NAND circuit, corresponding to the number of input data, and the output terminals and search pulse terminals of the same bit are respectively connected, and the reset inputs of each flip-flop are commonly connected. Maximum value detection characterized in that after resetting the flip-flop, the maximum value of input data is detected at the data output terminal by sequentially applying single pulses from the high-order bit side terminal of the search pulse terminal. circuit device.