JPS5944635B2 - Digital signal storage display circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal storage and display circuit that stores video signals input at low speed and displays the stored contents on a television receiver at high speed.

Conventionally, this type of device stores display pixels arranged so as to sweep the rows to be displayed in the width direction as video signals in a shift register, and synchronizes the stored video signals with the synchronization signal of the television receiver. At least it was cyclically read out and displayed at high speed. However, in this type of device, if the width of the display line differs, the memory format must be changed, making the circuit complex, and if the display start point is not at the beginning of the display area, input must be performed even in the non-display area. Input time was wasted. Furthermore, when the device is used as a learning machine, there is a need to display characters in the order of strokes, but conventional devices cannot meet this requirement. Therefore, in order to eliminate the drawbacks of the conventional device and meet the needs of a learning machine, the present invention employs a random access memory (hereinafter referred to as RAM) as a storage element, and uses an address signal corresponding to a storage location in the RAM. The purpose of this paper is to propose a new digital signal storage/display device that uses character pattern position information as an input signal. The present invention will be described in detail below according to an illustrative embodiment.

First, as shown in FIG. 1a, the input signals are signals arranged in the order of control signal C) display signal V, no-signal period/and audio signal A, and the control signal C is the signal that is arranged in the order of the audio signal A and the audio signal A. The display signal V is a special signal that can be determined, and the display signal V is a set of address signals CD arranged according to the order of strokes as shown in FIG. As shown in Figure C, there is a main pilot signal MP at the beginning and a sub pilot signal S at the front.
15 digital signals 1D1-D via P respectively
, 5. The main pilot signal MP is twice as long as the sub-pilot signal SP, and the digital signal D has a binary value of "0" or "1". Therefore, in this embodiment, the entire video signal is converted into FS, considering that the digital signal is converted into an analog signal in order to reproduce the input signal with an audio tape recorder.
Modulation, i.e. tie [one pilot signal MP to 2KHz
2 wavelengths of sine wave (1msec), Sad? The rod number SP is a 2KHZ sine wave with one wavelength (0.5msec), and the digital signal DO)''0 is a 4KHZ sine wave with two wavelengths (0.5msec).
msec), digital signal D(7) 611 to 6101
The Z sine wave has three wavelengths (0.5 msec).

The operation of this apparatus when the reproduction signal as described above is input from a tape recorder will be described in detail below with reference to the circuit block diagram shown in FIG. The playback output of the tape recorder TP is input to a control signal detection circuit CN that predicts the arrival of the display signal V.

The control signal detection circuit CN which has detected the control signal C sets the first flip-flop FF1 and clears the contents of the memory circuit MM, which will be described later. The set output of the first flip-flop FFl switches the signal switching circuit CH to the video system circuit side. Therefore, the display signal V
is input to the demodulation circuit DM via the signal switching circuit CH to obtain a waveform as shown in FIG. Then, the outputs are inputted to a first waveform shaping circuit CPl and a second waveform shaping circuit CP2, which shape the output into positive and negative waveforms, respectively, and the digital signal D and pilot signal shown in FIGS. 5B and 5C are generated. It is separated into MP and SP. Further, the output of the second waveform shaping circuit CP2 is further inputted to a delayed pulse generation circuit DL which generates a shift pulse with a slight delay with respect to the rising edge of the second waveform shaping circuit CP2, and as shown in FIG. A shift pulse S to SR is derived.
Therefore, the shift register SR temporarily stores 15 digital signals forming the address signal CD. On the other hand, the shift pulse S shifts the contents of the shift register SR, and also shifts the contents of the shift register SR.
Trigger l, RM2. That is, the first triggerable monomulti RM detects the position of the main pilot signal MP where the shift pulse S is not generated for 2 msec with a metastable period of about 1.5 msec, and generates the main pilot pulse m. 2nd triggerable mono multi RM
2 has a quasi-stable period of about 5 msec, detects that the shift pulse S is discontinued, and generates a reset pulse to the first flip-flop FFl in order to switch the path of the input signal to the audio system circuit. above) shift register SR
Since the main memory circuit MM performs write and read operations, the 15-bit address signal CD recorded in the 15-bit address signal CD must specify the write position outside the period in which the read operation is performed for display.

Therefore, the address signal CD of the shift register SR is
In order to input the address of the main memory circuit MM during the non-display period of the horizontal scanning section without directly specifying the address of the main memory circuit MM with the main pilot signal MP, the second flip-flop FF2 set by the main pilot pulse m is set in the open state. Horizontal periodic signal H via the first AND gate A1
is input to a mono-multi MO whose metastable period is set to the non-display period of horizontal scanning, and the (metastable) output of the mono-multi is written to the selected output of the address signal CD and the main memory circuit MM. They are also used for the input command signal and the second flip-flop set output. Therefore, when the address signal CD is input to the main memory MM, the contents of the corresponding address are inverted in level, and the level-inverted addresses form a pattern. On the other hand, in connection with the scanning of the television receiver T, the read address signal RC reads out all the stored contents written in the main memory circuit MM in a sweeping manner, and the display area shown in FIG.
+1) In a display area extending from the (X+1)th picture element to the (X+256)th picture element of the horizontal synchronization signal from the main to (Y+128)th picture element, characters that are being memorized are displayed in accordance with the stroke order.

Such a read address signal is derived from a circuit such as the block diagram shown at the bottom of FIG. That is, the output of the pulse generator 0SC, which generates pulses corresponding to the picture elements scanned by the television receiver TV, is transmitted to the first gate control circuit B.
Xl and the second AND gate circuit A2. The output of the first gate control circuit BXl starts with the horizontal synchronizing signal H, rises at the X-th pulse of the output of the first half pulse generator, falls after counting 256 pulses, and remains in a high state in the display area. Become. Therefore, the second AND gate A, which is controlled by the output of the first gate control circuit, converts the output of the pulse generator to (X+1) with the horizontal synchronization signal H as the starting point.
256 pulses from the th pulse are passed.
Further, the second gate circuit BX2 that counts the horizontal synchronization signal H is
Generates an output that starts at the vertical synchronization signal and rises at the (Y-1)th horizontal synchronization signal H (falls at the Y+12Jth horizontal synchronization signal H. Therefore, the rise of the output of the second gate control circuit is captured. The output of the differentiating circuit DF which generates a pulse is used as a clear pulse of the counting circuit CT,
The output of the third AND gate A3, which takes the logical product of the first gate control circuit output and the second gate control circuit output, is used as a control signal for the display gate DG. The counting circuit CT, which is cleared by the output of the differentiating circuit and counts the output of the second AND gate A2, counts all the pulses input in relation to the horizontal synchronizing signal H, and each of the counting circuits CT Pit output is read address signal RC
form. The address selection circuit CS which receives the address signal CD and the read address signal RC selects the address signal CD only when an output from the mono-multi MO is generated, and normally selects the read address signal RC.

Therefore, a selected address signal and a monomulti output specifying writing or reading are input to the main memory circuit MM&Cj, and in addition to specifying the address, the stored contents are refreshed by the selected read address signal. The read memory content is converted into a video signal by the video conversion circuit M through the display gate DG, which is open only during display, and is further high-frequency converted by the high-frequency conversion circuit RF together with the output of the audio amplification circuit AA, and then sent to the television. The signal is input to the antenna terminal of the digital receiver T. The main memory circuit MM has a circuit configuration as shown in FIG.

Since the RAM, which is a storage element, cannot follow changes in the read code signal WC, in order to cyclically switch the four storage elements M1 to M4, the lower two bits of the address signal, which change rapidly, are selected from the storage elements M1 to M4. It is allocated to Therefore, the lower two bits of the address signal correspond to the memory elements M1 to M1.
The remaining upper 13 bits are input to the first multiplexer MPl on the input side and the diplexer DP on the output side of \, and the remaining upper 13 bits are input to each storage element, and at the time of writing, each storage element in the writing state is input by monostable multi-output. The same code is specified for M1 to M4, and the first and second multiplexers MPl and MP2
High level generation circuit HL is applied only to the memory element specified by
At the time of reading when the output of the read address signal RC is input, the output of each memory element that reads the contents of the same address at a rate of 1/4 of the change in the read address signal RC is controlled by a diplexer DP that selects the output according to the change in the read address signal RC. It is configured to select and read out cyclically. In this embodiment, if the display speed is too fast to confirm the stroke order, it goes without saying that the display speed can be freely adjusted by repeatedly recording the same address on the tape in advance. Therefore, according to the present invention as described above, a learning machine capable of displaying the stroke order is made possible, and not only is the circuit configuration simple and costs can be reduced, but the size of the displayed characters can be freely adjusted, so the effect is It's large.

[Brief explanation of the drawing]

The figures are particularly illustrative of one embodiment of the present invention; Fig. 1 is an explanatory diagram showing the recording state of a tape, Fig. 2 is a main circuit block diagram, and Fig. 3 is a display of a television receiver. Figure 4 shows a detailed block diagram of the main memory circuit, and Figure 5 shows a waveform explanation diagram of the main circuit block diagram of Figure 2.〇Explanation of main figure numbers, C... ...Control signal, ...Video signal, Z...No signal section, A...Audio signal, CD...Address signal, TP... ...Tape recorder, SR・
...Shift register, 0SC...Pulse generator, CT...Counting circuit, CS...
Address selection circuit, MM... Main memory circuit, R
F...High frequency conversion circuit, T...Television receiver.

Claims (1)

[Claims] 1. A display signal consisting of positional information corresponding to display picture elements constituting a multi-stroke character pattern arranged in stroke order is reproduced at low speed so that a display signal corresponding to a unit stroke is derived in a period longer than the field period. , the position information is patterned and stored in a memory corresponding to the display area at a scanning timing outside the display area of the television receiver; and the position information is stored in synchronization with the display area scanning timing of the television receiver. A digital signal storage and display circuit that reads the stored information from the memory in address order at high speed and displays the read information in a display area on a television screen.