JPS5945157B2 - Image memory - writing speed conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a graphic display device including:
DDA (Digital Differential An
When writing the image data calculated by the DDA
The present invention relates to an image memory write speed conversion circuit used to match the difference between the calculation speed of the circuit and the write speed of the image memory configured with an IC.

Traditionally, most graphic display devices have used so-called analog memory, such as storage tubes or phosphors on monitor CRT tubes, to store their images.

However, with the recent development of IC technology, low-cost digital IC memories with large storage capacities have been realized, and it has become practically possible to use these as image memories. The digital IC memory that can be used for this image memory is a MOS type LSI with a large storage capacity.
Among these, the refresh type is particularly suitable for image memories that require a very large storage capacity because it is easy to obtain one with a large storage capacity. However, the above-mentioned IC memory that can be used as an image memory has a long cycle time, and for example, a refresh type memory usually requires a writing time of 800 ns or more, including the time required for refreshing.

This writing speed of 800 ns is too slow considering that the image creation speed of the DDA circuit is preferably 200 ns or less. Therefore, in order to write the image data calculated by the DDA circuit into an image memory constituted by a digital IC, it is necessary to overcome the difference in speed between the two. The present invention was made in view of the above background, and its purpose is to transfer image data calculated by the DDA circuit to a digital IC without reducing the calculation speed.
An object of the present invention is to provide an image memory write speed conversion circuit suitable for writing data into an image memory having a slow writing speed without difficulty.

In other words, the image memory writing speed conversion circuit according to the present invention converts a buffer memory into a display device in which the image memory is formed of a digital IC, in order to write image data calculated by a DDA circuit into the image memory. At the same time, the X-axis and Y-axis address data determined by the DDA circuit are divided into upper digit and lower digit data, and the upper digit data determines the address of the image memory, and the lower digit The data also determines the address of the buffer memory 1, and when the address data of the X-axis or Y-axis changes beyond a certain range, the image data stored in the buffer memory 1 is transferred in parallel to the image memory 1. A detailed embodiment thereof will be described below with reference to the drawings.

First, FIG. 1 shows an outline of a display device in which a writing speed conversion circuit according to the present invention is implemented, which includes a display processor 1, a DDA circuit 2, an X-axis address counter 3a, . Y-axis address counter 3b,
It is composed of a write speed conversion circuit 4, an image memory 5 composed of a digital IC, a video circuit (not shown), and the like.

Here, the display processor 1 develops a display file provided by a host computer 1 (not shown) to obtain data necessary for generating straight lines and curves, including scale, rotation, etc. The DDA circuit 2 is designed to calculate image data based on the data obtained by the processor 1. The X-axis address counter 3a and the Y-axis address counter 3b count up or down, respectively, based on the image data calculated by the DDA circuit 2, thereby reading the address data of the X-axis and Y-axis. It is designed to be created and output in parallel. The write speed conversion circuit 4 reads, stores and stores the image data at high speed based on the address data, and whenever the address data changes beyond a certain range, the write speed conversion circuit 4 reads the image data stored and stored during that time. are transferred in parallel to the corresponding addresses in the image memory 5. What is shown in FIG. 2 is the write speed conversion circuit 4 and its peripheral parts.
It is composed of an axis address selection section 7, a Y-axis address selection section 8, and an overflow detection circuit 9. The buffer memory 16 uses a bipolar type high-speed digital IC and forms an MXm memory array. The X-axis address selection section 7 selects among the address data output in parallel from the X-axis address counter 3a.
Based on the data consisting of n bits of lower digits, the address on the X-axis of the above-mentioned buffer memory 16 is determined, and the Y-axis address selection section 8 selects the address of the above-mentioned Y-axis address counter 3.
The addresses of the buffer memory 16 on the Y-axis are determined based on the data consisting of n bits of the lower digits of the address data output in parallel from the buffer memory 16. Then, the overflow detection circuit 9 detects the x-axis and Y-axis address counters 3a.
, 3b, it is detected whether the change in the address data on the X-axis or Y-axis exceeds a certain range, that is, the address range of the buffer memory 16. When this is detected, that is, when the address exceeds the capacity of the buffer memory 16, the image data stored and accumulated in the buffer memory 16 is read out all at once and written into the image memory 5. At this time, the writing location in the image memory 5 is determined based on the data of the upper digits of the x-axis and Y-axis address data. FIG. 3 shows a further embodiment of a part of the write speed conversion circuit 4, which includes a shift register array 10, an n-bit decoder 11, a shift counter 12,
A latch circuit 13, an AND gate 14, 0R gates 15, 16, etc. are used. The shift register array 10 includes m bidirectional shift registers 10a to 10d.
This array is used as the buffer memory mentioned above. Each of the shift registers 10a to 10b uses a bipolar high-speed digital IC to increase its response speed. The n-bit decoder 11 inputs data consisting of n bits of the lower digits of the Y-axis address data output in parallel from the Y-axis address counter, and demultiplexes this input data into an alternative selection signal. It is designed to be encoded and output. This decoded signal is outputted by Zn=m selected terminals Y1 to Y4, each of which is connected to each serial input SR of the shift registers 10a to 10b. As a result, the shift register corresponding to the lower digit data of the Y-axis address data is selectively selected, and a selection signal is input thereto. The shift counter 12 counts high-speed clock pulses CP1, and is preset by data consisting of n bits of the lower digits of the X-axis address data output in parallel from the X-axis address counter. ing. Then, when the count value of the high speed clock pulse CP1 reaches the preset value. Set output S
Latch P. 13 to the clock input. The latch circuit 13 is latched by the set output, but until it is latched, the high speed clock pulse CP1 input to the count input of the shift counter 12 is passed through the AND gate 14 and the OR gate 15. The clock signal is continuously sent to each clock input port of the shift registers 10a to 10b. Here, in addition to the X-axis and Y-axis address data, the DDA circuit sends a DDA start signal DS. Mode control signal C/B. for determining the counting mode of the X-axis address counter, ie, count up or count down. Also, a clock pulse CP1 synchronized with the DDA operation speed is sent. The start signal DS is sent to each reset input of the shift counter 12 and the latch circuit 13, and is also sent to each clear input CL of the shift registers 10a to 10b via an 0R gate 16.
It is now also sent to R. Mode control signal C/
B is sent to each mode control input M of the shift registers 10a to 10b. Further, the clock pulse CPX is sent via the 0R gate 15 to each clock input CP of the shift registers 10a to 10d. With the above configuration, when the start signal DS indicating the start of calculation is sent from the DDA circuit, the shift register 1
0a-10c. The shift counter 12 and the latch circuit 13 are all reset.

Along with this, when X-axis and Y-axis address data are sent, the decoder 11 processes the . The shift register corresponding to the lower digit data of the Y-axis address data is alternatively selected, and the input bit of the selected shift register is set. That is, write a signal. On the other hand, the lower digit data of the 6X-axis address data is stored in the shift counter 12.
The soft counter 12 continues to operate the high speed crop pulse CP until its count value reaches the preset data value and the latch circuit 13 latches.
It will continue to count 1. Until this latching is done, the high speed clock pulses counted by the shift counter 12 are . It is also sent to each clock input of the shift registers 10a to 10b via an AND gate 14 and an OR gate 15.
A to 10b are shifted left and right according to the lower digit data of the X-axis address data. As a result, if the X-axis address data sent from the 6DDA circuit changes, the shift register array 10 shifts left and right in synchronization with the change, and the decoder 11 at that time selectively selects the data. A bit is now set at the serial input SR of the shift register. The bits set in this way correspond to each point of a two-dimensional figure made up of a series of points, and are based on the X-axis and Y-axis address data calculated by the DDA circuit. The information is written into the shift register array 10, arranged in a two-dimensional manner, and stored. At this time, the arrangement state of the bits written in the shift register array 10, for example, the consecutive direction of points represented by the bits, is determined by the mode control signal sent from the DDA circuit to determine the shift direction of the shift register array 10. 6 can be freely determined by controlling with C/B. In this way, the shift register array 10 has . While synchronizing with the calculation speed of the DDA circuit,
A portion of the image data O is written, but when the X-axis and Y-axis address data begins to go outside the address area defined in the shift register array 10, a detection signal 0D is output from the overflow detection circuit. uttered,
Some of the image data accumulated in the shift register array 10 up to that time. Each shift register 10a-1
6 digital I through 0d parallel output terminals QA-QD
At the same time, the shift register array 10 is reset and the reading and accumulation of the image data, which is subsequently calculated by the DDA circuit, is repeated again. FIG. 4 shows the relationship between the shift register array 10 and the image memory 10. If the storage capacity of the image memory with a slow writing speed is MXM bits/point, the shift register array 10 has a storage capacity of MXM bits/point. It has a storage capacity of MXm, which corresponds to one partition divided into 6 planes (two-dimensionally).

The image data that is sequentially operated by the DDA circuit is first written in series to the shift register array having a storage capacity of MXm, and the image data goes outside the address area of the shift register array. Then, the image data that has been written and accumulated up to that time is written in parallel to the corresponding address of the image memory while maintaining the write arrangement state. By repeating this writing, image data is written into the image memory 6 for each divided section. Here, suppose the storage capacity of the image memory is 1000 x 1000 bits/point,
On the other hand, the storage capacity of the shift register array is 1
Assuming 6 x 16 bits/point, the write cycle of the above image memory is, on average. The calculation cycle is about 16 times longer than that of the DDA circuit, so that the difference between the image creation speed of the DDA circuit and the writing speed of the image memory can be sufficiently overcome. As described above, the writing speed conversion circuit according to the present invention provides a write speed converting circuit for a display device in which the image memory is composed of a digital IC.
A 6-puffer memory is provided to write the image data calculated by the DA circuit, and each address data of the X-axis and Y-axis determined by the 6 DDA circuits is converted into upper digit and lower digit data, respectively. The upper digit data determines the address of the image memory, and the lower digit data determines the address of the buffer memory, so that the X-axis or Y-axis address data changes beyond a certain range. By transferring the image data stored in the buffer memory 6 to the image memory in parallel when It is possible to write image data without difficulty in an image memory which is configured with a 6-video display and has a slow writing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an outline of a display device in which the present invention is implemented. FIG. 2 is a block diagram showing a part of it. FIG. 3 is a circuit diagram illustrating a part of the image memory write speed conversion circuit according to the present invention. FIG. 4 is a diagram showing the relationship between the image memory and the buffer memory. 1: Display processor 1, 2: DDA circuit, 3a
:x-axis address counter, 3b: Y-axis address counter, 4: writing speed conversion circuit, 5: image memory, 6: buffer memory, 7: X-axis address selection section, 8: Y-axis address selection section, 9: overflow 1 detection circuit; 10: shift register array;

Claims (1)

[Claims] 1. In a display device whose image memory is composed of a digital IC, a buffer memory is provided in order to write the image data calculated by the DDA circuit into the image memory, and the image data determined by the DDA circuit is provided. Each address data on the X-axis and Y-axis is divided into upper digit and lower digit data, and the upper digit data determines the address of the image memory, and the lower digit data determines the address of the buffer memory. and when the X-axis or Y-axis address data changes beyond a certain range, the image data stored in the buffer memory is transferred in parallel to the image memory. Write speed conversion circuit.