JPS5945159B2 - Display drive device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display driving device suitable for a preset display device such as a preset receiver, and particularly to a display driving device that drives more display elements than the number of timing signals with a timing signal of the least digit. The purpose is to reduce the number of IC pins when devices are integrated.

Recently, with the advancement of digital technology, so-called preset receivers have been put into practical use that electronically control the channel selection operation and are equipped with a storage device to electronically preset desired stations.

By the way, in such a preset receiver, in order to display the preset channel selection state, a preset display element is provided corresponding to each preset key, and is configured to display which preset key is in the operating state. has been done. In conventional display devices, a display element corresponds to each preset key, so as the number of presets increases, the number of output signal terminals to the display element increases, and when the device is integrated, the number of IC pins increases. This has led to an increase in demand for improvements in display driving devices. Therefore, the present invention has been made in view of the above points, and provides a display driving device that can drive 10 display elements using a half 5-digit timing signal when the number of presets is 10, for example. It is.

An embodiment of the present invention will be described below with reference to the drawings.

Reference numeral 1 denotes a key input circuit to which preset keys P1 to PIO are connected, and is configured to output numerical data corresponding to the key operation, and the output is sent to the storage device 2 as an address signal.
is configured to control the storage device.

Reference numeral 3 denotes a determination circuit which uses the output of the key input circuit 1 as one input and the output of the constant setting means 4 to which a constant "5" is set as the other input, and the output is connected to the set terminal of the flip-flop 5. Saw, one input is the other input, i.e.
``The flip-flop 5 is set when the value is greater than ``.''.

6 is an arithmetic circuit which takes the output of the key input circuit 1 as one input and the output of the constant setting means as the other input, and subtracts the input ``5'' of the other from one input, and the output is the same as the one input. AN to which the set output Q of flip-flop 5 is connected
It is connected to the other input of D gate 7.

8 is an AND gate having one input connected to the output of the key input circuit 1 and the other input connected to the reset output Q of the flip-flop 5;
It is connected to one input of the matching circuit 10 via an OR gate 9 along with the output of the matching circuit 10 .

Reference numeral 11 denotes a timing signal generator that generates timing signals as shown in FIG.
It is connected to a display element drive transistor, which will be described later.

Further, a resetting pulse generated from the timing signal generator 11 every timing signal cycle is connected to the resetting terminal of the flip-flop 5. Incidentally, the coincidence circuit 10 generates the output of the 0R gate 9 connected to one input in synchronization with the timing signal connected to the other input, and the output is generated by the set output of the flip-flop 5 connected to one input. A to which Q and set output Q are connected
It is commonly connected to the other input of ND gates 12 and 13. L1 to L5 are preset display LEDs corresponding to the preset keys P1 to P5, respectively, whose anode electrodes are commonly connected to the output of the AND gate 13, and whose cathode electrodes are grounded via drive transistors Trl to Tr5, respectively. The timing signals T1 to T5 are applied to the bases of the transistors, respectively. L6~Ll
0 is a preset display LED corresponding to each of the preset keys P6 to P1O, whose anode electrode is commonly connected to the output of the AND gate 12, and whose cathode electrode is connected to the collector of the drive transistors Trl to Tr5, respectively. Next, the operation of the present invention having such a configuration will be explained.

First, when no preset key is operated, the flip-flop 5 is in the reset state by a reset pulse from the timing pulse generator 11. Next, if the third preset key P3 is operated in this state, the numerical data 03 corresponding to the third from key input circuit 1
” is output.

At this time, the address corresponding to 63'' is selected in the storage device 2, and the stored data is output.Meanwhile, the determination circuit 3 determines that the output of the constant setting means 4 is 15''; Since it is small, no output is obtained from the determination circuit 3 and the flip-flop 5 is not set. Therefore, the flip-flop 5 continues to be in the reset state, and the AND gate 8 is opened by the set output Q, and the numerical data 63'' is inputted to the matching circuit 10 via the 0R gate 9.Then, the matching circuit 10 outputs the numerical data 131. A pulse A synchronized with the corresponding timing signal T1 is obtained and applied to the AND gate 13, so that the AND gate 13 is opened and, at the same time, the driving transistor Tr is made conductive by the timing signal T3, and the third LED L3 is dynamically lit. It is displayed that the third preset key P3 is now being operated (see Figure 3).At this time, the LED L3 connected to the drive transistor Tr is
Since the D gate 12 is not opened by the preset key Ps, it is not lit. Thus, when the selection of preset key 1 is within the range of P1 to P5, flip-flop 5
The Otori LED in the beam set state is L! -L5 is selected, and the LED corresponding to the selected preset key can be lit based on the preset key data and timing signal. Next, a case will be described in which, for example, the ninth preset key P9 is operated.

At this time, the key input circuit 1 outputs numerical data 69'' corresponding to the 9th position, which is used as the address designation input digit of the storage device 2, and at the same time, the determination circuit 3 outputs the output 6 of the constant setting means 4.
5", and in this case, since it is larger than 65", an output is obtained from the judgment circuit 4 and the flip-flop 5
Set. On the other hand, the calculation circuit 6 performs the calculation "9-5" and outputs 64 times to the AND gate 7 and the 0R gate 9.
The signal is input to the matching circuit 10 via. At this time, since the flip-flop 5 is in the set state, the AND gate 8 is not opened. When the calculation data 04'' is input to the matching circuit 10 through the 0R gate 9, the data 64'' is inputted in the same manner as described above.
A pulse N synchronized with the timing signal T4 corresponding to " is obtained and applied to the AND gate 12, so that AN
At the same time as the D gate 2 is opened, the driving transistor Tr4 is driven by the timing signal T4, and the ninth LED is
L9 is dynamically lit to indicate that the ninth preset key P9 is currently being operated (see FIG. 4).

At this time, similarly to the above, the LEDL4 connected to the drive transistor Tr4 is not turned on because the AND gate 13 is not opened. Thus, the first selection of preset keys is P6~
When within the range of PlO, flip-flop 5 is set to the set state, so that the LEDs are in the range L6-L! 0 is selected, and the LED corresponding to the selected preset key can be lit based on the preset key data and timing signal. In the above embodiment, the number of display elements is 10, but by changing the value of the constant setting means 4, it is possible to increase the number of display elements to 15 without changing the timing signal.
, 20 can be added.

As described above, the display drive device of the present invention is configured to combine several display elements into a set, compare or calculate the magnitude of input with a specific number, and select and drive a set of display elements in synchronization with a timing signal. Since it is possible to drive N times as many display elements as the number of timing signals, it is possible to greatly reduce the number of IC pins when integrating display driving devices, which has an extremely practical effect. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a display 1 driving device of the present invention, and FIG.
The figure is a waveform diagram of the main part of Figure 1, and Figures 3 and 4 are waveform diagrams explaining the operation of the present invention. DESCRIPTION OF SYMBOLS 1...Key input circuit, 2...Storage device, 3...Judgment circuit, 4...Constant setting means, 6...Calculation Circuit, 10... Matching circuit, 11... Timing signal generator.

Claims (1)

[Claims] 1. A display element group consisting of a plurality of display elements each corresponding to an input key, a selection signal for selecting the display element group, and a timing signal common to each group, dynamically select the corresponding display element by key operation. In a display driving device configured to turn on the light, a constant setting means is configured to set a constant for determining whether the input key data is large or small, a determining means is configured to determine whether the constant is large or small from the input key data, and a constant is set from the input key data. 1. A display driving device, comprising: arithmetic means for subtracting .times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..times..