JPS5945254B2 - clock output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock output circuit for extracting a clock for driving circuits in a large-scale semiconductor integrated circuit (LS).

Recently, due to the demand for lower prices, a CPG (clock pulse generator, oscillator) for timing generation is provided inside the LSI, and based on the output of this CPG, for example, 2
A method of creating phase clocks is used.

This method allows operation with an external oscillator (especially a crystal oscillator), and uses two terminals: an external CPG input terminal and a terminal for frequency adjustment of the built-in CPG, and input signals are applied to both terminals. Both CPGs can be switched depending on the state. That is, this method will be explained in more detail using the circuit of FIG. 1A. FIG. 1A is a circuit diagram of a clock output circuit employing the above-described method, and as shown in the figure, input signals φS and φR are input to external terminals P1 and P2.
NOR gate circuit G0, input signal φR, and built-in oscillator 1 controlled by this signal φR.
AND gate circuit G3 having two inputs of the output of
A NOR gate circuit G2 whose two inputs are the output of the OR gate circuit G1 and the output of the AND gate circuit G3, a frequency divider circuit 2 that receives the outputs of the two gate circuits G2, and this frequency divider circuit 2.
Output buffer circuit 3 (inverters G4A, G5A) receiving one frequency-divided output of push-pull configuration FETQ4,
Q2) and an output buffer circuit 4 (consisting of inverters G4B and G5B) which receives the divided output of the other frequency dividing circuit.
) consisting of push-pull configuration FETs Q3 and Q4).

The outputs φ1 and φ2 obtained from each output buffer are
The signal is supplied to a predetermined internal circuit (not shown). Furthermore, the outputs φ1 and φ2 are applied to external terminals P3 and P4 so that they can also be supplied outside the LSI. FIG. 1B is a timing chart for explaining the operation of the clock output circuit. First, when using an external oscillator, the output of the external oscillator is applied to input terminal P1, and the output of the external oscillator is applied to input terminal P1.

Assume that the signal φR applied to the input terminal Fix the signal φs applied to P1 at ``0'' or 1'',
If the signal φ1 applied to the other input terminal P2 is set to ``1'', an oscillation output φ can be obtained from the NOR gate circuit G2. By passing the oscillation output φ obtained in this way through a frequency divider 2 and output buffer circuits 3 and 4, frequency-divided outputs φ1 and φ2 are obtained. Normally, as shown in Figure 1B, the oscillation output φ is 300 KHz, the frequency division outputs φ1 and φ2 are set to obtain the oscillation output φ divided by 7, and the first The phase difference between the frequency output φ1 and the second frequency-divided output φ2 is designed to cause a delay of five pulses of the oscillation output φ. Therefore, the width 11 from the arrival of the second frequency-divided output φ2 to the first frequency-divided output φ1 corresponds to three pulses in the oscillation output φ. As described above, the lock output circuit can only obtain signals based on the outputs of the external oscillator and the built-in oscillator, which is inconvenient when testing LSI characteristics, particularly timing characteristics.

For example, when the frequency divided output φ2 is used for precharging of a ratioless MOSFET circuit and the frequency divided output φ1 is used for decharging, if the period '1 from the arrival period of φ2 to the arrival period T2 of φ1 is short, Among the plurality of circuits, a circuit may be driven without being precharged to the end, which may result in malfunction. To perform such a timing check, a clock having a width (12) that allows sufficient precharge time is required, as shown in FIG. 1B. In other words, the function of the clock output circuit is not only to switch between the external oscillator and the built-in oscillator to obtain a divided output with a constant phase difference as described above, but also to apply a clock with a different phase difference from the outside during timing measurement. The present invention has been made in response to the above-mentioned demands, and its purpose is to provide a clock output that allows clocks to be applied from outside without increasing the number of control terminals. The purpose is to provide circuits.

The present invention will be specifically described below with reference to embodiments and drawings.

FIG. 2 is a circuit diagram showing an embodiment of the clock output circuit of the present invention.

As shown in the figure, input signals φs and φR are input to input terminal Pl.
, P2, an AND gate circuit G3 whose two inputs are the input signal φ, and the output of the built-in oscillator 1 controlled by this signal φ.
The output of the above NOR gate circuit G1 and the AND gate circuit G
A NOR gate circuit G2 having two outputs from the gate circuit G2, a frequency divider circuit 2 receiving the output of this gate circuit G2, an output expansion circuit 3 receiving one of the divided outputs of this frequency divider circuit 2, An output buffer circuit 4 receiving the frequency-divided output of the other circuit and an AN having two inputs of the input signals φ8 and φ.
It consists of a D gate circuit GlO.

The output buffer circuit 3 includes the AND gate circuit Gl.
NO whose 2 inputs are the output of O and one output of frequency divider circuit 2.
An R gate circuit G6, a NOR gate circuit G7 whose two inputs are the output of this gate circuit G6 and the output of the AND gate circuit GlO, and FETs Ql and Q2 that receive the outputs of the respective gate circuits G6 and G7 are connected in series. Consists of circuits. The second output buffer circuit 4 also includes a NOR gate circuit G8 having two inputs, the outputs of the AND gate circuits G and O and the other output of the frequency divider circuit 2, and this gate circuit G8.
a NOR gate circuit G having two inputs, the output of and the output of the AND gate circuit GlO, and each of the above gate circuits G8
, G, and a series connection circuit. Then, the frequency-divided output φ, is transmitted from the output point of the first output buffer circuit 3 to the second output buffer circuit 3 via the output terminal P3.
A divided output φ2 is obtained from the output point of the output buffer circuit 4 via the output terminal P4. According to the circuit configured as above, the following operations are performed. (1) When using the built-in oscillator, the input signal φs is set to logic "O", and the input signal φR is set to logic "1".

Built-in oscillator 1 is activated by “1” of input signal φR, and N
The gate of OR gate circuit G2 is opened, and an oscillation output φ is obtained as its output. This output φ is frequency-divided by a frequency dividing circuit 2, and the frequency-divided outputs can be taken out as outputs φ1 and φ2 via output buffer circuits 3 and 4, respectively. At this time,
Since the outputs of the AND gate circuits G and O are 330'', the gate circuit G6 of the output buffer circuits 3 and 4
The gates of ~G, are open, and frequency-divided outputs φ1 and φ2 are obtained according to the output of the frequency divider. (2) When using an external oscillator Set the input signal φ to "0" and apply the output of the external oscillator to the input terminal P1.

At this time, the NOR gate circuits Gl and G2 are opened, and the output φ of the external oscillator is applied to the input point of the frequency dividing circuit 2. This output φ is frequency-divided by a frequency dividing circuit 2. The divided outputs are outputted via output buffer circuits 3 and 4, respectively.
1, can be taken out as φ2. At this time, since the output of the AND gate circuit GlO is 0'', the gates of the output buffer circuits 3 and 4 are open, and frequency-divided outputs φ1 and φ2 corresponding to the output of the frequency divider are obtained. (3) When applying external clocks with different phases, the input signal φS,
By setting both φR to 1, the AND gate circuit G
, O's output becomes ゛1゛, so this output is applied to N
All gates of OR gate circuits G6 to G are closed, and each output point becomes a logic 80°.

This logic '01' turns FETQ to Q4 off. Output terminals φ1 and φ2 are in high impedance state,
In other words, it becomes a floating state. Output terminal φ,,φ
Due to the floating state of 2, these output terminals P3 and P4
A clock φ3 with an appropriate phase difference is input from the outside of the LSI.
, φ4 can be applied. The circuit inside the LS can be driven by this external clock. According to the circuit of the present invention, a desired clock signal, for example, a clock signal having a phase difference necessary for measuring circuit characteristics, especially timing characteristics, can be applied from outside the LSI without increasing the number of external terminals. 0, that is, by simply setting the signal levels applied to the control external terminals Pl and P2 to "1", the external terminal P3
, P4 are in a floating state. Therefore, it becomes possible to supply a desired clock signal freely formed outside the LSI to a circuit (not shown) inside the LSI via the external terminals P3 and P4. The present invention is not limited to the above embodiments, and various modifications can be made.

For example, in the above embodiment, the AND gate circuit GlO and the N
Although the output circuit is placed in a high impedance state using the OR gate circuits G6 to G, the combination of gates is not limited to this.

Further, one switching means is provided between the frequency dividing circuit and the output buffer circuit, and this switching means is connected to the above-mentioned A.
It may be driven by the output of the ND gate circuit. The present invention can be widely used as a clock output circuit to which a test and measurement clock can be externally applied without increasing the number of control terminals.

[Brief explanation of the drawing]

FIG. 1A is a circuit diagram showing an example of a conventional clock output circuit, FIG. 1B is a timing chart for explaining its operation, and FIG. 2 is a circuit diagram showing an example of the clock output circuit of the present invention. 1... Built-in oscillator, 2... Frequency divider circuit,
3, 4...Output circuit, G1-G,O...
・Gate circuit, Q1~Q4...FETsPl~
P4...Terminal.

Claims (1)

[Claims] 1 first and second external terminals to which external signals are applied;
a clock pulse signal generation circuit, a gate circuit that receives the external signal or the clock pulse signal, an output circuit that is controlled by the output signal of the gate circuit, and a third external terminal that is an output terminal of the output circuit. A semiconductor integrated circuit comprising at least a semiconductor integrated circuit, wherein a pulse signal applied to the second external terminal based on a first signal level of the first external terminal is applied to the output circuit via the gate circuit. and a third external terminal, and the clock pulse signal generation circuit is configured to transmit the clock pulse signal to the clock pulse signal generating circuit according to the second signal level of the first external terminal and the first or second signal level of the second external terminal. A clock pulse signal outputted from the gate circuit is transmitted to the output circuit and the third external terminal via the gate circuit, and the second signal level of the first external terminal and the second external terminal are A semiconductor integrated circuit characterized in that the output impedance of the output circuit is brought into a high impedance state by the second or first signal level of the terminal.