JPS5946078B2 - sense amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sense amplifier, and is particularly directed to a flip-flop type pre-sense amplifier.

As an example of a flip-flop type pre-sense amplifier used in a semiconductor memory device, the one shown in Figure 1 is known. This is a circuit diagram showing the arrangement situation. Focusing on the pre-sense amplifier located at the bottom stage, a flip-flop circuit is constructed with load FETs (insulated gate field effect transistors) Q1 and Q2 and switching FETs Q3 and Q4. A driving FETQ5 is provided between the flip-flop circuit and the ground terminal.
The load FETs QI and Q2 are driven by a drive signal φSA. The output point of this pre-sense amplifier is connected to data lines Do and Y5o. A pre-sense amplifier with such a configuration first has a data line D.

, Do are both precharged to the VDP (approximately half the potential of VDD) level, and this pre-sense amplifier is driven by applying the drive signal φSA, and the data is determined by the potential difference between the data line potentials V1 and V2 at this time. It is used to read or write. However, as shown in the figure, all the pre-sense amplifiers (128) are in the operating state by applying the drive signal φSA, so one of the load FETs is always turned on, and from all the pre-sense amplifiers, Current flows through drive FETQ5. This has the disadvantage of increasing power consumption. Incidentally, according to the inventor's experimental results, the current value flowing through one pre-sense amplifier was 68 mA, and the current value flowing through all (128 amplifiers) was 87 mA. As an example of a pre-sense amplifier that reduces the power consumption described above, one as shown in FIG. 2 can be considered.

As shown in the figure, a load FETQ. , Q, A flip-flop circuit is constructed by switching FETs Q8 and Q9, and has a driving FET Q1o, and is generally called a dynamic pre-sense amplifier.
This is different from the one in FIG. 1 above, and the data line D. J
Σ is provided on the source side of the load FETs Q6 and Q7. According to this circuit, switching FETQ8,Q
, data can be read by the difference between voltages 1 and V2 applied to the gates of , and at this time, there is no current path from the power supply VDD, so power consumption is low. However, in this circuit, one of the data lines is first charged up to the VDD level, and then the drive signal φSA is applied to perform discharge, so timing that does not cause malfunction is required. For this reason, the operating speed is slow, and the FET is
Since Q6 and Q7 do not operate as loads, write operations cannot be performed with the old pre-sense amplifier with this configuration, and two separate
This method has drawbacks such as the need for a write circuit for applying two contradictory signals Din and aTn. Therefore, an object of the present invention is to provide a sense amplifier with low power consumption.

Another object of the present invention is to provide a refreshence amplifier capable of refresh operation. Still another object of the present invention is to provide a pre-sense amplifier whose operating speed can be easily increased. One embodiment of the present invention improves output characteristics by applying a bootstrap to the gate of each load FET via a capacitor based on the potential of the output terminal of a clip-flop type sense amplifier. It is something that

The present invention will be specifically described below with reference to embodiments and drawings.

FIG. 3 is a circuit diagram for explaining the configuration of the present invention.

In the following description of the present invention, parts corresponding to the circuit diagrams described above are indicated by the same reference numerals. As shown in the figure, the load FET
The load FET Ql of the flip-flop circuit constituted by Ql, Q2 and switching FETs Q3, Q4.
Q2 gate and data line D.

, DO, respectively, and the potentials at the connection points between the capacitors Cl, C2 and the gates of the FETs Ql, Q2 are set to φSA, φSA2, respectively. This object is achieved by using the capacitors Cl and C2 of the present invention as bootstrap means. According to such a circuit, for example, when the potential V2 of the data line reaches a high level (power supply VDD level),
The potential of φSA2 is increased by the capacitor C2, and the potential V2 of the data line becomes close to the DD level.

Next, when the potential V2 of the data line rises, FETQ is turned on, and the data line D is turned on. The potential V1 of decreases. Therefore, the potential of φSA is lowered by the capacitor C1, and the load FET Ql becomes close to an off state. As a result, the load FETQl has a high impedance due to its low gate potential, so FETQl→FET
The current flowing from Q3→FETQ5→GND becomes extremely small (one FETQ2→FETQ4→FETQ,→G
It goes without saying that no current will flow in the ND path since FETQ4 is inactive). The above-mentioned FIG. 3 is a circuit diagram for explaining the basic principle of the present invention, and it is not concrete as it is, but is actually embodied by a circuit diagram as shown in FIG. 4.

That is, FIG. 4 shows a specific circuit for actual use, and the load FETs Ql and Q2 are connected to the drive signal φ.
Since it is driven by SA, it has the same configuration as the conventional circuit, and the load FETs Ql and Q shown in the principle diagram of FIG.
FETs Qll and Ql2 that perform the same operation as 2 are newly installed, capacitors C and C2 are connected between the gates of these FETs and the data line, and these capacitors are precharged when the chip is not selected (CE-VDD level). Pre-charge FETs Ql3 and Ql4 are provided to keep the current.

Here, FET Qll, Ql2, capacitor Cl, C2
and precharge FETs Ql3 and Ql4 are referred to as bootstrap means. Note that FETQ3 and Q4 are switching FETs, and FETQ5 is a driving FET. FIG. 5 is a timing chart for explaining the operation of the above circuit.

First, when the chip is not selected (CE=VDD level), the capacitor terminal potentials φSA, φSA2 are set to VDD-Vth.
(Threshold voltage of FET) and data line D.

, TiO potentials 1 and V2 are precharged to the VDP level. At this time, the gate potential φSAl'φSA of FETQll7Ql2 to which capacitors C, , C2 are connected
2 is a potential V higher than the DP level of the data line potentials 1 and 2 by the voltage based on the accumulated charge of the capacitor.
DC (period T). Next, chip selection signal C
When E is applied (period t1) and this data line is selected, a potential difference is generated between the outputs 1, , of this pre-sense amplifier due to the data in the memory cell. For example, if Vl and 2 are at a high level and 2 is at a low level, Vl and 2 are divided as shown in the figure (period T2). Then, the pre-sense amplifier drive signal φS
When A is applied, discharge is performed by the drive FET Q5, and the potentials 1 and 2 at the output point are further separated by turning on the FET Q4 to which a high level 1 is applied (V1>2). At this time, the gate voltages φSAl and φSA2 of FETs Qll and Ql2 are voltage-divided due to the bootstrap effect of capacitors Cl and C2, and in particular, the charge of capacitor C2 is removed via FETQ4 and FETQ5, so the gate potential φSA2 of FETQl2 decreases. (on the other hand, φSAl increases). Therefore, the impedance of FETQl2 becomes high and the load FET
ETQ2→FETQl2→FETQ4→FETQ5→G
The current flowing through ND becomes extremely small (period T3). Thus, predetermined reading can be performed when the potentials are completely separated (period T4). Note that during writing, for example, the data line D. If the potential 2 of the data line D is set to high or low level, the data line D. The inverted level is obtained at the potential V1 point, and a write operation can be performed without providing a special circuit, and a refresh operation is possible. As described above, the present invention minimizes the current path by increasing the impedance of the load FET using bootstrap means, and therefore consumes very little power.

By the way, according to the inventor's experimental results, the current consumption of 128 pre-sense amplifiers at 16K bits is 16mA.
This is approximately 80% less than that of the conventional circuit shown in FIG. 1 above. Further, according to the present invention, writing can be easily performed without providing a special writing circuit, and a refresh operation is possible.

Furthermore, unlike the conventional example shown in FIG. 2, the timing of precharging and discharging is not required, so the operation speed can be improved.

The present invention is not limited to the above embodiments, and various modifications can be made.

For example, as shown in FIG.
, one FE to which the drive signal φSA is applied instead of Q2
TQl, may be used as a load FET.

In such a case, the degree of integration can be improved. The present invention is applicable not only to all semiconductor memory devices but also to logic circuits, and has an extremely wide range of uses.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing →1 of a conventional pre-sense amplifier.
Fig. 2 is a circuit diagram showing another example, Fig. 3 is a circuit diagram for explaining the basic principle of the present invention, Fig. 4 is a circuit diagram showing an example of a specific configuration of the invention, and Fig. 5 is a circuit diagram for explaining the basic principle of the present invention. A timing chart for explaining the operation, and FIG. 6 is a circuit diagram showing another example of the present invention.

Claims (1)

[Claims] 1 a pair of first and second driving FETs and the first
A third FET is provided corresponding to the second FET, and a third FET whose drain and source are connected in series between the drain of the first FET and the power supply, and a third FET whose drain and source are connected in series between the drain of the first FET and the power supply. and the source is the above second FET
a fourth FET connected in series between the drain of the
, wherein the gate potential of each of the driving FETs is determined by the drain potential of the other driving FET, wherein the third and fourth FETs means that each gate potential is changed according to the change in the drain potential of the corresponding driving FET by the capacitance between the drain of the corresponding driving FET and each gate. Featured sense amplifier.