JPS5946452B2 - Noise removal circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise removal circuit that removes noise components contained in audio signals in equipment such as radio receivers that are susceptible to pulse noise interference.

Conventionally, this type of noise removal circuit has been shown in FIG.

In the figure, 1 is a noise detection circuit, 2 is a delay circuit, and 3 is a sample and hold circuit. FIG. 2 is a wiring diagram showing a more detailed operation of the sample and hold circuit 3, in which 4 and 8 are operational amplifiers, 5 is a field effect transistor (hereinafter abbreviated as FET), 6 is a resistor, and T is a It is a capacitor. 3A, 3B, and 3C are waveform diagrams of each part of this noise removal circuit.

Next, the operation will be explained.

When the noise detection circuit 1 receives an input audio signal a containing a noise component n as shown in FIG. 3A, it detects the noise component n and generates a noise detection signal which is a pulse in the negative direction. The delay circuit 2 is for correcting the operation time delay of the noise detection circuit 1 and completely removing the noise caused by the operation of the sample and hold circuit 3, and outputs a signal d obtained by delaying the audio signal a by a predetermined time. The sample and hold circuit 3 is controlled by the noise detection signal, and holds its output c at the voltage immediately before detecting the noise component n while the noise detection signal is being input, and keeps the input signal d as it is for other periods. is configured to print. In this way, the signal d input to the sample and hold circuit 3 is input with a slight delay due to the delay circuit 2 so that the noise component n is contained within the period in which the noise detection signal b is input to the sample and hold circuit. During the period when the noise component n of the signal d is included, the output signal c is held at the voltage immediately before the noise component n appears, and the noise component n is removed from the output signal c as shown in FIG. It becomes an audio signal. Next, let me explain a little about the sample and hold circuit. In Figure 2, F
ET5 operates as an electronic switch, and the source electrode and drain electrode are non-conductive (
OFF), and conductive (ON) during other periods.

Here, operational amplifiers 4 and 8 have high input impedance,
It operates as a buffer amplifier with low output impedance. When the FET is ``0FF'', the capacitor 7 serves to keep the output voltage c substantially constant by the action of the electric charge stored inside it.Also, when the FET is ``0N'', the capacitor 7 is instantaneously charged and discharged by the output of the operational amplifier 4 through the FET, and its terminal voltage becomes equal to the output voltage of the operational amplifier 4. In addition, the operational amplifier 4
Since 8 and 8 are buffer amplifiers with a gain of 1, the input signal d and the output signal c are approximately equal during the period when the FET is "ON". When the FET reaches t'OFF0, the capacitor 7
A charge corresponding to the voltage just before is stored in the operational amplifier 8, but since the operational amplifier 8 has high input impedance characteristics, there is no discharge path for this, and therefore the terminal voltage of the capacitor 7 is held at an approximately constant value. , whereby the output voltage c of the operational amplifier 8 is also held constant.

As mentioned above, it was possible to completely remove the noise component even with the conventional circuit, but as shown in FIG. Waveform distortion was a major problem.

In other words, in the conventional circuit, if the time Ts for blocking noise becomes long, the noise removal circuit will generate more noise. As for the ingredients, sufficient effects could not be obtained. This invention was made in order to eliminate the above-mentioned drawbacks of the conventional circuit, and by adding a circuit to the conventional circuit to cancel out the distortion components generated when the sample and hold circuit operates, The purpose is to provide a noise removal circuit that can obtain sufficient effects even for wide noise components without increasing secondary noise. A transfer circuit transfers signals with waveform distortion caused by the circuit.
This purpose is achieved by creating a waveform with reduced waveform distortion using a correction signal generating circuit and an adder.

An embodiment of the present invention will be described below.

FIG. 4 is a block diagram of an embodiment of the present invention, and FIG. 5 is a wiring diagram of the main part thereof, that is, after the sample and hold circuit.
FIG. 6 is a waveform diagram of each part, and FIG. 7 is an example of frequency characteristics of the phase shift circuit. In the figure, 9 is a phase shift circuit, 10 is a clamp circuit, 11 is an integration circuit, 12 is an electronic switch, 13 is a differentiation circuit, 14 is a capacitor, 15 is a resistor, 16 is an addition circuit, and 37 is a correction signal generation circuit. be.

Here, the noise detection circuit 1, delay circuit 2, and sample hold circuit 3 operate exactly the same as in the conventional example. Therefore, the output signal c of the sample and hold circuit 3 is the same as in the conventional example, as shown in FIG. 6A. The phase shift circuit 9 has the function of converting the signal C into a waveform e that can effectively perform waveform compensation, as shown at the beginning of FIG. Once the waveform e has been converted in this way, by adding the correction signal f shown in FIG. 6C, a waveform g with significantly reduced distortion can be obtained as shown in FIG. 6B.
Next, the operation of the phase shift circuit 9 and the generation of the correction signal f will be described in detail.

The phase shift circuit 9 actually consists of an operational amplifier 17, resistors 18, 19, 20, and a capacitor 21, as shown in FIG.

Now, assuming that the value of the resistor 20 is R, the values of the resistors 18 and 19 are equal, and the value of the capacitor 21 is C, the characteristics of this phase shift circuit can be expressed as follows.

Here, V1 is the input voltage, V2 is the output voltage, and ω is the angular frequency of the signal. Further, when equation (1) is set, it can be easily proven that the amplitude characteristic G(0) and the phase characteristic φ(leakage) become.

In addition, the group delay characteristic τ (leakage is from equation (4)
, can be obtained as . 8th
The figure illustrates each characteristic when ωa=2·π·700 (radians/second).

The process by which sample-and-hold circuit output waveform C in FIG. 6 is converted into waveform e by phase shift circuit 9 can be explained as follows from the characteristics shown in FIG. 8 and the waveform diagram in FIG. 9.

First, the input signal to the phase shift circuit 9, that is, the sample-and-hold circuit output C, is added by the sample-and-hold circuit to the signal k that is considered to be obtained when there is no noise, as shown in FIG. It can be thought of as a superposition of distortion components 1.

Here, although FIG. 9 is an example of only a specific part of the signal, if the condition that the change in the signal is gradual compared to the sample-and-hold period T8 is established, then the distortion added to the signal waveform by the sample-and-hold Even if the waveform of the signal and the part sampled and held are different from those shown in FIG. 9, the components have a waveform similar to a sawtooth wave as shown in FIG. 9C, with only the difference in amplitude and positive/negative direction.

Therefore, it is thought that the discussion based on FIG. 9 can be applied to many other cases as well. Now, the input of the phase shift circuit 9 is the signal k,
Assuming that it is a composite wave of distortion component l, its output can also be considered to be a composite of the outputs of each component.

For convenience of explanation, the signal k is assumed to be a low-frequency sine wave.The output for the signal k is a sine wave m with a slight phase shift as shown in Figure 9 (2), and the output for the distortion component 1 is as shown in Figure 9 (E). This results in a distortion component p. The waveform discontinuity v in distortion component 1 is considered to have a very high frequency component, and is output with almost no delay in the phase shift circuit and with a phase change of 180 (degrees). A discontinuous portion v in the opposite direction to component 1 occurs. Moreover, the leading edge of the waveform of distortion component 1 is a monotonically increasing curve,
The frequency components can be considered to have a frequency spectrum biased towards relatively low frequencies, and most of them appear in the output with a relatively long delay time. As a result, most of the distortion components p are concentrated at the waveform discontinuity portion v and its trailing edge. Therefore, if the distortion component p can be canceled by some means so that it becomes the curve r shown by the broken line in FIG. 9, the composite output e shown in FIG. As shown, an output with reduced waveform distortion can be obtained. Next, the correction signal generation circuit 37 will be explained in detail.

The correction signal f has a waveform as shown in FIG. It is sufficient if the voltage is proportional to the voltage and the trailing edge is attenuated logarithmically, and in this embodiment as well, by providing such a correction signal f, an output signal g with relatively little distortion is obtained. .
In the example of FIG. 5, by utilizing the fact that the voltage change at the discontinuous part x of the waveform before passing through the phase shift circuit 9 and the discontinuous part y after passing through the waveform is equal, A correction signal f is generated from the output signal c of the sample and hold circuit 3. In FIG. 5, reference numeral 8 denotes an operational amplifier forming a part of the sample-and-hold circuit 3 described above, and a signal c having a waveform shown in FIG. 7A appears at its output. A resistor 23, a capacitor 24, an operational amplifier 22, and an FET 25 connected to the output of the operational amplifier 8 form a clamp circuit 10.
FET 25 is operating as an electronic switch. The purpose of this clamp circuit 10 is to make the FET 25 conductive (
0N), the output of the operational amplifier 22 maintains the ground potential, and when the FET 25 becomes non-conductive (0FF), the DC component is blocked by the capacitor 24, and the output signal c of the operational amplifier 8 is kept at the ground potential by the FET 25. The purpose is to extract only the voltage change from the time when the voltage reaches 0FF'5 to the output of the operational amplifier 22. Here, the control voltage applied to the gate electrode of the FET 25 is applied to the resistors 26 and 28 with respect to the noise detection signal b.
and a capacitor 27, and the waveform of the signal h is as shown in FIG. 7C. Therefore, the FET 25 becomes "0FF" only for a short period before and after the discontinuous portion x of the output signal c, and the output of the operational amplifier 22 has a ground potential as shown in the output signal i shown in FIG. With reference to , only the voltage change and a part of the signal at the discontinuous portion x of waveform c are extracted.Next, the output of the operational amplifier 22 is connected to the FET 29 that constitutes the electronic switch 12. ,F
The ET 29 is controlled by an output signal j (FIG. 7(e)) of a differentiating circuit 13 consisting of a resistor 31 and a capacitor 30. A negative voltage is applied to one end A of the resistor 31, and the FET 29 is normally
maintains the state of "0FF". Next, when a negative pulse of the noise detection signal b is generated, the output signal 1 is applied to the gate electrode of the FET 29, and the FET 29 outputs 0N only at the time when the negative pulse of the noise detection signal b disappears and immediately after that.
It will be done. This also corresponds to the discontinuity X in the output signal c
And also right after that. Due to this switching operation of the FET 29, a voltage corresponding to the voltage change at the discontinuous portion x of the output signal c is applied from the operational amplifier 22 to the capacitor 14. The output impedance of the operational amplifier 22 is considered to be sufficiently low, and the capacitor 14 is charged to a voltage approximately equal to the voltage change of the discontinuity x during the "ON" period of the FET 29. A resistor 15 is a discharge resistor for the electric charge stored in the capacitor 14, and in FIG.
4. Also serves as a part of the adder circuit consisting of resistors 15, 35, and 36. Ru. As a result, the peak voltage E of the terminal voltage of the capacitor 14 is approximately equal to the voltage change at the discontinuous portion X of the output signal c, and Le=E{1-Exp(7-)} (where R: resistance value
value (Ω), C: value of capacitor 14 [F], t: FE
Elapsed time since returning to T29゛0FF゛'' (S
A waveform f as shown in FIG. 7C is obtained, which attenuates according to the equation (EC).

By adding the correction signal f obtained as described above and the output signal e of the 4-phase shift circuit in the adder circuit 16, the output of the operational amplifier 34 is as shown in FIG. An output signal g with reduced distortion components is obtained.

In the above embodiment, the noise detection circuit 1 detects the audio signal, but in the radio receiver,
Noise detection may be performed from a high frequency signal or an intermediate frequency signal modulated by the audio signal.

In addition, when noise detection is performed using a high frequency signal or an intermediate frequency signal in a radio receiver, a high frequency filter, an intermediate frequency filter, etc. are included in the signal and noise path from the noise detection part to the noise removal circuit. , these cause delays in signals and noise, so a separate delay circuit 2 may not be necessary. In addition, clamp circuit 1
0, the control voltage of the electronic switch 12 is in this embodiment:
Integrating circuit 11 and differentiating circuit 1 using resistors and capacitors
3, however, other circuit means may be used, such as a monostable multipipulator circuit, which ultimately performs the same function. As described above, according to the present invention, it is possible to greatly reduce the secondary distortion caused by the sample and hold circuit used as the noise removal circuit, and it is possible to significantly improve the noise removal effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional noise removal circuit, Fig. 2 is a wiring diagram of a configuration example of the sample and hold circuit, Fig. 3 is a waveform diagram of each part in the conventional example, and Fig. 4 is an embodiment of the present invention. A block diagram showing an example, FIG. 5 is a wiring diagram of a configuration example of an embodiment of the present invention, and FIGS. 6, 7, and 9 are waveform diagrams of various parts of an embodiment of the present invention. Figure 8 shows the phase shift circuit 9
FIG. In the figure, 1 is a noise detection circuit, 3 is a sample and hold circuit, 9 is a phase shift circuit, 10 is a clamp circuit, 12 is an electronic switch, 14 is a capacitor, 15 is a resistor, 16 is an adder circuit, and 37 is a correction signal generator. It is a circuit.

Claims (1)

[Scope of Claims] 1. A noise detection circuit that detects a noise component contained in an input signal and outputs a noise detection signal while the noise component continues; A delay circuit that delays the time corresponding to the time delay, and an output signal of a hold circuit that holds the level of the delayed input signal at the level when the noise detection signal was input while the noise detection signal is input. A phase shift circuit that shifts the phase closer to 180° as the frequency increases;
a correction signal generation circuit that generates a correction signal having the same phase and opposite polarity as the discontinuity formed in the input signal that has passed through the phase shift circuit from the output signal of the sample hold circuit and the noise detection signal; and the phase shift circuit. A noise removal circuit including an addition circuit that adds the output signal of the circuit and the correction signal. 2. The correction signal generation circuit is controlled by the noise detection signal so that the output signal of the sample and hold circuit passes through only the period including the discontinuous portion formed by the sample and hold, and the other period is kept at a substantially constant value. A patent claim consisting of a clamp circuit, a switch that allows the output signal of the clamp circuit to pass only during a period including the discontinuous portion of the sample-and-hold circuit, and a shaping circuit that includes a capacitor that is charged by the output signal of the switch. The noise removal circuit according to item 1.