JPS5947264B2 - Test pattern copying device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test pattern copying device for writing an application pattern and an expected pattern into a pattern memory for testing a logic circuit device, a memory device, etc. configured as a semiconductor integrated circuit.

To test a semiconductor integrated circuit device such as a logic circuit or memory, an application pattern is supplied to the device, and it is checked whether the output pattern matches an expected pattern. For this test, a test pattern is prepared in advance that is a combination of the applied pattern and the expected pattern, and the test is conducted using that test pattern. In other words, the application pattern and the expected value pattern are stored in the pattern memory 11, but first, the application pattern prepared in advance is transferred to this pattern memory 11, and the pattern memory 11 is sequentially outputted to the format control section. supply to 12;
Here, the predetermined levels, waveforms, etc. are changed, and the device under test 13 is the same as the device under test but is correct and has no failures.
supply to. The output from the device under test 13 is sampled by the sampling section 14, and the output is written as an expected pattern in the pattern memory 11 at the same location as the previously applied pattern via the buffer memory 15. Each terminal pin of the device under test 13 may serve as an input pin or an output pin, and its state differs depending on the application pattern. Conventionally, sampling section 1
All the bits output from the sampling section 14 obtained in step 4 were written into the pattern memory 11 through the buffer memory 15. Therefore, the application pattern corresponding to the written expected pattern is erased. Therefore, after writing the expected pattern corresponding to each application pattern, the application patterns prepared in advance are sequentially written into the pattern memory 11 again, and only the application pattern and the corresponding expected pattern are written in the pattern memo January 1. I got a better test pattern. The pattern memory 11 containing the application pattern and expected pattern thus obtained is read out, and the application pattern is given to the device under test, and its output is compared with the expected pattern at that time to determine whether or not it is a good product. .
As mentioned above, in the conventional test pattern copying device, all the bits of the sampling section are written to the pattern memory 11, so the applied pattern is destroyed, and after storing the expected pattern, the applied pattern is written again to the pattern memory 11. I needed to write.

An object of the present invention is to provide a test pattern copying device that can write an expected pattern into a pattern memory without erasing the applied pattern at the time, thereby shortening the time required to obtain a test pattern, that is, the time required for copying. be.

According to this invention, data specifying whether each input/output pin of the device under test at that time is an input pin or an output pin is stored in advance in an output pin designation memory in accordance with the application pattern, and When a pattern is read out, the address where output pin designation data corresponding to the pattern is stored is stored in an address memory, and when the application pattern is read out, the address data is also read out at the same time, and the output pin designation memory is read out using the address data.

The multiplexer is controlled by this output pin designation data to select bits on the application pattern side for those corresponding to the input pin at that time, and to take out the output of the sampling section for bits corresponding to the output pin. As a result, an applied pattern and a corresponding expected pattern are obtained from the multiplexer, that is, a test pattern is obtained, and this is stored in the pattern memory via the buffer memory. For example, in FIG. 2, parts corresponding to those in FIG. Output pin designation data that designates whether the output pin is an output pin is stored in the output pin designation memory 16. In other words, each bit in one word of the memory 16 corresponds to each pin of the device under test 13, and the output pin designation data is such that, for example, if it is O, it designates the input pin, if it is 1, it designates the output pin, etc. It is stored for each word. In addition, the output pin designation memory 16 corresponds to the application pattern read out from the pattern memory 11.
Address data indicating which output pin designation data is to be read out is stored in the address memory 17.

The same address is read out from the address memory 17 at the same time as the pattern memory 11 is read out, and this read address data is given as an address to the output pin designation memory 16, and the output pin designation data is read out and is controlled by the multiplexer 18. given as a signal. The multiplexer 18 is supplied with the application pattern from the pattern memory 11 and the sampling output from the sampling section 14, and corresponds to each bit of the output pin designation data when it designates an input pin. Outputs the bits of the applied pattern, and if an output pin is specified, outputs the corresponding bits of the sampling output.

Therefore, the output of the multiplexer 18 becomes a test pattern in which the applied pattern and its expected pattern are combined, and this is stored in the buffer memory 15 and then stored at the corresponding address in the pattern memory 11. 1 with the same pin
In the case of a so-called input/output pin that performs input/output during a cycle, the output of data read from the output pin designation memory 16 is also controlled so that the output pin designation data becomes 1 only at the timing of output. Even if the pin functions only as an output pin, it does not output in every cycle, but only in a specific cycle, and the output pin designation data is created so as to specify the output only in that cycle. As described above, according to the test pattern copying apparatus according to the present invention, when the application pattern from the pattern memory 11 is applied to the device under test 13, the application pattern at that time and the output of the device under test are output for each bit. One of them is selected according to the pin designation data, and the test pattern is obtained all at once. Since this is stored in the pattern memory 11, all the application patterns are sequentially applied to the non-defective device under test 13, and when it is completed, the test pattern is automatically A test pattern including an applied pattern and an expected pattern is obtained. Therefore, there is no need to read in the applied pattern again after the expected pattern is obtained, and copying can be performed in a short time. Generally, the output pin designation data does not necessarily differ even if the application pattern differs, so the depth of the output pin designation data is short compared to the depth (number of addresses) of the application pattern, and the capacity of the output pin designation data memory 11 is relatively small. A small one will suffice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional test pattern copying apparatus, and FIG. 2 is a block diagram showing an example of a test pattern copying apparatus according to the present invention. 11: Pattern memory, 12: Formats control section, 13
: device under test, 14: sampling section, 15: buffer memory, 16: output pin designation memory, IT: address memory, 18: multiplexer.

Claims (1)

[Claims] 1 A pattern memory that stores application patterns and expected patterns, an output pin designation memory that stores output pin designation data that designates whether the pin is an input pin or an output pin, and a memory corresponding to each application pattern in the pattern memory. An address memory that stores address data indicating which output pin designation data of the output pin designation memory is used, and an application pattern from the pattern memory to the IC under test.
a sampling section that samples the output of the IC under test; and selection of the application pattern from the pattern memory and the output of the sampling section based on the output pin designation data from the output pin designation memory. 1. A test pattern copying device comprising a multiplexer that performs the following operations, and a buffer memory that temporarily stores the output of the multiplexer and writes it into the pattern memory.