JPS594732B2 - Bus control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system bus control system used in a system using a microcomputer, and more particularly to a system for determining the right to use the bus.

In systems using microcomputers,
A system-common bus interface is often used to connect memory and various I/Os.

Normally, this bus interface is wired to the back panel, adapters for connecting the CPU, memory, and various I/Os are mounted on the printed circuit board, and these various printed circuit boards are mounted on the back panel. He often talks about various microcomputer systems. A parallel arbitration method and a serial arbitration method are known as methods for arbitrating bus usage rights in this type of microcomputer system.

FIG. 1 shows a parallel arbitration method in the prior art, and FIG. 2 shows a serial arbitration method. In both Figures 1 and 2, 1 is a bus usage right arbitration circuit, and 2 is an adapter A connected to the bus.
Similarly, 3 indicates adapter B, and 4 indicates adapter C. Bus signals other than those shown in the figure are also connected to the adapters 2, 3, and 4, but these are omitted because they are not relevant to the following explanation. First, the parallel arbitration method shown in FIG. 1 will be explained.

In Figure 1, REQ0, REQ(B), REQ(
C) is a bus use request signal sent from adapters 2, 3, and 4. Also, ACK (A), ACK (B), AC
K(C) is a bus use permission signal outputted from the bus use right arbitration circuit 1 to each adapter. The bus usage right arbitration circuit 1 receives REQ signals from each adapter 2, 3, and 4 in parallel, and if two or more adapters send bus usage requests almost simultaneously, the An ACK, which is a bus use permission signal, is sent to the adapter with the determined highest priority, and the adapter with the highest priority is allowed to use the bus. The adapter with a lower priority is made to wait until the adapter with a higher priority finishes using the bus, and when the adapter finishes using the bus, the bus usage right arbitration circuit 1 awards the usage right again, and as a result, when it receives a usage permission signal, , can use the bus for the first time. The bus usage priority order at this time is determined by the bus usage right arbitration circuit 1. That is,
REQ. A. The B, CLACKA, B, and C signals are determined by which priority of the bus right arbitration circuit 1 they are connected to. The advantages of this parallel arbitration system are that the bus right arbitration circuit 1 makes arbitration in parallel, so it can be arbitrated at high speed; the mounting position of the adapter can be set regardless of the priority order; This means that you can keep an adapter that has one available as a spare for expansion, and there will be no problem even if it is not present in the first place. Next, the serial arbitration method shown in FIG. 2 will be explained.

In FIG. 2, the REQ signal is a bus use request signal sent by each adapter 2, 3, and 4. This signal is a wired-OR bus request signal sent from each adapter, and when any adapter turns on the REQ signal line, the bus usage right arbitration circuit 1 determines whether one or more adapters You can know that you are requesting to use the bus. The ACK signal is a signal sent by the bus right arbitration circuit 1 as a bus use permission signal, and this ACK signal is input to the adapter A that is closest to the mounting position. ACK
(5), ACK (B), and ACK (C) signals are bus use permission signals sent by each adapter, and are signals transmitted through each adapter in series.
When each adapter receives an ACK signal, which is a bus use permission signal, if it is not sending out a bus use request signal REQ, it sends the ACK signal as it is to the next adapter, and the signal is transmitted in an orderly manner. When the adapter that is sending the REQ signal receives the ACK signal, it gains the right to use the bus and does not transmit the ACK signal to the next adapter. In this way, REQ from multiple adapters at the same time
When the signal is sent, the adapter closest to the bus right arbitration circuit 1 will get the right to use the bus. That is,
Regarding the bus usage priority, the one closest to the bus usage right arbitration circuit 1 has the highest priority, and the priority decreases toward the end. The advantage of this method is that since the ACK signal lines are simply connected in series, there is no limit to the number of adapters that can be added. As described above, both the parallel arbitration method and the serial arbitration method have their advantages, but on the other hand, both methods have the following problems.

First, there is a parallel arbitration method. In this method, when the number of adapters increases, one bus use request signal REQ and one bus use permission signal ACK are required for each adapter, so the bus use right arbitration circuit is used. The number of signals to be output is 2n, where n is the maximum number of adapters connected to the system bus.

In the example shown in Figure 1, there are three adapters, so the number of signals is six, but if the number of adapters increases, the number of signal pins of the bus right arbitration circuit 1 will increase, and priority will be assigned in parallel. The number of circuit components for arbitration also increases, making it impractical. For example, the maximum number of adapters etc. is 8 to 16.
If the number is small, it will not be much of a problem, but 6
When the number is about 4 to 255, it becomes impractical. Therefore, a parallel arbitration method cannot be used in such a large bus with the maximum system configuration. Recent improvements in the performance of microcontrollers have been remarkable, and it is desirable to be able to connect a large number of adapters as a general-purpose system bus. However, parallel arbitration is not used in such systems; There are many cases where the serial arbitration method shown in Figure 2 is adopted. However, the problem with the series arbitration method is that if there is no adapter in the middle of the series connection, the ACK signal will not be transmitted, and the priority of the right to use the bus will be lower towards the end of the series connection.

For this reason, in the system configuration, the adapters must be lined up in order of priority without empty space, and spare space for expansion must be prepared at the end of the bus. Therefore, if there is an adapter that you want to add to the bus later, it will be connected to the end of the series connection and will have the lowest priority for bus use. However, the priority of bus use is determined by the balance of the entire system, such as the bus usage rate of the adapter and the time allowed until the right to use the bus is obtained. It is not always good to have the lowest priority. If you want to increase the priority of the adapter you want to add, you must cut off the serial connection of the ACK signal midway through the addition, and then shift the adapters one by one. However, it is often difficult to move and reinstall existing adapters each time an expansion is needed because of the individual wiring output from the existing adapter and the individual wiring routed to the back panel. In this way, both the parallel arbitration method and the serial arbitration method have advantages and disadvantages.

For this reason, some multi-bus systems have been announced that can employ either a parallel arbitration method or a serial arbitration method, but the choice of which method to use is determined at the time of system design. It is a method that is fixed, and once it is decided, its advantages and disadvantages will be either parallel arbitration method or serial arbitration method. The purpose of the present invention is to eliminate the above-mentioned problems, without increasing the number of signal pins or arbitrating circuits when the maximum number of connected packages is large in the parallel system, and without increasing the number of signal pins or arbitrating circuits as in the case of the serial arbitrating system. To provide a bus control method that prevents a portion from having the lowest bus usage right.

To achieve the above object, the present invention installs a plurality of bus use request signal lines in parallel, and sets different priority levels to each signal line. Each adapter is arbitrarily connected to one of these bus use request signal lines, and an adapter attempting to obtain the right to use the bus connects the bus use request signal line corresponding to the priority level to which it is connected. Turn on. On the other hand, the bus use right arbitration circuit monitors each bus use request signal line, selects the one with the highest priority level from among the bus use request signal lines that are turned on, and uses that level as the bus use permission signal. Send. This bus permission signal is
This is valid only for the adapter corresponding to the priority level among the adapters issuing the bus use request.
The adapters are also connected in series by a priority determination signal line, and the priority determination signal is used to directly connect adapters that have not issued a bus use request and adapters that have issued a bus use permission signal that is not valid. Finally, among the adapters for which permission to use the bus is valid, the adapter to which the priority determination signal arrives first gains the right to use the bus. below,
The contents of the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 3 is a block diagram of an embodiment of the bus control method according to the present invention, in which 1 is a bus right arbitration circuit, 2 is an adapter A, and 3 is a block diagram of an embodiment of the bus control system according to the present invention.
Adapter Bl4 indicates adapter C.

REQO~3 are bus use request signals for each adapter, REQO has the highest priority level, REQl,
The priority level of REQ3 decreases in the order of REQ2, and the priority level of REQ3 is 1.
Assume that it is set to the lowest setting. Also, as shown in FIG. 3, adapter 2 has a REQO line, and adapter 3 has a REQ line.
It is assumed that the Ql line and the REQO line are connected to the adapter 4 again, and REQ2 is not used. In addition, R
EQ3 is a signal with special meaning, which will be described later. ACKO, ACKl and ACKSTB are bus use permission signals from which the bus use right arbitration circuit 1 grants permission to use the bus. Among these, ACKO,l is a signal that informs the priority level to be permitted; ACKO indicates priority level 2, and ACKl indicates priority level 21. That is, when both ACKO and l are on, the priority level is 3, which indicates the priority level corresponding to REQ3. Similarly, when both ACKO and l are off, it corresponds to priority level 0, that is, REQO, and ACK
When O is on and ACKl is off, priority level 1, A
When CKO is off and ACKl is on, priority level 2 is indicated. ACKSTB is ACKO,l
This is a timing signal for identifying. ACKO,l
has meaning only when this ACKSTB signal is on, and has no meaning when it is off. ACKRET is a signal for receiving the right to use the bus, and the adapter that has been granted permission to use the bus receives ACKO,
This is a signal sent to indicate that ACKSTB and ACKSTB have been received. BUSY is a bus-in-use signal, which is sent by the adapter currently using the bus. PR
N is a priority determination input signal, PRO is a priority output signal,
Both are signals for conveying bus priority, and the priority output signal PRO of the previous stage is serially propagated one after another as the priority determination input signal of the next stage. In addition, adapter (A) 2
The priority determination input signal PRN is grounded. Third
The movement of the diagram is as follows. An adapter attempting to obtain the right to use the bus sends bus use request signals REQO to REQ3.
Turn on the signal that corresponds to your priority level. Once this bus use request signal is turned on, it remains on until the user is allowed to use the bus. The bus use right arbitration circuit 1 uses a bus use request signal REQO~
REQ3 is monitored, and the level with the highest priority among the turned-on bus use request signals is specified by the bus use permission signal ACKO,l, and at the same time, the ACKSTB signal is sent out. The adapter that receives the bus use permission signal uses its own bus control circuit to determine whether or not the bus use permission signal is at a level corresponding to the bus use request signal sent by itself. If the adapter does not send out a bus use request signal, it passes the PRN signal, which is a priority determination signal for serial connection, as it is to the next adapter as a PRO signal. If you receive a bus permission signal with a level corresponding to the bus request signal you sent, fix the PRO signal to OFF and wait for the PRN signal to turn on. BUS is sent to the bus right arbitration circuit 1 to notify that the right to use the bus has been obtained.
After the Y signal turns off, the ACKRET signal is turned on to notify. Once the bus arbitration circuit 1 makes a priority arbitration and sends out a bus use permission signal, the bus arbitration circuit 1 processes the bus from the device that has obtained the right to use until it is notified of this by the CACKRET signal.
The next priority award will not be made.

In addition, once the adapter etc. starts to pass the priority determination signal of the series connection (sending the PRN signal as it is as the PRO signal) because it does not issue its own bus use request signal, it then issues its own bus use request signal. Even if the signal is turned on and the bus grant signal is at a level corresponding to the bus request signal, the P
Without checking the level of the RN signal, it must be passed as is to the next adapter etc. as a PRO signal.
This PRN signal is passed as a PRO signal by ACKST, which is a strobe signal among the bus use permission signals.
Only when the B signal is on. The adapter or the like that has obtained the right to use the bus notifies the bus right arbitration circuit 1 of this fact by means of an ACKRET signal. At this time, those who have obtained the right to use the bus can use the bus immediately if it is not in use, but if it is in use, they can use it as soon as it becomes vacant. Therefore, when the BUSY signal is on, even if the PRN signal turns on and you get the right to use the bus, you do not immediately send the ACKRET signal.
After confirming that the BUSY signal is turned off, turn on the AC
Turn on the KRET signal, and at this time also turn on the BUSY signal. By doing this, only one person can preemptively obtain the right to use the bus while the bus is in use.
FIG. 4 is a time chart when the adapter (B) 3 turns on the REQl signal and, at the same time, the adapter (C) 4 turns on the REQO signal.

Although the CLOCK signal in FIG. 4 has not been mentioned in the explanation so far, it is a clock signal that indicates the reference time for sampling each signal. In Figure 4, R
EQl and REQO are output from adapters 3 and 4 at the same time, but the bus right arbitration circuit 1 outputs permission signals for REQO, which has a higher priority, as ACKO and ACKl.
and send it as a code signal. Adapter 2 has the highest priority in the series connection priority determination signal, and its PR
The N(A) signal is always on, but the ACKSTB
Since the bus use request signal has not been sent at the time of receiving the signal, the PR is not sent while the ACKSTB signal is on.
Send the N(A) signal as it is to adapter B as the PRO(4) signal. Adapter 3 receives the bus use permission signal at a level that does not correspond to the bus use request signal it sent, so while the ACKSTB signal is on, it directly uses the PRN(B) signal as the PRO(B) signal. Send to adapter 4. When adapter C receives the bus use permission signal and confirms that the level corresponds to the bus use request signal it sent, it passes the PRN (C) signal as the PRO (C) signal even if it receives the ACKSTB signal. Instead, it monitors the PRN (C) signal, and after the signal propagation delay of adapters 2 and 3, when the PRN (C) signal turns on, it obtains the right to use the bus and confirms that the BUSY signal is off. After confirming, turn off the REQO signal you sent, send the ACKRET signal, turn on the BUSY signal, and start using the bus. By the ACKRET signal,
Bus usage right arbitration circuit 1 performs the next priority determination, and adapter 3 receives the bus usage right this time. However, since this is preemption control, adapter 3 receives the BUSY signal after adapter 4 has finished using the bus. The bus can only be used once it is turned off. FIG. 5 shows a specific example of the configuration of the bus right arbitration circuit, and FIG. 6 shows a specific example of the configuration of the bus control circuit placed in each adapter. Although the MRST signal has not been mentioned in the explanation so far, it is a reset signal for initializing the circuit state and is not directly related to the operation of the present invention. For convenience, it is assumed that FIG. 6 is a bus control circuit within the adapter 4 of FIG. 3.
Further, in both FIGS. 5 and 6, explanations of parts not directly related to the present invention will be omitted. In Figure 6, switch SWO
, l, 2 are switches for setting the REQ level for that adapter.

Since the REQ level of the adapter 4 is assumed to be "0" in this embodiment, the switch SWO is 0FF1 switch SW.
l,2 are supposed to be set to 0N. As a result, REQl,2 will no longer be output. When adapter 4 wishes to obtain the right to use the bus, a BUSREQ signal is applied from a circuit within the adapter to this bus control circuit. This BUSREQ signal is the flip-flop F
It is synchronized and set to 1 by the CLOCK-P signal. REQ- which is the set output of flip-flop F1
The 1P signal becomes the REQO signal through the gate circuit G1 and is sent to the bus. This signal is an open collector signal and is wired-ORed on the bus. At this time,
The REQ3 signal is also sent onto the bus through gate circuit G2. This puts the REQ3 at the lowest level on the bus,
By everyone who wants to obtain the right to use the bus,
This is so that the bus usage right arbitration circuit can easily know that there is someone requesting the use of the bus. That is, the REQ3 signal is used together with the common bus request signal. In other words, in this embodiment, once a device has secured the right to use the bus, it can hold the bus indefinitely by issuing the BUSY signal without stopping, so data can be transferred in burst mode. . In such a case, by using REQ3 as a common bus request, the BUSY signal is sent out to the one holding the bus without a brim.
You can let them know that there are other people who want bus rights. With this, it is also possible to cancel the burst mode. The REQO signal output from the adapter 4 is input to the bus right arbitration circuit shown in FIG.

This REQO signal is latched together with other REQ signals in the latch registers FlOl-FlO4 of FIG. 5 in synchronization with the CLOCK signal. This latched FlO
The signals from l to FlO4 are the priority encoder Gl.
It is input to Ol. Priority encoder GlO
l encodes the outputs of FlOl to FlO4 according to their priorities, and outputs the code as a combination of ACKO and ACKl. For example, if REQl is issued from adapter 3 at the same time as REQO from adapter 4, FlO4, FlO3, and FlOl (R as a common bus request)
EQ3 is also output) is set, but Fl
Since O4 is connected to the highest priority pin of GlOl's priority encoder, both GlOl's outputs ACKl and ACKO are low level, and REQ
A bus signal enable signal "00°" corresponding to 0 is generated.
At this time, the priority encoder GlOl generates an ANYREQ signal, and this signal is synchronized with the CLOCK signal by the flip-flop FlO5, and the AC
A KSTB signal is generated. These ACKO, I and ACKSTB signals are inputted again to the bus control circuit of FIG. 6 through the bus.

Referring again to FIG. 6, ACKO,l is the comparator circuit G3
is input. This comparison circuit G3 has its A side input and B
When the side inputs match, an A-B match signal is output. REQ connected to the A side input of comparison circuit G3
The OP and REQl-P signals are both high due to the settings of switches SWO,l,2. In addition, comparison circuit G3
ACKO,l is connected to the B side of , and in this case, high is also input to both of them. Furthermore, flip-flop F
1 outputs the REQ-1P signal, and A of the comparator circuit G3
A high level is also input to the =B (IN) pin. Therefore, the comparison conditions in the comparator circuit G3 are met, and a match signal is output to the AB output pin. This match signal is latched into flip-flop F2 by the ACKSTB signal. The set output of this flip-flop F2 is the gate circuit G4, G
5, the AND condition of the ACKSTB signal and the PRN signal, which is a series-connected priority determination signal, is taken one after another. The output of gate circuit G5 is input to gate circuit G6. Gate circuit G6 gates the output of gate circuit G5 while there is a BUSY signal on the bus, but when the BUSY signal disappears, it inputs the output of gate circuit G5 to flip-flop F3. Flip-flop F3 is set in synchronization with CLOCK by the output of G6, and the output of flip-flop F3 is output to the bus as an ACKRET signal through gate circuits G6 and G7. This ACKRET signal is again the fifth
It is input to the bus right arbitration circuit shown in the figure. In FIG. 5, the Aα signal is input to flip-flop F106, which is set in synchronization with CLOCK. The output of flip-flop FlO6 is input to the reset input of flip-flop FlO5, and flip-flop FlO5 is reset. As a result, A
The CKSTB signal disappears, and the right to use the bus goes to the adapter (C
) was given to 4. On the other hand, in the bus control circuit shown in FIG.
While sending out the CKRET signal, the flip-flop F4
is set in synchronization with CLOCK, and a BUSY signal is placed on the bus.
A signal is output through gate circuit G8 to secure the right to use the bus. Further, the output of flip-flop F4 becomes a BUSACK signal through gate circuit G9. This BUS
The ACK signal is sent by the BUSREQ signal to the circuit within the adapter C that has requested the bus control circuit to take the bus right. The circuit within the adapter that receives this signal starts using the bus from then on. Next, in the bus control circuit shown in FIG. 6, a case in which the user does not take ownership of the bus will be explained. In FIG. 6, if the REQ signal is not sent out by the comparison circuit G3, or if the ACKO,l signal is different from the REQ level sent out by the comparison circuit G3, no matching signal is output. Therefore, flip-flop F2 is not set and the output of gate circuit GlO becomes valid, indicating that the bus use permission signals ACKO,l and ACKSTB do not designate their own bus control circuit. The gate circuit Gll passes the PRN signal, which is a priority determination signal of series connection, as it is when there is a signal from the gate circuit GlO, and transmits it to the next stage as a PRO signal. If flip-flop F2 is set, it means that it has been given the right to use the bus, so the output of gate circuit GlO remains high, and PRN
The signal does not pass through the gate circuit Gll, and the PRO signal is not output. Therefore, the priority determination signal is no longer transmitted to the next stage, and even if a plurality of parties are sending REQs of the same level, only one party can obtain the right to use the bus. As described above, in the embodiment of the present invention, there are four bus use request signals REQO to REQO3, but of course this can be any number. In addition, the bus use permission signal AC
KO and ACKl are weighted 2A and 21 corresponding to REQO~3, and are set to two, but when the REQ signal is increased, the ACK signal must also be increased. Also, AC
Although the number of signals is reduced by weighting as shown in 2 K signals, 21, it is also possible to use signal lines that correspond one-to-one to the REQ signal. In this case, ACKS
A method that does not use the TB signal is also possible. Furthermore, while the bus is in use, it is possible to preempt the right to use the bus using the BUSY signal, but if the BUSY signal is monitored by the bus right arbitration circuit, it is possible to use a system that does not preempt the right to use the bus. is also possible. As described above, according to the present invention, the right to use the bus is granted to the adapter with the higher request level for the right to use the bus in parallel connection even if it is the last adapter in the series connection order. As a result, the direct connection method of the conventional technology
The priority of the adapter connected after being the highest will no longer be the lowest. For example, in FIG. 3, assuming that adapters 2 and 3 are conventionally connected adapters and adapter 4 is an added adapter, adapter 4
adapter 3 even though it was connected to the end of the series connection.
If adapters 3 and 4 issue requests to use the bus at the same time, adapter 4 is given the right to use the bus. Further, according to the present invention, the possible number of additional adapters, which was a problem with the parallel connection method, can be arbitrarily increased by extending the series connection portion. As described above, according to the bus control method of the present invention, a large-scale system bus configuration can be easily realized, the number of signals does not increase significantly, and the priority is determined by giving high priority to the part to be added. It is possible to assign a ranking and realize a highly expandable system bus.

In the future, it is expected that microcomputers will become more sophisticated and the system configurations using them will become larger in scale, so the bus control method of this method will have a great effect.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams showing the conventional bus control system, and Figure 3 shows the conventional bus control system.
4 is a timing diagram for explaining the operation of FIG. 3, and FIG. 5 is a specific circuit diagram of the bus right arbitration circuit in FIG. 3. , 6th
This figure is a specific circuit diagram of the bus control circuit on the adapter side in FIG. 3. 1... Bus usage right arbitration circuit, 2, 3, 4...
...Adapter, REQO~3... Bus use request signal, ACKO, l, ACKSTB... Bus use permission signal, ACKRET... Bus use permission reception signal, BUSY. ...Bus busy signal, PR
N...Priority determination input signal, PRO...
-Priority determination output signal.

Claims (1)

[Claims] 1. In a bus control method that determines bus usage rights for multiple adapters commonly connected to a bus, multiple bus usage request lines, each with a different priority level, are provided in parallel to handle the bus usage request. The plurality of adapters are arbitrarily connected to the bus line, each adapter is connected in series with a priority determination signal line, and a bus use right arbitration circuit is connected to one end of the bus use request line. The usage right arbitration circuit monitors the bus usage request of the adapter through each bus usage request line, and when there is a bus usage request, it issues a bus usage permission signal indicating the request line with the highest priority level among the bus usage request lines. Each adapter sends a priority determination signal to the priority determination signal line if it is not issuing a bus use request, or if it is not at a level corresponding to the bus use permission signal even if it is issuing a bus use request. is passed to the next-stage adapter, and the adapter at the level corresponding to the bus use permission signal establishes the right to use the bus by taking in the priority determination signal, and stops sending the priority determination signal to the next-stage adapter. A bus control method featuring: