JPS594734B2 - Operation time generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operation time generation method, and particularly to an information processing apparatus, in which signals of a plurality of data channels are turned on or off for a predetermined time after inputting a start signal, and The present invention relates to an operation time generation method that causes each channel to transmit and receive signals for a predetermined period of time or to relay signals.

In an information processing apparatus having a plurality of data channels, it is often necessary to have each channel transmit and receive signals for a predetermined period of time, or conversely, to relay transmission and reception.

In such a case, conventionally, as shown in FIG.
The switches SWI to SWnf1 provided for each operation time generator circuit C and the time generators T1 to Tn provided for the operation time generation circuit C
fl is used to set the operation time for transmitting, receiving, or relaying the start signal P for each channel as a reference point.

Therefore, one time generator is required for each channel,
There is a problem in that the amount of hardware becomes larger and the mechanism becomes more complicated. In order to solve these problems, the present invention uses memory to generate separate operation time signals for each channel without having to install a time generator for each channel. An object of the present invention is to provide an operation time generation method that simplifies the operation time generation method, and for this purpose, the operation time generation method of the present invention allocates operation time data set for each of a plurality of channels to each channel. a reference time generator that generates a reference signal train of a predetermined unit period at the same time as the start signal; and a reference time generator that reads the operation time data of the first memory at the first reference signal and stores it at the same address. a second memory that reads time data from the second memory, performs subtraction of a predetermined value, and generates an overflow signal when the subtraction result becomes zero; a writing means for rewriting the subtracted time data of each channel to the same address in the second memory; and a writing means for decoding the address in the second memory and generating an output signal to the channel corresponding to the decoded address. and latching means for latching a channel in which the overflow signal from the arithmetic unit matches the output signal from the decoder, thereby simultaneously generating separate operation time signals for a plurality of channels. do.

An embodiment of the present invention will be described below with reference to FIGS. 2 to 4.

FIG. 2 shows the configuration of an embodiment of the present invention, and FIGS. 3 and 4 are time charts showing an explanation of its operation.

In the figure, 1 is a time setting device, 2 is an address switch, and 3 is a first
4 is a data switch, 5 is a second memory, 6 is an arithmetic unit, 7 is an address counter, 8 is a reference time generator, 9 is a decoder, and 10 is a latch circuit.

The operation shown in FIG. 2 will be explained together with the time charts shown in FIGS. 3 and 4.

Prior to the operation time generation operation, the time setter 1 sets in advance the predetermined operation time for channels CHl to CHn+, I and the write address assigned to channels CHl to CHn+, 3 (O to n1, that is, channel CHll is address O). , Channel CH2k is number 1,
. . . Address n is assigned to channel CHn+1) and written in the first memory 31.

Now, when the start signal P is applied to the address counter 7 and the reference time generator 8, the address counter 7 receives a clock signal from a clock source (not shown), and the reference signal S from the reference time generator 8 is applied. Each time, (n+1) equal to the number of channels, read addresses R1 for the first memory 31 and addresses for the second memory 5 are generated (FIGS. 3A and 3B).

Here, the period of the clock signal is set so that this (n+1) addresses can be generated during the period T of the reference signal S.
It is selected to be sufficiently smaller than the period T. First, when the first address O of the read address R1 for the first memory 3 is supplied to the first memory 3 via the address switch 2,
Time T.

Channel CH, operation time data (0D
0) is read from the first memory 3 and becomes the input data (0D0) of the second memory 4 via the data switch 4,
The second memory 41 is written (Fig. 3B, c7eyh)
0, then time T at the same address O.

2, the read address R for the second memory 5
2 is supplied to the second memory 5, the above-mentioned written data (0D0) is read out and supplied to the arithmetic unit 6 (FIG. 3d).
).

The arithmetic unit 6 is a (-1) subtracter, and calculates data (0D0) obtained by subtracting 1 from the input operation time data (0D0).
-1) (Fig. 3 f). This output data (0D
0-1) is time T. 3, the second memory 5t is rewritten to address O via the data switch 4 by the write pulse W2.

Note that 1 subtracted from the calculator 6t corresponds to the unit time when setting the operation time. When the address O ends in this way, the data at address O in the first memory 3 remains as is (0D0), and the data at address O in the second memory 5 becomes (0D0-1) (second Figure C, h). The second memory 51 is supplied with the read address R2 and write pulse W2 as described above, but the third memory 51 is supplied with the read address R2 and the write pulse W2 as described above.
In the figure, they are collectively shown as one address line. Similarly, during the period when the read address R1 is address 1, the channel CH stored in the first memory 3t is
The operation time data (0D1) of 2 is transferred to the second memory 5, then read out, subtracted by the arithmetic unit 6 to (0D1-1), and rewritten to address 1 of the second memory 5. Then, at the final read address n, the operation time data (0Dn
)1 data (0Dn-1) is written. Therefore, the first of the reference signals S generated by the start signal P
When the third cycle T ends, the operation data (
0D0) to (0Dn) are stored as they are, and addresses 0 to n of the second memory 5 are channel CH1.
1 is subtracted from the operation time data of the first memory 3 as new time data of CHn+, respectively (0D
0-1) to (0Dn-1) will be set. Next, when the second period of the reference signal exceeds 1, the first memory 3 is separated from the second memory 5 by the data switch 4, so the operation time of channels CH1 to CHn+1 is stored at addresses O to n of the first memory 3. Data (0D0) to (0Dn
) is memorized as is. On the other hand, addresses 0 to n of the second memory 5 are stored as new time data of channels CHl to CHn+1 (0D0-1) to (0Dn-
The time data (0D0-2) to (0Dn-2) obtained by subtracting 1 from the calculation unit 61ζ from 1) are set via the data switch 4 (see Fig. 4 a to 9).
). Note that FIG. 4A shows the relationship between the start signal P1, the reference signal S, and the address of the second memory;
This is a detailed time chart of one second cycle of the reference signal S in Figure A. Similarly, the stored contents of the first memory 3 do not change due to the generation of the reference signal, and the operation time data (0D0
) to (0Dn) are kept as they are, but the time data of channels CHl to CHn+1 stored in the second memory 5 are subtracted by 1 from (0D0) to (0Dn) every time a reference signal is generated. It will decrease.

The current operation time interval of channel CH2 is the smallest value ′ζ
Assume that it has been set.

The time data stored at address 3 of channel CH2 of second memory 5 every time the reference signal S is generated is (
0D2-1), (0D2-2), (0D2-3)...
...(0D2-1), ......(3), (2),
It decreases to (1) and finally becomes (0). Then, when the next reference signal is generated and the address is applied to the second memory 5, the output of the arithmetic unit 6 becomes O-11, generates an overflow signal at time TF, and supplies it to the latch circuit 10. Figure 4, mouth, m). The latch circuit 10 has internal flip-flops corresponding to channels CH1 to CHn+, all of which are in the set state from the first start signal Pt.

These flip-flops are individually applied with address signals corresponding to each decoded channel by the decoder 9f, and an overflow signal F from the arithmetic unit 6 is applied in common, so that the address signal and the overflow signal are applied simultaneously. The flip-flop is configured to be set. Therefore, an overflow signal F is first generated for channel CH2', and when address 1 for channel CH2 is decoded by decoder 9 and applied to latch circuit 10, the flip-flop of channel CH2 is activated at time TF. is set (Figure 4, opening, R2).

The time interval from the generation of the start signal to time TF becomes the operation time set for channel CH2. Similarly, each time the time data of each channel of the second memory 5 reaches zero, the arithmetic unit 6 generates an overflow signal at the next address, and the latch circuit 10 resets the channel where the time data has reached zero. Set it up. In this way, the channels CHl to CHn+ of the latch circuit 10
11, a signal is generated which is in the set state for a respective set operating time.

Furthermore, by reversing the set and reset states, it is possible to generate a signal that is in the set state for the respective set operation time. As described above, according to the present invention, (1) separate operation time signals can be assigned to a plurality of channels at the same time with the configuration of one operation time generator.

(2) Since an operation time generator is not provided for each channel, the proportion of hardware is small, reliability is improved, and the cost is low.

(3) Since a memory is provided, the operation time only needs to be set once, making it ideal for continuous repeated operations.

It is possible to provide an operation time generation method with excellent effects such as the following.

[Brief explanation of drawings]

FIG. 1 shows a conventional operation time generating device, FIG. 2 shows the configuration of an embodiment of the present invention, and FIGS. 3 and 4 are time charts for explaining its operation. In the figure, 1 is a time setting device, 2 is an address switch, and 3 is a first
4 is a data switch, 5 is a second memory, 6 is an arithmetic unit, 7 is an address counter, 8 is a reference time generator, 9 is a decoder, and 10 is a latch circuit.

Claims (1)

[Claims] 1. A first memory that stores operation time data set for each of a plurality of channels in addresses assigned to each channel, a reference time generator that generates a reference signal sequence of a predetermined unit period simultaneously with a start signal, and a first a second memory that reads the operation time data of the first memory and stores it at the same address as the reference signal; and an operation that reads the time data of the second memory, subtracts a predetermined value, and generates an overflow signal when the subtraction result becomes zero. a writing means for rewriting the time data of each channel subtracted by the arithmetic unit each time the reference signal is generated to the same address in the second memory, and decoding the address in the second memory. By providing a decoder that generates an output signal on a channel corresponding to the decoded address, and a latch means that latches the channel in which the overflow signal from the arithmetic unit and the output signal from the decoder match,
An operation time generation method characterized by simultaneously generating separate operation time signals for multiple channels.