JPS5947389B2 - memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit using an insulated gate field effect transistor called an IC memory or MOS memory.

Integrated circuits using insulated gate field effect transistors are being developed into large-scale integrated circuits because they can be easily increased in density.

In particular, large-capacity memory integrated circuits have large-capacity memory cells on a common semiconductor substrate, and realize high-performance, highly reliable semiconductor devices. Therefore, a preferred memory cell is a one-transistor random access memory (ITR-R).
In this MOS memory, switching transistors and information storage capacitive elements are arranged at matrix intersections where word lines and digit lines intersect, as included in a MOS memory called AM. In this ITR-RAM, it is necessary to attach a highly sensitive sense circuit to the digit line in order to prevent the capacitance value of the capacitive element from increasing as the capacity increases. Conventional circuit technology couples the sense circuit and digit lines with transistors that operate in saturation. This circuit technology was also developed in 1975 by ISC Technical Digest Paperpers (75IS).
SCC Technical Digest Papers)
As described by Heller (L, G, Heller) et al. in "P, 112, a sensing operation is initiated by a signal to a sense node that is larger than the signal amplitude of the digit line.

However, in this conventional circuit technology, the precharge state of the digit line before the start of the sense operation governs the conditions at the start of the sense circuit operation, and this precharge operation is performed through the transistor in the saturated state, so both sides of the sense circuit It takes a long time to reach the equilibrium precharge obtained at the end of the precharge of the digit line, and the cycle time when performing the information read operation one after another is long, and if the cycle time is shortened, the sense node amplitude for reliable information read operation is reduced. There is a drawback that you will not be able to obtain

In other words, after the digit lines on both sides of the sense circuit have settled to high and low levels during the first read, etc., and before the potentials of the digit lines on both sides are aligned during precharging for the second read, this method is However, it takes an extremely long time and has the disadvantage of increasing cycle time. Similar drawbacks can be seen in MOS memories that do not use conventional saturated transistors as described above to connect the sense circuit and digit line, but instead use a simple gated flip-flop circuit as the sense amplifier.
This results in decreased sense sensitivity and increased cycle time. A first object of the present invention is to provide a memory circuit having a high-speed sensing circuit with high sensing sensitivity.

A second object of the present invention is to provide a memory circuit including a 1-transistor/cell type sense circuit that allows large changes in the input voltage to the sense circuit and can operate at high speed.

In the memory circuit of the present invention, memory cells are provided at the intersections of a matrix of rows and columns where a plurality of digit lines and a plurality of word lines intersect, and a potential difference generated between a first digit line and a second digit line is It is amplified and output to the first and second sense nodes. a sense circuit, first and second charging transistors charging the first and second sense nodes, and third and fourth transistors connected between the first digit line and a charging voltage source. a series circuit of transistors, a series circuit of fifth and sixth transistors connected between the second digit line and the charging voltage source, and a series circuit of fifth and sixth transistors connected between the first and second digit lines and the first and second digit lines; a second sense node, the third and fifth transistors are controlled by a charge control pulse, and the fourth transistor operates in response to the second node potential. However, the sixth transistor is configured to operate in response to the first node potential.

According to the present invention, the first and second nodes are charged by the first and second charging transistors connected to the first and second nodes during precharging, and the first and second nodes are charged by the first and second charging transistors connected to the first and second nodes. The digit line is also charged via the third and fifth transistors.

In particular, in this case, the low level digit line is driven by the high level sense node potential, and the J high level digit line is driven by the low level sense node potential, so both digit lines are at the same potential. The precharging time is extremely shortened, and high-speed operation is achieved. Next, embodiments of the present invention will be explained using the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This embodiment uses a plurality of word lines (Wd, W, . . .
) and multiple digit lines (D., [), ......)
A memory cell consisting of a transistor and a capacitive element is provided at each fulcrum of a matrix formed by a matrix. To simplify the explanation, only one word line, ie, address signal line W, one dummy address signal line Wd, and digit lines D, D, extending on both sides of the sense circuit 10 are shown in this figure. The dummy address signal line Wd is driven by a dummy address signal ψWd when reading information from a memory cell coupled to one digit line [)1, and transfers the information of the dummy cell coupled to the digit line D, to the other digit line D,
to communicate. That is, the memory cell transistor QM,
One of its drain and source is connected to the digital line D, and the other is coupled to one end of the capacitive element CM, and its gate electrode is driven by an address signal ^. Further, one of the drain and source of the dummy cell transistor Qbll is connected to the digit line D1, the other is connected to one end of the capacitive element Cd, and the gate electrode is driven by the dummy address signal 11)Wd. A precharge signal ψL is connected to the gate between the connection point of the transistor Qdll and the capacitor Cd and the reference power supply.
is applied to the transistor Q. . , which sets the capacitor Cd to the reference potential every precharge. Furthermore, coupling transistors QRn, QR, .
are provided respectively, and each transistor QRI is connected to the digit line D,,I)1 and the sense nodes A, B of the sense circuit 10.
Regions called the drain and source of I and QR2l are respectively coupled. A power supply is connected to the gate electrodes of transistors QRll and QR2l. are connected to each other. The sense circuit 10 has two precharge transistors QLll and QL2l whose drains are connected to the high power supply line VD and whose gates are connected to the precharge signal A.

The sources of each of these transistors are connected to a first sense node A and a second sense node B, respectively. First sense node A1 sense transistor Q. The drain of the transistor QD2l and the gate of the second sense 1 transistor QD2l are connected. Similarly, the second sense node B has a first sense transistor Q. 2l drain and first cent transistor Q.

2l gates are connected.

sense transistors QDll and Q; The sources of 2l are commonly coupled to the drain of the 1 drive transistor Q8l, and the gate of this transistor Q8l is connected to the sense signal ψ5.
By driving the voltage at the lower potential of the power source (GND).

As a result, the sense circuit 10 becomes active. Also,
Although not shown, a smoothing transistor whose gate is connected to the precharge signal line A is provided between nodes A and B, so that the potentials of the nodes A and B are balanced during precharging. , may be made to work.

All transistors here are N-channel insulated gate field effect transistors.

All transistors and capacitive elements constitute a memory circuit in an integrated circuit formed on the same semiconductor substrate, and a transistor QFll, which has an enhancement type gate threshold characteristic by applying a −2 base voltage to the substrate,
QF2l, QDll, QD2l, QRll, QR2l,
Qdll, Q, 2l, QMl, QUl have a reference gate threshold voltage of 1. Also, pre-charge transistor QLl
1, QL2l is a depressant with a reference gate threshold voltage of -2. It is a Yong type. In this example, the power supply is even higher.

It has two first-stage bit line precharge transistors Qllll and QT2l whose drains are connected to the precharge signal line A and whose gates are connected to the precharge signal line A. The source of this transistor is the second stage precharge transistor Qp.
It is connected to the drains of ll and Qp2l. The gate of the transistor Qpll is connected to the sense node B, and the source is connected to the digit line D1, and the gate of the transistor Qp2l is connected to the sense node A, and the source is connected to the digit line r). The operation of the circuit shown in FIG. 1 will be explained using the operating waveforms shown in FIG.

Consider a situation in which in the previous read operation, the potential Ua of the digit line D1, that is, the potential UA of the sense node A, was at a high level, and the potential Ub of the digit line 1)1, that is, the potential UB of the sense node B was at a low level.

At this time, precharge signal A becomes high level, and during that period (40 to 120 nsec), nodes A and B are at high power. More charged. At this time, since the charging transistors QLll and QL2l are of the depletion type, their current capacity is larger than that of the enhancement type.
Therefore, the node B at the low level is charged at a high speed, and an improvement in the charging speed is expected. However, it goes without saying that this charging transistor is not limited to the depletion type, and may also be of the enhancement type. Here, the digit line 1)1 at a low level is charged via the coupling transistor QR2l, but in addition to this, the digit line 1)1 is charged via a transistor Qp2l which operates in response to the potential of the node A at a high level. It is also charged from the charge transistor QT2l.

Therefore, as the potential UA of the node A rises, the potential Ub of the digit line [)1 is rapidly raised.
On the other hand, the digit line D1, which is at a high level, is charged through the coupling transistor QRll and is also charged through the transistor Qp2l, but the gate of this transistor Qpll is connected to the node B, which is at a low level.
Therefore, the potential Ua of the digit line D1 is raised as the potential UB of node 8B rises, but in this case, the potential Ua of the digit line D1 is already at a high level, so the potential Ua of the digit line D1 is maintained at this high level. Become. The above means that the digit lines Dl and [)1 rise in accordance with the potentials of the nodes B and A, so the equilibrium state of the potentials UA and UB of the nodes A and B is compared to the conventional one. , can be obtained extremely quickly.

Therefore, the read cycle time becomes extremely short and high-speed operation becomes possible. After the precharge period ends, the signal line A becomes low level, but the cut transistors are connected to the nodes A and B and the precharge transistors QLII, respectively.
QL2l, there will be no coupling between the parasitic capacitances of nodes A and B and the parasitic capacitances between the sources and gates of transistors QL,l, QL2, and therefore There is no change in potential at nodes A and B due to charge division.

Therefore, an improvement in sense sensitivity is achieved by this cut transistor. Of course, it is not necessary to provide this cut transistor. In this embodiment, the coupling transistors QRII and Ql2l, which connect the sense nodes A and B and the digit lines D, , [), respectively, are turned off in the saturated state, and therefore, compared to the conventional sense circuit, As a result, the sense sensitivity can be improved by about 5 times or more. FIG. 3 is a circuit diagram of a second embodiment of the invention.

This embodiment uses coupling transistors QR, , QR in the circuit of the first embodiment (FIG. 1).

1 is removed and the sense node is connected directly to the digit line. ．． Furthermore, in this embodiment, the precharge transistors QL, , Q,2, are of the enhancement type;
The precharge transistors QP, . . . , QP2l in the first stage are depletion type. In this example, the first
Since the sense node A of is connected to the gate of the transistor Qp2l which precharges the second digit line D1, and the second sense node B is connected to the gate of the transistor Qpll which precharges the first digit line D1. During pre-charging, the time required to align the low level and high level is significantly reduced, making it possible to shorten the cycle time. Further, since the precharge transistors Qpll and Qp2l are of the depletion type, the current capacity is larger than that of the enhancement type, resulting in a larger precharge ability.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an operation waveform diagram explaining the operation of the embodiment of FIG. 1, and FIG. 3 is a circuit diagram of a second embodiment. A, B...Sense node, Dla, l) 1b...
...digit line, QL,,,QL2l...
・Pre-charge transistor, QDII, QD2l゜゜゜゜゜゜゜゜Sense transistor, Qs2゜゜゜゜゜゜゜Drive transistor, QR,,,QR.

Claims (1)

[Claims] 1. A memory cell is provided at each intersection of a matrix where a plurality of digit lines and a plurality of word lines intersect,
a sense circuit that amplifies a potential difference generated between a first digit line and a second digit line and outputs the amplified potential difference to first and second sense nodes; and a sense circuit that charges the first and second sense nodes. a series circuit of first and second charging transistors, third and fourth transistors connected between the first digit line and a charging voltage source, and the second digit line and a charging voltage source; a series circuit of fifth and sixth transistors connected between a source and a coupling means for coupling the first and second sense nodes to the first and second digit lines, respectively; The third and fifth transistors are controlled by charging control pulses, the fourth transistor operates by receiving the potential from the second node, and the sixth transistor operates by receiving the potential from the first node. A memory circuit characterized in that it operates in response to an electric potential. 2. The coupling means includes a seventh transistor that connects the first node and the first digit line, and an eighth transistor that connects the second node and the second digit line. A memory circuit according to claim 1, characterized in that: