JPS5947466B2 - Manufacturing method of semiconductor device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a two-layer gate electrode structure including a lower electrode and an upper electrode.

TECHNICAL BACKGROUND OF THE INVENTION Conventionally, the following method has been employed to manufacture a semiconductor device having a two-layer gate electrode structure, such as a MOS type dynamic RAM.

First, as shown in FIG.
After forming a silicon oxide film 3 by oxidizing it in a dry oxygen atmosphere, polycrystalline silicon 4 is deposited on this silicon oxide film 3 as a first electrode material layer.

After introducing impurities into this polycrystalline silicon film 4 by a method such as phosphorous diffusion, a resist pattern formed by photolithography is provided, and the exposed polycrystalline silicon film 4 is selectively etched using this resist pattern as a mask. A first gate electrode 5 is formed. Furthermore, the exposed silicon oxide film 3 is etched using the first gate electrode 5 as a mask.

After forming the state shown in FIG. 1b in this way, the first
As shown in FIG. c, the insulating film T is formed by oxidation in a wet oxygen atmosphere. This insulating film 7 becomes a second gate oxide film and is also used as an insulating film between the first and second gate electrodes. Next, a polycrystalline silicon film is deposited as shown in FIG.
A gate electrode 8 is formed. Thereafter, an n+ layer is formed in the silicon substrate 1 according to a well-known manufacturing method, and aluminum wiring is provided in a contact hole formed in a protective film covering the entire surface of the silicon substrate 1, thereby manufacturing a MOS type dynamic RAM. Problems with the Background Art However, the conventional method of manufacturing a semiconductor device as described above has the following drawbacks.

That is, when growing the thermal oxide film that will become the second gate insulating film in a wet oxygen atmosphere, as shown in FIG. The oxide film 11 of the first gate electrode 5 is lifted up due to the difference in oxidation rate with crystalline silicon, and a so-called overhang structure is formed in which the eaves 12 of the oxide film 11 of the first gate electrode 5 protrude. The use of high melting point metals and their silicides as second gate electrode materials has attracted attention in recent years, and has begun to be put to practical use in VLSIs such as 256KD-RAMs.

When such a high-melting-point metal and its silicide are used as the second gate electrode material, the second gate may be formed under the eaves 12 of the oxide film 11 due to the wrapping characteristics during deposition in the overhang region described above. The electrode material is embedded.

When the second gate electrode is formed by patterning by photolithography in such a shape, the high melting point metal and its silicide 13 that have gone under the eaves 12 are removed as shown in FIG. 2b. The second gate electrode 8 remains.
This causes them to short circuit each other.

In order to remove the remaining high melting point metal and its silicide, it is necessary to carry out overetching during the patterning process.

As a result of such overetching, the width of the second gate electrode 8 becomes extremely narrow, which hinders high-density microfabrication.

In addition, recently, anisotropic etching such as reactive ion etching with high processing accuracy has been used for etching gate electrodes, but with this etching method, etching progresses in a direction, so No matter how much over-etching is done, the residue that has gotten under the eaves 12 cannot be removed. Furthermore, high melting point metals and their silicides are
0°C), and the stress caused by this stress causes an extreme step part that causes an overhang as described above to cause step breakage 14 as shown in Figure 2c, making it unusable as wiring. It also has some drawbacks when you get used to it. OBJECTS OF THE INVENTION It is an object of the present invention to suppress the lifting phenomenon of the end of the first gate electrode and improve the overhang structure, thereby reducing the amount of residual material of the second gate electrode under the overhang region. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress the deposition of the second gate electrode and also prevent breakage at the step portion during heat treatment of the second gate electrode.

Summary of the Invention In order to achieve the above object, the present invention forms a film on the surface of a first electrode material film, implants impurity ions through this film, and implants impurities near the surface of the first electrode material film. a step of causing damage, a step of etching the first electrode material film using a mask material after removing the film to form a lower electrode having a tapered step, and a step of etching the first electrode material film on the surface of the first electrode material film. forming an insulating film and a second electrode material film to cover the tapered stepped portion; and patterning the second electrode material film into a desired shape using a mask material to form an upper electrode. It is characterized by comprising a process.

Embodiments of the present invention will be described in detail below with reference to the drawings.

Embodiment of the Invention FIGS. 3a to 3f show cross-sectional views of each step of the device when the present invention is applied to the manufacture of a MOS type dynamic RAM having a two-layer gate electrode structure.

First, an area other than the element region of the P-type silicon substrate 21 is etched using a silicon nitride film (not shown) as a mask, and this etched portion is doped with boron to form a p+-type region 22 for channel cutting. Using this as a oxidation mask, selective oxidation is performed to form a field oxide film 23.

Subsequently, a thermal oxidation process is performed to grow a silicon oxide film 24 with a thickness of approximately 300λ in the element region of the silicon substrate 21.

Subsequently, a polycrystalline silicon layer 25 as a first gate electrode material film is deposited to a thickness of about 4000 Å over the entire surface by CVD.

Next, phosphorus was diffused into the polycrystalline silicon layer 25 at 900° C. for 30 minutes in order to lower the layer resistance (FIG. 4a).

Next, heat treatment is performed for 1 hour in a dry oxidation atmosphere at 900° C. to form a silicon oxide film 26 with a thickness of about 500λ on the surface of the polycrystalline silicon film 25. Next, phosphorus ions are implanted into the polycrystalline silicon film 25 for taper etching. This phosphorus ion implantation is 40KeV, 3×10
This is done at about 15 cm-2 (Figure 4b). Thereafter, the oxide film 26 of the polycrystalline silicon film 25 is removed by wet etching. Note that the ion implantation conditions are not limited to the above example, but at least 1×10140
It is necessary to drive 1rL-2 or more.

In this ion implantation, it is necessary to perform ion implantation having a projected range that is approximately the same as the thickness of the oxide film 26 formed on the surface of the polycrystalline silicon film 25.

The reason why ion implantation is performed through the oxide film 26 in this manner is to prevent a double step structure from occurring during taper etching, which will be described later.

That is, if ions are directly implanted into polycrystalline silicon 5 without using oxide film 26 as shown in FIG. Since this does not occur, a double step shape is formed with a right-angled step portion and a tapered portion, and this right-angled step shape causes step breaks in the high melting point metal and its silicide. Therefore, if an oxide film is formed on the upper surface of the polycrystalline silicon film 5 and ions are implanted with a projected range approximately equal to the film thickness of this oxide film, then this oxide film is removed. As shown in FIG. 4b, in the subsequent taper etching, a polycrystalline silicon film 5 having a gentle taper without a right angle step can be formed.

By performing ion implantation through the oxide film in this manner, damage caused by ion implantation can be caused only to the surface of polycrystalline silicon.

Subsequently, as shown in FIG. 3C, a resist pattern 27 is formed on the polycrystalline silicon layer 25 at a portion where the first gate electrode is to be formed by photolithography. Next, a first gate electrode 28 is formed by plasma etching or the like using the resist pattern 27 as a mask.

In this first gate electrode 28, ions are implanted through an oxide film, so that only the surface of the polycrystalline silicon is damaged by the ion implantation. Therefore, by plasma etching, a very smooth tapered shape without right angle steps can be obtained.

Next, using this first gate electrode 28 as a mask, the exposed silicon oxide film 24 is etched to form a first gate oxide film 24.
form 9. Next, after removing the resist pattern 27, heat treatment is performed for 30 minutes in a wet oxygen atmosphere at 850°C.

In this way, an oxide film 30 with a thickness of approximately 2000λ is grown on the upper surface of the first gate electrode 28, and since the end portion of the gate electrode is tapered etched, no overhang occurs, and the oxide film 31 at the end portion is It has a very smooth shape. At the same time, the exposed surface of the silicon substrate 21 has a second
An oxide film 32 with a thickness of approximately 400 mm is grown as a gate oxide film (FIG. 4d).

Next, a molybdenum silicide film 33 is deposited on the entire surface as a second gate electrode material to a thickness of about 3000λ, and after a resist pattern is formed, this is etched to overlap the top of the first gate electrode 28 with an oxide film 30 interposed therebetween. A second gate electrode 33 is formed.

Next, an oxide film 33 is formed using the second gate electrode 33 as a mask.
A second gate oxide film 34 is formed by etching (FIG. 3e).

Next, arsenic ions are implanted into the exposed substrate 21 by self-alignment, and activated to form an n-type region 35 that becomes positive to the digital line.

After that, a CVD-SiO2 film 36 is deposited on the entire surface, and the first
CVD-SiO? corresponding to second gate electrodes 28, 33 and n+ type region 35? 36 and wet oxide film 30
A contact hole 37 is formed by selectively etching away. Thereafter, an aluminum film is vacuum deposited and patterned to form the first and second gate electrodes 28,
33 and the n+ type region 35 via a contact hole 37, an aluminum wiring 38 is formed to manufacture a MOS type dynamic RAM ((FIG. 3f)).

In the above-described embodiment, the silicon oxide films 26 and 30 oxidized in a dry oxygen atmosphere were grown on the polycrystalline silicon film 28 as the first gate electrode. A similar oxide film can also be formed by the CVD method.

Effects of the Invention As described above in detail based on the embodiments, according to the method of the present invention, the layer resistance of the first gate electrode made of polycrystalline silicon can be made sufficiently low. Since ion implantation is performed through the oxide film, damage occurs only to the surface portion, so that an electrode film having a gentle slope can be formed by the subsequent taper etching.

Therefore, the lifting of polycrystalline silicon during the subsequent oxidation in a wet oxygen atmosphere at low temperatures is
can be prevented and the overhang structure can be improved.

Therefore, step breakage can be prevented when heat treatment is performed using a high melting point metal such as molybdenum silicide and its silicide as the second electrode material film.

Furthermore, even when anisotropic etching is used to etch the second electrode material film, it is possible to prevent short circuits between the second gate electrodes due to etching residue V, resulting in high reliability and high density etching with small pattern conversion differences. M with a second gate electrode of
An OS type dynamic RAM can be obtained.

[Brief explanation of drawings]

Figures 1a-d show MOs with conventional double-layer gate electrode structure.
A cross-sectional view of an element showing the manufacturing process of an S-type dynamic RAM,
FIGS. 2a-c are device cross-sectional views for explaining the problems in forming a double-layer gate electrode in the above manufacturing process, and FIGS. 3e-f are MOS type devices according to an embodiment of the present invention. Process-specific cross-sectional diagrams showing the manufacturing process of dynamic RAM, Figures 4A and b
1 is a sectional view showing a shape formed by taper etching. 21... Silicon substrate, 23... Field oxide film 26... Film (oxide film), 28... First gate electrode (lower electrode), 29... First gate oxide film, 30...
- Low temperature oxide film, 33... second gate electrode, (upper electrode) 34... second gate oxide film, 38... aluminum wiring.

Claims (1)

[Claims] 1. A first electrode material film and a second electrode material film are deposited on a semiconductor substrate via an insulating film, and each material film is patterned into a desired shape to form a lower electrode. and an upper electrode, a film is formed on the surface of the first electrode material film, and impurity ions are implanted through the film to damage near the surface of the first electrode material film. etching the first electrode material film using a mask material after removing the film to form the lower electrode having a tapered step; and etching the first electrode material film on the surface of the first electrode material film. forming the insulating film and the second electrode material film to cover the tapered stepped portion;
A method for manufacturing a semiconductor device, comprising the step of patterning the second electrode material film into a desired shape using a mask material to form an upper electrode. 2. A polycrystalline silicon film as the first electrode material film,
Claim 1, characterized in that a high melting point metal or a high melting point metal silicide is used as the second electrode material film.
A method for manufacturing a semiconductor device according to section 1. 3 The impurities in the ion implantation are As, B, P, and S.
The method for manufacturing a semiconductor device according to claim 1, characterized in that i or Ar is used.