JPS5948332B2 - Photoelectric conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a photoelectric conversion circuit that detects the amount of light with a photodiode and converts it into a voltage corresponding to the amount of light.

A conventional photoelectric conversion circuit uses a differential type operational amplifier, as shown in FIG.

In the figure, numerals 3 and 4 are P-channel MOSFETs whose sources and back gate terminals are connected in common, with the gate terminal of FET 3 serving as an inverting input terminal and that of FET 4 serving as a non-inverting input terminal. In addition, the drains are each NPN
It is connected to an active constant current load circuit composed of transistors 6 and 7. The non-inverting input terminal is connected to the GND terminal 15. The signal input from the inverting input terminal is MOS
Amplified and taken out from the drain of FET4, NPN
It is transmitted to the base of transistor 8. transistor 8
The collector of is connected to a load resistor 10 and the base of an NPN transistor 11 that constitutes an output stage emitter follower circuit, and the signal is amplified by transistor 8 and taken out from the emitter of transistor 11, and then sent to output terminal 14.
The output voltage will be . Resistor 12 is a load resistance of transistor 11. A diode 1 is connected between the output terminal 14 and the inverting input terminal, and a photodiode (hereinafter referred to as SPD) 2 is connected between the inverting input terminal and the GND terminal 15. In addition, 5 is a resistor, 9 is a phase compensation capacitor,
13 is a power terminal. Assuming that any light is now hitting the SPD 2, a photocurrent 1L flows along the path 11→1→2 as shown in FIG. 1.

Since the gate terminal of MOSFET 3 is insulated due to its structure, only leakage current flows and can generally be ignored.
Since the gate of FET 4 is grounded, the voltage at the gate terminal of FET 3 is almost at the Y ground potential.

This operation is well-known since negative feedback is provided by the diode 1. To be precise, the input offset voltage Vi is due to the difference in threshold voltage Vth between FETs 3 and 4.
O appears. Therefore, the output voltage V. is expressed by the following equation. VO=ViO+forward voltage of diode 1 As shown in the above equation, the photocurrent IL appears at the output terminal 14 as a logarithmically converted voltage.

Since the photocurrent is proportional to the amount of light, generally in a 1:1 relationship, the amount of light is logarithmically converted to voltage. The drawback of the conventional circuit shown in FIG. 1 is that the output voltage changes depending on the MOSFET (DViO), as can be seen from the above equation.

Generally, MOSFET (DViO) is large enough to reach 1±50mV, and offset adjustment must be performed to compensate for this.Also, since it is a differential type, when converting the light intensity of multiple channels, Since the circuit in Figure 1 must be parallelized by the number of channels, MOS
The number of FETs (2) is required to be more than twice the number of channels. If this is implemented using an integrated circuit, the MOSFET occupies a large area, resulting in an increase in chip size. This invention was made in view of these points, and by using a single 2-input format instead of the conventional differential input format, the influence of input offset voltage on the output is eliminated, eliminating the need for offset adjustment. In addition, the present invention proposes a photoelectric conversion circuit that can reduce the number of MOSFETs required when converting the light amount of multiple channels. Second
The figure shows one embodiment of the invention.

In the figure, the first MOSFET 3 has its source and back gate connected to the power supply terminal 13, and its gate connected to the connection point between the anode side of the SPD 2 and the collector of the NPN transistor 11.
The drain is connected to the load resistor 5 and NPN1-. , are connected to the connection points of the bases of the transistors 8, respectively. Second MOSF
The source and back gate of ET4 are connected to the power supply terminal 13, and the gate and drain are connected to the cathode side of SPD2.
The emitter of NPN transistor 8 is connected to GND terminal 15,
The collector is connected to the load resistor 10 and the base of the NPN transistor 11. The emitter of the NPN transistor 11 is connected to the GND terminal 15, and the collector is connected to the SPD as described above.
It is connected to the anode of MOSFET 2 and the gate of MOSFET 3.
Therefore, MOSFET3→NPN transistor 8→NP
Negative feedback occurs in the loop of N transistor 11→MOSFET 3, and the overall gain is stable at 0 dB. Here, the phase compensation capacitor 9 prevents oscillation around the phase due to negative feedback, and as an example, is connected in parallel between the pace and collector of the NPN transistor 8, but it is especially necessary to do so at this point. There isn't. MOSFETs 3 and 4 are
An enhancement type P-channel MOSFET is used as an example. Next, the operation of this circuit will be explained.

Now, assuming that any light is hitting SPD2, the photocurrent IL corresponding to the amount of light will change from MOSFET4 to SPD2.
→Flows with NPN transistor 11. The collector potential of the NPN transistor 11 is as follows: MOSFET3→NPN transistor 8→NPN transistor 11→MOSFET3
Due to negative feedback in the path of
Potential VA determined by th and power supply voltage (VA= Vcc-
V, h). Furthermore, the gate and drain of MOSFET 4 are connected to the cathode side of SPD 2, and a photocurrent IL flows therethrough. Approximately V≧−Vth, which is equal to VA. This is necessary in order to minimize the influence of the dark current of the SPD 2, and the SPD 2 is normally operated in such a state that the anode and cathode potentials are equal. Figure 3b shows the MOSFET
ET drain-source voltage VDS vs. drain current I
This is the D characteristic. The bias current of MOSFET 3 is determined by the load resistor 5, and this load resistor 5 is connected to the NPN transistor 8.
Since the transistor 8 is connected between the base and emitter of the transistor 8, the forward voltage VBE of the transistor 8 is set to 0.6V. Therefore, the drain current I of MOSFET3
D is determined by dividing 0.6V by the resistance value of resistor 5.
Vth is determined by this ID. As mentioned above, SPD2
Due to the Vth of MOSFETs 3 and 4, the potentials of the anode and cathode become approximately equal, and the photocurrent in this state flows as the collector current of the NPN transistor 11.

Here again, the current at the gate of MOSFET 3 can be ignored. Therefore, the voltage at the output terminal 14 is only the base-emitter forward voltage of the NPN transistor 11, and is expressed by the following equation. As in the previous equation, in the circuit of FIG. 2, the output voltage does not include the MOSFET (DViO).

Therefore, offset adjustment is not necessary. On the other hand, when performing photoelectric conversion of multiple channels using this photoelectric conversion circuit, MOSFET 4 can be used as a common element as shown in Figure 4, so the amplifier for each channel is placed within the dotted line shown in Figure 4. Only the circuit 100 is required.

In the figure, 16 and 17 are SPs of the second channel.
D and output terminals 18 and 19 are the SPD and output terminal of the nth channel. Therefore, only one MOSFET is required for each channel, which saves the number of elements. In other words, in the case of n-channel, in the conventional circuit, MOSFET
2n pieces are required, whereas in the circuit of Fig. 4, (n+1
) is sufficient. FIG. 5 shows another embodiment of the present invention, in which MOSFETs 3 and 4 are N-channel enhancement type MOSFETs.

Therefore, the connection is completely opposite to that in Figure 2, and the NPN in Figure 2
Transistors 8 and 11 become PNP transistors 21 and 22, respectively. In this case, since transistors complementary to the circuit shown in FIG. 2 are used, the operation is exactly the same except that the potential is reversed. In addition, in Figure 5,
Although constant current sources 20 and 23 are used in place of the load resistors 5 and 10, both act as loads and operate in exactly the same way. A multi-channel circuit using the circuit of FIG. 5 is shown in FIG. This case is also the same as FIG. 4. FIG. 7 shows a modified circuit of the circuit shown in FIG. 2, in which the resistive loads 5 and 10 are changed to constant current loads 20 and 23, and a level shift resistor 24 is inserted. Further, a diode 25 similar to the transistor 11 is inserted between the emitter of the NPN transistor 11 and the GND terminal 15 so that the change in output voltage when IL changes becomes large. In other words,
This diode 25 increases the base potential of the NPN transistor 11. The output voltage V of this circuit. is expressed by the following equation. However, Ll23 is constant current source 2
3 is the current value, and R and 4 are the resistance values of the level shift resistor 24.

By appropriately selecting 123 or R24, the output voltage can be set freely.

FIG. 8 shows a reference voltage source 2 in place of the diode 25 in FIG.
7 is included, and by changing this value, any information can be included.

Further, the constant current source 26 controls the MOSFE by changing the photocurrent.
It is inserted for the purpose of flowing a certain bias current in order to prevent the Vth of T4 from fluctuating. The purpose of the diode 28 is to lower the open loop gain. The output voltage V of this circuit.
is expressed by the following equation. Here, Vr is the voltage value of the reference voltage source 27.

As described above, according to the circuit of the present invention, the photoelectric conversion output voltage is only a pure logarithmic conversion output without any error in the offset voltage of the MOSFET, and no adjustment can be achieved. Further, when a multi-channel conversion circuit is constructed using this, the number of MOSFETs is reduced, which is economical. This is extremely advantageous when implemented using an integrated circuit. Furthermore, there is no need to tighten the standards for the offset voltage of the MOSFET, which has great advantages in terms of manufacturing process management and parts purchasing.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional photoelectric conversion circuit, Figure 2 is a circuit diagram showing an example of a conventional photoelectric conversion circuit.
The figure is a circuit diagram showing one embodiment of this invention, and Figure 3 is a MOS
FIG. 4 is a circuit diagram showing an application example of FIG. 2, FIG. 5 is a circuit diagram showing another embodiment of the present invention, FIG. 6 is a circuit diagram showing an application example of the FET, and FIG. 7 and 8 are circuit diagrams showing still other embodiments of the present invention. In the figure, 2 is a photodiode, 3 and 4 are MO
SFET, 5 and 10 are resistors, 8 and 11 are NPN
Transistor, 13 is a power supply terminal, 14 is an output terminal, 15
is the GND terminal, 20, 23 and 26 are constant current sources, 21
22 is a PNP transistor, 24 is a level shift resistor, 25 and 28 are diodes, and 27 is a reference voltage source.

Claims (1)

[Claims] 1: a first insulated gate field effect transistor connected in series between a first level potential source and a second level potential source;
a photodiode and a first bipolar transistor; a first load and a second bipolar transistor connected in series between the two potential sources; a second insulated gate field effect connected in series between the two potential sources; a transistor and a second load, the gate of the first insulated gate field effect transistor is connected to the connection point between the first insulated gate field effect transistor and the photodiode, and the base of the first bipolar transistor is provided. at the connection point between the first load and the second bipolar transistor, the base of the second bipolar transistor at the connection point between the second insulated gate field effect transistor and the second load, and the base of the second bipolar transistor at the connection point between the second insulated gate field effect transistor and the second load. A photoelectric conversion circuit comprising a gate of a second insulated gate field effect transistor connected to a connection point between the photodiode and the first bipolar transistor. 2. The photoelectric conversion circuit according to claim 1, wherein the second load is a resistor. 3. The photoelectric conversion circuit according to claim 1, wherein the second load is a constant current source. 4. Claim 1 in which the second load is a diode.
The photoelectric conversion circuit described in . 5. The photoelectric conversion circuit according to any one of claims 1 to 4, wherein the first load is a resistor. 6. The photoelectric conversion circuit according to any one of claims 1 to 4, wherein the first load is a constant current source. 7. The first load is composed of a constant current source connected to the first level potential source and a level shifting resistor connected between the constant current source and the second bipolar transistor, and 5. The photoelectric conversion circuit according to claim 1, wherein a connection point between the constant current source and the level shifting resistor is an output terminal. 8 a first insulated gate field effect transistor connected in series between a first level potential source and a second level potential source;
a photodiode, a first bipolar transistor, a means for increasing the absolute value of the base potential of the first bipolar transistor, a first load and a second bipolar transistor connected in series between the two potential sources; comprising a second insulated gate field effect transistor and a second load sequentially connected in series between both potential sources;
The gate of the first insulated gate field effect transistor is connected to the connection point between the first insulated gate field effect transistor and the photodiode, and the base of the first bipolar transistor is connected to the connection point between the first load and the second bipolar transistor. the base of the second bipolar transistor at the connection point between the second insulated gate field effect transistor and the second load; A photoelectric conversion circuit having a gate connected to a connection point between the photodiode and the first bipolar transistor. 9. The photoelectric conversion circuit according to claim 8, wherein the means for increasing the absolute value of the base potential of the first bipolar transistor is a diode. 10. The photoelectric conversion circuit according to claim 8, wherein the means for increasing the absolute value of the base potential of the first bipolar transistor is a reference voltage source. 11 Claim 8, wherein the second load is a constant current source
The photoelectric conversion circuit according to any one of Items 1 to 10. 12. The photoelectric conversion circuit according to any one of claims 8 to 10, wherein the second load is a diode. 13 The first load is composed of a constant current source connected to the first level potential source and a level shifting resistor connected between the constant current source and the second bipolar transistor, and 13. The photoelectric conversion circuit according to claim 8, wherein a connection point between the constant current source and the level shifting resistor is an output terminal. 14 A first insulated gate field effect transistor, a photodiode, and a first bipolar transistor connected in series between the first level potential source and the second level potential source; 1 load and a second bipolar transistor, a second insulated gate field effect transistor and a second load connected in series between both potential sources, the first insulated gate field effect transistor and a photodiode; a constant current source connected between the connection point of and the second level potential source, the gate of the first insulated gate field effect transistor is connected to the first insulated gate field effect transistor and the photodiode. The base of the first bipolar transistor is connected to the connection point between the first load and the second bipolar transistor, and the base of the second bipolar transistor is connected to the connection point of the second insulated gate field effect transistor. and a second load, and a gate of the second insulated gate field effect transistor is connected to a connection point between the photodiode and the first bipolar transistor, respectively. 15. The photoelectric conversion circuit according to claim 14, wherein the second load is a diode. 16 Claim 1 in which the second load is a constant current source
4. The photoelectric conversion circuit according to item 4. 17 The first load is composed of a constant current source connected to the first level potential source and a level shifting resistor connected between the constant current source and the second bipolar transistor, and 17. The photoelectric conversion circuit according to claim 14, wherein a connection point between the constant current source and the level shifting resistor is an output terminal.