JPS5948578B2 - Single sideband frequency division multiplex signal demodulation method using digital processing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single sideband frequency division multiplexed signal (hereinafter referred to as SSB-F
The present invention relates to an SSB-FDM signal demodulation method for converting a DM signal (referred to as a DM signal) into a baseband signal.

Conventionally, an analog modulator and an analog band-pass filter have been used to extract a baseband signal from an SSB-FDM signal in which a predetermined number of baseband signals are multiplexed in the frequency domain.

Instead of using such analog processing technology, S
It has become possible to extract a baseband signal from an SB-FDM signal.

The following literature shows a typical known example of performing the above extraction digitally. Publication “IEEE TR-ANSACTION SONCOMM” published in December 1971.
UNICATION TECHNOLOGY, VOL-C
The paper “System Analysis” published on pages 1050 to 1059 of “OM-19, M6”
DM-FDM Transl-ator/Digital
A-typeChannelBanK'' (Reference 1) 01
Publication “EEETRA-NSAC” published in September 1974
TIONSON COMMUNICATIONS, VOL
- COM-22, M9, pages 1199 to 1205 of the paper "TDM-FDM Transmul-tip"
lexer■DigitalPolyphaseand
FFT” (Reference 2).

When using digital processing technology, the number of multiplications required per unit time almost entirely depends on the size of the device.
In turn, the device price is determined.

This is due to the fact that multiplication is the most complicated process in digital calculations, and multiplication is an essential calculation element in constructing digital modulators and digital filters. SUMMARY OF THE INVENTION An object of the present invention is to provide a single sideband frequency division multiplex signal demodulation method using novel digital processing that requires fewer multiplications per unit time.

Another object of the present invention is to provide a single sideband frequency division multiplex signal demodulation system that is compact, inexpensive, and easy to manufacture and maintain. Another object of the present invention is to provide a single sideband frequency division multiplexed signal demodulation scheme that facilitates the conversion of frequency division multiplexed signals to time division multiplexed signals.

Yet another object of the present invention is to provide a single sideband frequency division multiplex signal demodulation scheme that simplifies the hardware of the polyphase circuit. The single sideband frequency division multiplexing signal demodulation method of the present invention obtains an actual sample value when a frequency division multiplexed signal of N baseband signals including an arbitrary number of dummy baseband signals is sampled at a sampling frequency N-Fs. a polyphase circuit that is supplied with a sequence as an input and outputs N complex sample value sequences respectively corresponding to N subsample value sequences when the real sample value sequence is further sampled at a sampling frequency Fs, and the polyphase circuit An offset discrete Fourier processing circuit that receives N complex sample value series outputs as input and outputs N complex sample value series, and a bandwidth Fs/
It is characterized in that it is constructed by cascading a complex filter having two complex filters.

Next, the principle and configuration of the SSB-FDM signal demodulation system of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram for explaining the principle of the SSB-FDM signal demodulation method of the present invention.

Reference letters (4) and 8 indicate examples of frequency spectra of SSB-FDM signals obtained by multiplexing N baseband signals having a bandwidth Fs/2 Hertz (units are omitted hereinafter) in the frequency domain.

The bandwidth of the SSB-FDM signal of the N-channel baseband signal is N-Fs/2. In particular, reference letter (4) indicates an SSB-FDM signal in the 0NN-Fs/2 band, and reference letter 8 indicates an SSB-FDM signal in the band from N-Fs/2 to N-Fs.
The cases where there is an FDM signal are shown respectively. Reference alphabet (4)
Or, when sampling the SSB-FDM signal with the frequency spectrum of 8 at frequency N-Fs, the reference alphabet (
A sample value sequence having a spectrum of C) is obtained. In the above explanation, when the number N of multiplexed channels is given, the sampling frequency N-Fs is uniquely determined, but this relationship can be changed freely by assuming an appropriate number of dummy channels in the number N of multiplexed channels. can be changed to

Considering a 60-channel FDM supergroup as an example, this SSB-FDM signal exists in the 312-552 KHz band.

Further, the bandwidth Fs/2 of one channel is 4 KHz. In this case, assuming 12 dummy channels, N272, and the band of the 72 channels of SSB-FDM signal is 288~288 (including the above 312~552KHz).
Considering 576KHz, the sampling frequency N-Fs
is 576KHz. It is convenient for N to be a power of 2 for reasons explained later.

In the above example, to make N a power of 2, four dummy channels can be included to make N=64, and the sampling frequency can be set to N-Fs=512 KHz. In this case, the supergroup band 312 to 552 KHz is set in advance to
For example, it is necessary to frequency shift to the 8-248 KHz band. Hereinafter, the present invention will be described with reference to a sample value series of an SSB-FDM signal having a frequency spectrum as indicated by the reference letter (C). If only the signal component of a specific channel as shown in reference alphabet 9 or [F] is extracted from the frequency spectrum of reference alphabet (C), and the extracted signal is further subsampled at frequency Fs, the frequency of reference alphabet 8 or 6 is obtained. A spectrum is obtained.

The direction of the frequency spectrum of the reference alphabet 6 is opposite to the direction of the frequency spectrum of the reference alphabet 8, resulting in frequency inversion. For a sample value series having a frequency spectrum of reference alphabet 6, the polarity of the sample values is inverted every other sample. In other words, it is possible to invert the frequency spectrum by multiplying by (-1)n (where n is the time number of the sample point). spectrum can be obtained. The reference letters 8 and 8 are nothing but spectra of the sample value series of the baseband signal sampling frequency Fs.

Therefore, the reference alphabet (b) and 5 signals can be converted to the original analog baseband signal by passing through a low-pass filter with a band of Fs/2. The present invention is characterized by an arithmetic method for obtaining baseband sample value sequences of a reference alphabet (translated) and I from a sample value sequence of an SSB-FDM signal such as a reference alphabet (C), and a circuit for realizing the same.

First, for convenience, channel numbers in the sample value series (hereinafter sometimes simply abbreviated as sample value series) of the SSB-FDM signal are assigned as follows.

Let k be an integer from o to N-1, and the signal of the k-th channel means a signal whose center frequency is (4k+1)Fs/4. Since the SSB-FDM signal is a real signal sequence, it has a symmetrical structure with a frequency that is 1/2 of the sampling frequency NFs as a symmetrical point, and has a number arrangement as shown in FIG. 1C. Next, the sampling frequency N-Fs
Assume a complex digital bandpass filter (CBPF) operating at And this Z transfer function is expressed as Hk.

However, Z is Z=ExpIJ2πf/(N − Fs)}
is defined, and Z-1 is a delay operator indicating the sample delay. The signal of the k-th channel is obtained as the real part of the filter output by passing the SSB-FDM signal through a filter Hk.

The Z transformation of the k-th channel signal (before subsampling with Fs) is X-transformed, and the Z-transformation of the SSB-FDM signal is Y(
Zl), the above operation can be expressed as follows. Xk
(self)=Re{Hkノ)・Yｽ｝} (1) Instead of directly calculating equation (1), YΦ is set to the sampling frequency Fs(
1) It is also possible to decompose it into N sets of subsample value series Yn (ZN) and perform calculations with a configuration as shown in FIG.

In Figure 2, the terminal designated by reference numeral 1 has an SSB
-FDM signal Y (self) is applied, and the signal component Xk of the k-th channel is obtained from the terminal indicated by the reference numeral 7. Reference numbers 21, 22... 2N are (N-1), (N-2),... for Y, respectively.
, o samples, and reference numbers 31, 32, ..., 3N are sub-sample switches operating at frequency Fs, and the output signal of each switch is YO, (ZN). ,Y1 (ZN),...
, YN-1 (ZN). Reference numbers 41, 42,・
. . . , 4N is a complex (digital) bandpass filter having the aforementioned transfer function Hk, with reference numerals 51, 5
2,...,5N are respectively 0, 1,...
, (N-1) sample delay circuit, and the reference numeral 6 is the delay circuit 51, 52, . . . 5N
This is an adder circuit that combines the outputs of . From Figure 2, Yn(Z
The relationship between N) and Xk is expressed as equation (2).

The complex band filter Hk2 has a band of Fs/4 as well as the real low-pass filter G? It can be obtained by applying a frequency shift of (4k+1)Fs/4 to .

In other words, it becomes.

Next, considering that the input to the real low-pass filter G(z!) is given at the sampling frequency Fs, we can input G(Z to N filters Gi() operating at the sampling frequency Fs.
It is easy to see that it can be refined by using ZN).

is required.

That is, each sub-filter Gi(ZN) is GΦ・zl
If the impulse response is equal to the impulse response sampled at the frequency Fs, the impulse response of G can be obtained by delay-adding these according to equation (4). If G(Z) passes only the band below Fs/2, the in-band amplitude characteristic of G,(ZN) is equal to all 1's, G,(ZN)/G.

The in-band phase transfer characteristic of (ZN) is Exp2π f・(1)
It has a linear phase characteristic.

That is, N-FQG (Z can be considered by being decomposed into sub-filter groups G, (ZN) having equal amplitude characteristics and differing only in phase characteristics.

The inputs to the filters 41, 42, . . . , 4N in FIG. 2 are also given at the sampling frequency Fs. and expression (3
Since it is related to the actual low-pass filter G by , the result of equation (4) can be applied.

G1(-JZN) is the Z transfer function N of Gi(ZN) mentioned above.
．． In N, it has a Z transfer function in which all Z's are replaced with -JZ, and is equivalent to the frequency characteristic of Gi(Z) shifted by Fs/4.

Therefore, NGl(-JZ) also has the same amplitude characteristics for all i, and only the phase characteristics are proportional to i.

These N sub-filter groups Gi(-JZ) will be collectively referred to as a polyphase circuit.

Therefore, by substituting equation (5) into equation (2) and rearranging, we get
Xk2 can be expressed as follows.

However, n+i:p. Since Xk2 needs to be sampled next at frequency Fs, p=N− in equation (6).
1, and if the N series of sample values after sampling is Xk(Z), excluding the overall simple delay, it is possible to obtain .

Next, the complex band filter, which is a component of the polyphase circuit, will be explained in detail.

First, the standards for the in-band characteristics and out-of-band attenuation for filter G2 with sampling frequency N-Fs are given, and then the standard is satisfied. Such filter G (2)
is designed.

Here, G(2) is a real low-pass filter D(ZN) having a bandwidth Fs/4 designed at the sampling frequency Fs, and a sampling frequency N-Fs so as to attenuate the harmonics of this D(ZN). Assuming that G2 is given by cascade connection with filter E(8) designed as follows, G2 can be expressed as follows. Here, if G(8) is decomposed as shown in equation (4), we obtain.

As is clear from equation (9), D(Z) can be grouped out as a common term in the polyphase N circuit, so
In the following explanation, the N sub-pools Ei(Z) will be regarded as a polyphase circuit.

If formula (9) is used, "" can be obtained instead of formula (7).

FIG. 3 shows the SSB-
An example of an FDM signal demodulation method is shown.

The input terminal indicated by the reference numeral 301 has an SSB-FDM
The signal sample value series Y(2) is input. The reference number 304 is the reference number 21, 22, . . . in FIG. 2.
. . , 2N and 31, 32, . . . , 3N.
The N outputs are YN-1 (ZN), YN-2 (△N...
..., corresponds to YO(Z).

N sets of output signals Y (Z
) is the next reference number N-1-1 characters 311, 312,...
. . , is supplied to the sub-filter group indicated by 31N.

Reference numbers 311, 312, N..., 31N0)
The Z transfer function is E.

(-JZ), E1 (-JZN), ... - ..., EN-1
(-JZN). SSB- given to terminal 301
Since the FDM signal, that is, the output of the serial-to-parallel converter 304 is a real signal, the sub-filter groups 311, 312, . . .
. . , 31N, the calculation part related only to the imaginary part input can be omitted. Sub-filter groups 311, 312, ..., 31N forming the polyphase circuit
The complex output of is provided to an offset discrete pulley processing circuit indicated by the reference numeral 302 below.

The offset discrete Fourier processing circuit 302 performs the calculation and is provided as described above because it is similar to the discrete Fourier inverse transform equation.

The signal Ai(Z) in equation (auto)N is given as.

Furthermore, the output B of the offset discrete Fourier processing circuit 302
A complex filter 33 whose (Z) has a bandwidth FkS/4
1, 332, 333, . . . and 33N.

Since the real number part of the output of the complex filter is equal to Xk(ZN), only the operations necessary to obtain the real number output need be performed.

Next, a complex filter ND(-J
Z) and the N sub-filters Ei (JZ) which are the constituent elements of the polyphase circuit will be explained in detail.

N First, the filter D(Z) is a real low-pass filter with a bandwidth Fs/4 designed at the sampling frequency Fs as described above, and the complex filter D(-JZ) with a bandwidth Fs/2 of NN is , can be obtained by substituting -JZ in place of Z in NN for D(Z).

N Next, a method for realizing the complex filter D(-JZ) will be described.

Generally, a recursive digital filter can be expressed as a product of quadratic expressions.

For example, consider a real filter with the following transfer function. It is well known that the actual filter expressed by equation A can be realized by the circuit shown in FIG. 4A.

In FIG. 4A, reference numeral 40 is an input terminal, reference numeral 42 is an adder, reference numerals 44 and 45 are one-sample delay circuits, and reference numerals 46, 4? , 48 and 49 indicate coefficient multiplication circuits for multiplying -Bl, -B2, Al and A2, respectively, and reference numeral 51 indicates an output terminal, respectively. In the real filter F2, the complex filter F(-JZ) in which Z is replaced with -JZ becomes the Gokyo JUI-vZ-1 and can be realized by a circuit as shown in FIG. 4B.

In FIG. 5B, reference numerals 400 and 401 represent the real part input terminal and the imaginary part input terminal, respectively, and reference numeral 4
20, 430, 421 and 431 are adders, reference numbers 440, 450, 441 and 451 are 1 sample delay circuits, 460, 470, 480, 490, 461, 4
71, 481 and 491 are Bl, B2, -, respectively
Al, - A2, - Bl, B2, Al and - A2
Coefficient multiplier circuit and reference numbers 410 and 41 to multiply
1 represents the real part output terminal and the imaginary part output terminal, respectively.

Next, N sub-filters Ei (-JZ), which are constituent elements of the polyphase circuit, will be explained in detail.

N As mentioned earlier, since filter E (self) is a multi-stop band filter that attenuates the harmonics of D (Z), it can be easily designed as a non-recursive digital filter.

E? Assume that is expressed by the following equation.ゞ゜'' The filter E1 (Z) decomposed from the formula Q is expressed as the following formula.

However, M=P−N. (However, M and P are both integers.) Furthermore, by substituting -JzN into the equation CLη instead of ZN, the complex filter Ei(-'ZN) becomes, and can be realized by a circuit as shown in FIG.

In FIG. 5, reference numerals 510 and 511 are the real part input terminal and imaginary part input terminal, respectively, and reference numeral 53
0 and 531 are delay circuits with taps for M samples, respectively. Reference numbers 5410, 5411, 5420, 542
1,543U, 5431, 5440, 5441,...
..., 54P-10, 54P-11, 54P0 and 54P0 are coefficient multiplication circuits, reference numbers 550 and 551
represents the adder and reference numerals 520 and 521 represent the real and imaginary output terminals, respectively. As mentioned in the explanation of FIG. 1, k≧N/N2 or k<−
In the channel, an operation of multiplying by (-1)n is required at the end.

Reference numeral 303 is a post-processing circuit for performing this operation. Output terminals 321, 322, 3 of post-processing circuit 303
23,...32N has k= 0, 1, 2,...
. . . , (N-1) is obtained. In this way, the present invention
It demodulates the baseband signal from the B-FDM signal, and includes N sets of low-speed operation sub-filter groups Ei (-JZN) common to each channel, an offset discrete Fourier processing circuit with N points of input and N points of output, and a band By using a complex filter having a width of F8/2, the baseband signal of the k channel can be demodulated, and the number of required multiplications per unit time can be extremely reduced.

Furthermore, according to the method of the present invention, it is possible to construct a polyphase circuit consisting of N sub-filters using non-recursive digital filters, which greatly simplifies the hardware configuration.

A technique well known as a fast Fourier transform (F}YI') can be applied to the operations required in the offset discrete Fourier processing circuit 302, thereby greatly reducing the number of multiplications.

It is known that the number of multiplications can be reduced most efficiently if N is a power of 2. Also, it can be expressed by rewriting the expression (self). Therefore, as shown in FIG. 4, it is also possible to realize an offset discrete Fourier processing circuit by cascading a phase offset circuit and a discrete Fourier inverse transform circuit. Reference numbers 601, 602, 603 in Figure 6.
..., 60N has sub-filter groups 311, 312
,313, . The discrete Fourier inverse transform circuit indicated by the reference numeral 620 calculates the equation (self) and calculates the result B
. (ZN), B1 (ZN), ......, BN-(Z
N) Reference numbers 631, 632,..., 63N
・Output to the signal line. Further, the calculation performed with reference numeral 620 can be performed by replacing k with -k in formula (self) instead of formula l. The arithmetic expression in this case can be regarded as a discrete Fourier transform. In this case as well, -k'=O becomes k=0 in equation (self), -k'=-
If it is considered that 1 corresponds to k=N-1, and generally -k'=K corresponds to k=NK, demodulation of the SSB-FDM signal can be performed in the same way. Also, the phase offset can be changed to e− instead of El2.
It may be used as J2 branch. In this case, the arrangement order of the output channel numbers will change. In an actual device, by using one circuit in a time-division multiplexed manner, that circuit can be assigned multiple functions.

For example, in the embodiment of FIG.
, 312, . . . , 31N can actually be realized by time division multiplexing of one filter operation circuit. In this case, the serial-to-parallel converter 304 is unnecessary,
The SSB-FDM signal at the terminal 301 is directly given as an input to the filter calculation circuit. The filter calculation circuit sequentially switches the coefficients to sub-filters 311 and 312.
, . . . , 31N may be executed. Further, the offset discrete Fourier processing circuit 302 can also multiplex its internal arithmetic circuits so that it receives input A1 in series and produces output Bk in series. Moreover, complex filters 311, 312, . . . , 31 having a bandwidth of F8/2
N can also be multiplexed. Furthermore, the post-processing circuit 303
This can also be realized by multiple use of one polarity inversion circuit.
The output occurs as a time division multiplexed signal, which is often convenient. If parallel output is required, a serial-to-parallel converter can be placed at the end. As explained above,
According to the present invention, it is possible to easily demodulate an SSB-FDM signal by using one polyphase circuit, one offset discrete Fourier processing circuit, and a complex filter having a bandwidth Fs/2. Become.

The polyphase circuit and the complex filter with a bandwidth Fs/2 can be realized for all channels with almost the same amount of computation as the bandpass filter Hk2 for one channel with a sampling frequency of N-F8, and offset discrete Fourier processing can be performed. Since the FFT calculation method can also be applied to the circuit, it is possible to demodulate the SSB-FDM signal with an overall small amount of calculations. Furthermore, since all arithmetic processing can be performed digitally, it is possible to make the device smaller, lower in price, and easier to manufacture and maintain. Furthermore, the present invention provides S
Since the present invention is characterized by a calculation method for obtaining a sample value sequence of a baseband signal from a sample value sequence of an SB-FDM signal and a circuit for implementing the same, an FDM signal can be easily converted into a TDM signal as is. Further, according to the method of the present invention, it is possible to construct a polyphase circuit consisting of N sub-filters using non-recursive digital filters, which greatly simplifies the hardware configuration.

In addition, in the above explanation, the center frequency of filter Hk2 has been explained as (4k+1)Fs/4, but it is first clear that baseband signals can be demodulated without any inconvenience even if this frequency is set as (4k+3)Fs/4. It can be easily understood from the diagram.

In the above explanation, if you change everything from (4k+1)Fs/4 to (4k+3)Fs/4, the final Gi
(-JZN) becomes Gi(JZN), so door i(J
ZN) and D(JZN), and Exp(J2π4
! The phase offset of N) will change to Exp(J2π-). At this time, Gi(JZbemaGi(-J
The center frequency of ZN) is shifted by Fs/2 to become a complex band filter with a center frequency of 3 fs/4.

[Brief Description of the Drawings] Figures 1A-H are diagrams for explaining the principle of the present invention, Figures 2A-H are diagrams for explaining the principle of the present invention;
The figures are diagrams for explaining the present invention, Figure 3 is a diagram showing an embodiment of the present invention, and Figures 4A and B are diagrams for explaining a complex filter having a bandwidth Fs/2 used in the present invention. Diagram.
FIG. 5 is a diagram for explaining a sub-filter which is a component of the polyphase circuit used in the present invention, and FIG. 6 is a diagram showing in detail the offset discontinuation Fourier processing circuit shown in FIG. 3. 3 and 6, reference numeral 301 is an input terminal for the sample value series of the SSB-FDM signal, reference numeral 302 is a serial-to-parallel conversion circuit, and reference numeral 311 is
, 312, 313, ..., 31N are sub-filters constituting the polyphase circuit, reference numeral 302 is an offset discrete Fourier processing circuit, reference numerals 331, 332
, 333, . . . , 33N are complex filters having a band Fs/2, reference numeral 303 is a post-processing circuit, reference numerals 321, 322, 323 . . . . , 32N is an output terminal for the baseband signal sample value series of N channels, reference numbers 611.612.613.・・・ ・
. . 61N indicates a phase offset circuit, and reference numeral 620 indicates a discrete Fourier (inverse) transform circuit.

Claims (1)

[Claims] 1 A first real sample value sequence obtained by sampling a frequency division multiplexed signal of N baseband signals including an arbitrary number of dummy baseband signals at a sampling frequency N·f_s is supplied as an input, and the first real sample value sequence is supplied as an input. outputs N first complex sample value sequences respectively corresponding to the N second real sample value sequences when the real sample value sequence is further sampled at the sampling frequency f_s, and at the sampling frequency N·f_s. A first filter group consisting of N complex filters operating at a sampling frequency f_s obtained by decomposing a complex filter, and N first complex sample value series of this filter group are input. and a second filter group consisting of N complex filters having a bandwidth f_s/2 and a sampling frequency f_s. A single sideband frequency division multiplex signal demodulation method characterized by: