JPS594867B2 - Method of manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a manufacturing method that can easily realize a field effect transistor, particularly a structure suitable for high frequency and high output.

Conventionally, field effect transistors with a vertical structure include devices with a buried gate structure and a surface wiring structure, as shown in FIGS. 1 and 2.

In the figure, 1 is a semiconductor substrate with a high impurity concentration that becomes a drain region, 2 is a semiconductor layer with a lower impurity concentration than the substrate 1, and 3 is a substrate 1
4 is a gate region having a conductivity type opposite to that of the substrate 1, and a source region 4 having the same conductivity type as the substrate 1. A drawback of these structures is that the output decreases when trying to improve high frequency characteristics. Reason 5 is that in Figures 1 and 2, if you try to increase the area and increase the current in order to obtain high output, the capacitance between the gate 3 and the drain 1 will increase, and the frequency characteristics will change. descend. In addition, in order to operate at a high voltage, the distance between gate 3 and drain 1 was reduced by 1
If the value is set to 0, the current path will become longer and the series resistance of the channel will increase, making it difficult for current to flow and preventing high output. If the semiconductor layer 2 is made thicker in an attempt to reduce the capacitance in order to improve high frequency characteristics, it will similarly become difficult for current to flow and high output will not be achieved. A structure as shown in FIG. 3 has been proposed as a structure to compensate for the above-mentioned drawbacks. In this structure, a high concentration region 11 protrudes from a drain region 1 in a region facing a source region 4 and is formed along the shape of an edge 20 of an air layer extending from a gate 3.
Therefore, the series resistance of the current path can be lowered and a large current can be generated without increasing the capacitance between the gate and drain.
Although it is clear from the above description that the above structure is suitable for higher frequencies and higher outputs, it has been extremely difficult to realize this.

That is, as a method for obtaining such a structure, first, the semiconductor layer 2 is grown by a vapor phase growth method or the like to a thickness that includes the protruding region 11, and then an impurity having the same conductivity type as that of the substrate 1 is added to the portion that is to become the region 11. 30 at a high concentration to form the region 11, and then grow the semiconductor layer 2 again to a desired thickness, or selectively excavate a predetermined surface region of the substrate 1 to form a recess. A semiconductor layer 2 is formed by vapor phase growth on a substrate 1 in which a recessed portion is formed, and the recessed portion is
A method is proposed in which the gate region 3 is formed in the surface layer of the semiconductor layer 2 which is projected from the surface of the semiconductor layer 2, and the source region 4 is formed in the surface layer of the semiconductor layer 2 which is projected by the surface region of the substrate 1 other than the upper concave portion. However, when using the former method, it is necessary to perform vapor phase growth in two steps to form the semiconductor layer 2, and when using the latter method, recesses are also formed in the semiconductor layer 2. Therefore, there was an inconvenience that photolithography for forming the gate region 3 and source region 4 became difficult.

This invention was made in view of the above points, and an object of the present invention is to easily realize a field effect transistor having a structure that enables high output by reducing drain resistance without increasing the capacitance between the gate and drain. The purpose is to provide a manufacturing method that allows for

An embodiment of the present invention will be described below with reference to the drawings.

First, as shown in FIG. 4a, an insulating film 6 such as a semiconductor oxide film is deposited on a predetermined surface region of an n+ type semiconductor substrate 1. As shown in FIG.
Next, as shown in FIG. 4b, using the insulating film 6 as a mask, a high concentration impurity having the same conductivity type as the substrate 1 is introduced into the substrate 1 by diffusion or ion implantation.
form 0. Here, as the impurity to be introduced, one whose diffusion rate in the semiconductor is higher than that of the impurity in the substrate 1 is selected. For example, when the impurity in the substrate 1 is antimony, arsenic and karin can be used. It is a matter of course that impurities other than group I and group I can be used as these impurities. After that, the insulating film 6 is removed and, as shown in FIG. Form. Next, as shown in FIG. 4d, gate regions 3 and 5 and source regions 4 are formed by a conventional method, such as thermal diffusion using a diffusion mask. Then, during this process, due to the difference in the diffusion rate of impurities between the substrate 1 and the region 10, the high concentration region 11 from the region 10 in the semiconductor layer 2 becomes the source region 4, as shown in FIG. 4d. They are formed to protrude so as to face each other. In this way, the region 11 that protrudes due to diffusion is formed so that the diffusion is deep in the center and shallow in the peripheral region because it spreads laterally, so its shape is similar to that of the edge of the protruding layer extending from the gate region 3. It can easily take a shape that follows the shape. Although the above description has been made by taking as an example the manufacture of an n-channel field effect transistor, it goes without saying that the present invention can also be applied to the manufacture of a p-channel field effect transistor.

As described above, according to the method of the present invention, by introducing an impurity having a higher diffusion rate than the impurity of the semiconductor substrate that becomes the drain into a partial region of the substrate, vapor phase growth is performed twice as in the conventional method. A high output field effect transistor with excellent frequency characteristics can be easily obtained without performing separate etching or etching.

[Brief explanation of the drawing]

1 and 2 are sectional views showing a conventional field effect transistor, FIG. 3 is a sectional view showing a field effect transistor having an improved structure, and FIGS. 4 a to 4 d are an embodiment of the present invention. FIG. In the figure, 1 is a semiconductor substrate, 2 is a semiconductor layer, 3 is a gate region, 4 is a source region, and 10 and 11 are high concentration regions.

Claims (1)

[Scope of Claims] 1. A low resistivity semiconductor region having the same conductivity type as the substrate and containing an impurity having a higher diffusion rate than the impurities of the substrate is selectively formed in a predetermined surface region of a low resistivity semiconductor substrate serving as a drain region. a step of forming a high resistivity semiconductor layer of the same conductivity type as the substrate on one main surface of the substrate including the semiconductor region; A method for manufacturing a field effect transistor, including a step of forming a conductive type low resistivity source region. 2. The method for manufacturing a field effect transistor according to claim 1, wherein the high resistivity semiconductor layer is formed by a vapor phase growth method.