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JPS5949719B2 - Hybrid integrated circuit device - Google Patents
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JPS5949719B2 - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS5949719B2
JPS5949719B2 JP53022997A JP2299778A JPS5949719B2 JP S5949719 B2 JPS5949719 B2 JP S5949719B2 JP 53022997 A JP53022997 A JP 53022997A JP 2299778 A JP2299778 A JP 2299778A JP S5949719 B2 JPS5949719 B2 JP S5949719B2
Authority
JP
Japan
Prior art keywords
chip
flip
integrated circuit
substrate
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53022997A
Other languages
Japanese (ja)
Other versions
JPS54115769A (en
Inventor
衞 水口
忠義 大野
高志 大関
光彦 田代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP53022997A priority Critical patent/JPS5949719B2/en
Publication of JPS54115769A publication Critical patent/JPS54115769A/en
Publication of JPS5949719B2 publication Critical patent/JPS5949719B2/en
Expired legal-status Critical Current

Links

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 この発明はフリップチップ素子を有する混成集積回路装
置に係り、特にフリップチップ素子の接続部の外部環境
に対する信頼性を向上させた混成集積回路装置に関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit device having a flip chip element, and more particularly to a hybrid integrated circuit device in which the reliability of the connecting portion of the flip chip element against the external environment is improved.

混成集積回路装置においては、集積度を上げるために1
個のチップに多数のトランジスタやダイオードを組込ん
だ半導体チップを使用することがある。
In hybrid integrated circuit devices, 1
Semiconductor chips with many transistors and diodes built into each chip may be used.

この場合、問題となるのは、チップの接続端子数が多い
ことによるボンディング工程のコスト上昇、ボンディン
グの不良による故障率の増加と歩留り、信頼性の低下で
あり、これらの問題点を解決する方法の一つに、フリッ
プチップ素子によるボンディング法があり、広く採用さ
れている。フリップチップ素子は、ワイヤリードやビー
ムリードなどのリード線を用いないで、半導体チップの
接続端子をチップ表面から突出した形状(バンプ)とし
、これと対応する位置に接続領域を有する導体パターン
を絶縁基板上に設けて、両者を超音波ボンディング法あ
るいは半田付法によつて接続するようにしたチップを総
称して呼ぶ。しかし、フリップチップ素子はチップと基
板とが接続端子および導体パターンを介して強固に接続
されるという構成のため、チップと基板との間に生じる
歪の差を吸収することが困難であり、熱的あるいは機械
的な歪を生じさせる外部環境に対する信頼性の点で問題
がある。例えば半導体チップの構成材料51と、絶縁基
板材料Al2O3とは熱膨張係数に差があり、熱サイク
ルを受けるチップには繰返し歪が生じることになる。こ
のため、熱サイクルの回数あるいは温度差によつては、
疲労により接続部が破壊する危険性があるが、実際には
このような熱的歪に対しては、それに耐え得るに十分な
強度を接続部に持たせることができ、実用上は問題とな
ることは殆んどない。しかし、フリップチップ素子を有
する混成集積回路基板を直接機構部品として取扱う場合
、例えばプリンタやファクシミリ等の記録ヘッドあるい
はビデオ機器等の磁気記録ヘッド等の用途に用いる場合
は、混成集積回路基板に直接、外力、振動が加わり、フ
リップチップ部に機械的歪が与えられることがあり、こ
の歪の大きさによつてはフリツプチツプの接続部が破壊
する危険性は十分考えられる。
In this case, the problems are an increase in the cost of the bonding process due to the large number of connection terminals on the chip, an increase in failure rate due to defective bonding, a decrease in yield, and a decrease in reliability.How to solve these problems One of these methods is a bonding method using flip-chip devices, which is widely used. Flip-chip devices do not use lead wires such as wire leads or beam leads, but instead have connection terminals on a semiconductor chip that protrude from the chip surface (bumps), and insulate a conductor pattern that has a connection area at a corresponding position. Chips that are provided on a substrate and connected to each other by ultrasonic bonding or soldering are collectively called chips. However, since flip-chip devices have a structure in which the chip and the substrate are firmly connected through connection terminals and conductor patterns, it is difficult to absorb the difference in strain that occurs between the chip and the substrate, and it is difficult to absorb heat. There is a problem in terms of reliability against external environments that cause physical or mechanical distortion. For example, there is a difference in thermal expansion coefficient between the constituent material 51 of the semiconductor chip and the insulating substrate material Al2O3, and repeated strain occurs in the chip subjected to thermal cycles. Therefore, depending on the number of thermal cycles or temperature difference,
There is a risk that the connection will break due to fatigue, but in reality, the connection can be made strong enough to withstand such thermal strain, which is not a problem in practice. There are almost no such things. However, when handling a hybrid integrated circuit board having flip-chip elements directly as a mechanical component, for example, when using it for a recording head of a printer or facsimile machine, or a magnetic recording head of a video device, etc., When external forces and vibrations are applied, mechanical strain may be applied to the flip-chip portion, and depending on the magnitude of this strain, there is a sufficient risk that the connection portion of the flip-chip may be destroyed.

すなわち、機械的歪は通常、熱的歪に比較して歪の変化
の速度、回数共に比べものにならない程大きく、疲労に
よる接続部の破壊の危険性は熱的歪より大である。従来
、混成集積回路基板を直接機構部品として使用する例は
少なく、従つて上記のような機械的歪によるフリツプチ
ツプ接続部の破壊の危険性の問題に対処する方策は考え
られていなかつたが、混成集積回路基板の機構部品への
使用例が増加しつつある現在においては、その要望大で
ある。
That is, mechanical strain is usually incomparably larger than thermal strain in both the speed and number of changes in strain, and the risk of fracture of the connection due to fatigue is greater than thermal strain. Conventionally, there have been few cases in which hybrid integrated circuit boards have been used directly as mechanical components, and therefore no measures have been considered to deal with the above-mentioned problem of the risk of flip-chip connections being destroyed due to mechanical strain. At present, there is a great demand for integrated circuit boards as the use of integrated circuit boards for mechanical parts is increasing.

この発明は上記した実情に鑑みてなされたもので、その
目的は絶縁基板上のフリツプチツプ素子の接続部に加わ
る歪を減少させて、基板が受ける外部環境に対する信頼
性を向土させ得る混成集積回路装置を提供するにある。
この発明は混成集積回路基板となる絶縁基板のうち、こ
の基板上の導体パターンのフリツプチツプ素子接続端子
の接続領域およびその近傍の導体の周辺部分を脆化させ
、この部分では基板に導体パターンが完全には固着しな
いようにすることにより、外部環境によつて基板に生じ
る歪を、導体パターンのフリツプチツプ素子接続領域お
よびその近傍の導体と、さらに基板の上記脆化させた部
分とで吸収し、フリツプチツプ素子の接続部に伝達させ
ないようにしたものである。
This invention has been made in view of the above-mentioned circumstances, and its purpose is to reduce the strain applied to the connections of flip-chip elements on an insulating substrate, thereby improving the reliability of the hybrid integrated circuit against the external environment to which the substrate is exposed. We are in the process of providing equipment.
This invention embrittles the connection area of the flip-chip element connection terminal of the conductor pattern on the insulated substrate that becomes a hybrid integrated circuit board and the peripheral area of the conductor in the vicinity, so that the conductor pattern is completely removed from the substrate in this area. By preventing the board from sticking to the board, the strain caused by the external environment is absorbed by the conductor in the flip-chip element connection area of the conductor pattern and its vicinity, as well as by the weakened part of the board, and the flip-chip This is to prevent the signal from being transmitted to the connection portion of the element.

以下、この発明を図示の実施例により詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

第1図および第2図はこの発明による混成集積回路装置
におけるフリツプチツプ素子1個の配置接続状態を示す
平面図および断面図である。
1 and 2 are a plan view and a sectional view showing the arrangement and connection state of one flip-chip element in a hybrid integrated circuit device according to the present invention.

この図において、1は絶縁基板、例えばグレーズ基板で
あり、その表面に導体パターン2としてフリツプチツプ
素子の接続端子に対応する接続領域(ランド部)2aと
これに接続される引出しリードパターン2bが形成され
ている。この導体パターン2は、基板1上にCr−Au
膜を蒸着し、それにフオトエツチングを施すことによつ
て作られる。ランド部2aと引出しリードパターン2b
の一部には、メツキ法によりNi2μ,Cu5μ、半田
15μが積層付着されている。ここで、基板1表面のガ
ラス層5のうち導体パターン2のランド部2aと、ラン
ド部2a近傍の引出しリードパターン2bとの周辺部分
(第1図中一点鎖線で囲んだ領域)は、脆化されている
。第2図中、5aが脆化されたガラス層部分を示してい
るこの基板1の部分的な脆化は、第1図中一点鎖線で囲
んだ領域のガラス層の露出している部分を除いて基板1
にマスクした状態で、基板1をフツ酸処理することによ
り達成される。そして、フリツプチツプ素子3、例えば
フリツプチツプ型ダイオードアレイを用意し、その接続
端子(バンプ)4を導体パターン2のランド部2bにフ
エイスダウンボンデイング法により接続した。一方、比
較のためにフツ酸処理を施してない基板上に同様に形成
した導体パターンに同じ条件でフリツプチツプ素子を接
続したものを用意した。
In this figure, reference numeral 1 denotes an insulating substrate, for example a glazed substrate, on the surface of which are formed a conductor pattern 2, a connection area (land portion) 2a corresponding to the connection terminal of the flip-chip element, and a lead pattern 2b connected to this. ing. This conductor pattern 2 is made of Cr-Au on the substrate 1.
It is made by depositing a film and photoetching it. Land portion 2a and drawer lead pattern 2b
2μ of Ni, 5μ of Cu, and 15μ of solder are layered and adhered to a part of the plate by plating. Here, in the glass layer 5 on the surface of the substrate 1, the peripheral portion of the land portion 2a of the conductor pattern 2 and the extraction lead pattern 2b near the land portion 2a (the area surrounded by the dashed line in FIG. 1) becomes brittle. has been done. In FIG. 2, 5a indicates the embrittled glass layer portion. This partial embrittlement of the substrate 1 is shown except for the exposed portion of the glass layer in the area surrounded by the dashed line in FIG. Board 1
This is achieved by treating the substrate 1 with hydrofluoric acid while masked. A flip-chip element 3, for example a flip-chip diode array, was prepared, and its connection terminal (bump) 4 was connected to the land portion 2b of the conductor pattern 2 by face-down bonding. On the other hand, for comparison, a flip-chip element was connected under the same conditions to a conductor pattern formed in the same manner on a substrate that had not been subjected to hydrofluoric acid treatment.

このようにして得られた2種類のサンプルについて外部
から与えられる歪に対するフリツプチツプ素子3の接続
部の信頼性を調べるために、各サンプルの絶縁基板に繰
返し歪をかけ、ダイオードのオープン発生率を比較した
。その結果、基板にフツ酸処理を施していないサンプル
では、ダイオードのオープン発生率が50%以上にも達
したのに対し、基板にフツ酸処理を施したサンプルでは
10%以下であつた。また、フリツプチツプ素子を基板
から強制的に剥離する実験を行なつたところ、基板にフ
ツ酸処理を施していないサンプルでは、フリツプチツプ
素子の接続端子が根元で切断されたのに対し、基板にフ
ツ酸処理を施したサンプルでは、ランド部下方のグレー
ズ層が共に剥離してきた。
In order to investigate the reliability of the connection part of the flip-chip element 3 against externally applied strain for the two types of samples obtained in this way, repeated strain was applied to the insulating substrate of each sample, and the open incidence rate of the diode was compared. did. As a result, in the samples whose substrates were not treated with hydrofluoric acid, the diode open occurrence rate reached over 50%, whereas in the samples whose substrates were treated with hydrofluoric acid, it was less than 10%. In addition, when we conducted an experiment in which we forcibly peeled a flip-chip device from a substrate, we found that in samples where the substrate was not treated with hydrofluoric acid, the connection terminals of the flip-chip device were cut at the root, whereas In the treated sample, the glaze layer below the land also peeled off.

さらに、基板を透明ガラス基板に代えて、前記実施例と
同様な工程を施して、基板裏面より観察したところ、フ
ツ酸処理された部分ではランド部および引出しリードパ
ターンの線に沿つてグレーズ層にクラツクが入つている
のが観察された。
Furthermore, when the substrate was replaced with a transparent glass substrate and the same process as in the previous example was performed, observation from the back side of the substrate revealed that in the areas treated with hydrofluoric acid, the glaze layer was formed along the land portions and the lines of the lead pattern. A crack was observed.

この場合、基板のフツ酸処理された部分に対応する導体
パターン部分に亀裂などの疲労の根跡が特に目立つこと
はなかつた。以上の実施例から明らかなように、この発
明による混成集積回路装置では、基板に生じた熱的、機
械的歪は導体パターンのフリツプチツプ素子接続領域お
よびその近傍の導体さらに基板の脆化させた部分によつ
て吸収されるので、フリツプチツプ素子の接続部に直接
伝達されない。
In this case, there were no particularly noticeable signs of fatigue such as cracks in the conductor pattern portion corresponding to the portion of the substrate treated with hydrofluoric acid. As is clear from the above embodiments, in the hybrid integrated circuit device according to the present invention, the thermal and mechanical strain generated in the substrate is applied to the flip-chip element connection area of the conductor pattern, the conductor in its vicinity, and even the embrittled portion of the substrate. , so it is not directly transmitted to the connections of the flip-chip device.

従つて、フリツプチツプ素子を多数装着した混成集積回
路基板をそのまま使用するような場合でも、接続部は基
板の熱的、機械的歪に対して破壊されるようなおそれが
なく、その信頼性が著しく向上する。熱的歪に対しては
、外部からの熱のみならずフリツプチツプ素子自身(多
くの場合半導体)の発生する熱による歪に対しても効果
があることは勿論である。また基板表面の脆化処理は、
基板表面部を除去して導体パターンを浮いた状態にする
わけではなく、脆化された層も導体パターンの支持体と
しては機能している。例えばフリツプチツプ素子をボン
デイングする際に当然導体パターンに力が加わるが、導
体パターンが蒸着膜やスパツタ膜など薄いものであつて
も、その下の脆化された層によつて支持されていて破壊
が防止される。なお、前記実施例ではグレーズ基板上に
薄膜技術による導体パターンを形成する場合の例につい
て述べたが、絶縁基板の材料、導体パターン形成技術は
これに限定されるものではない。
Therefore, even when using a hybrid integrated circuit board equipped with a large number of flip-chip elements, there is no risk that the connection parts will be destroyed by thermal or mechanical strain on the board, and its reliability is significantly improved. improves. Of course, it is effective against thermal distortion not only from external heat but also from heat generated by the flip-chip element itself (semiconductor in most cases). In addition, the embrittlement treatment of the substrate surface is
The conductive pattern is not removed by removing the surface of the substrate, but the embrittled layer also functions as a support for the conductive pattern. For example, when bonding a flip-chip device, force is naturally applied to the conductor pattern, but even if the conductor pattern is thin such as a vapor-deposited film or a sputtered film, it is supported by the embrittled layer underneath and is susceptible to breakage. Prevented. In the above embodiments, an example was described in which a conductor pattern was formed using a thin film technique on a glazed substrate, but the material of the insulating substrate and the technique for forming the conductor pattern are not limited thereto.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例の混成集積回路装置の要部
を示す平面図、第2図は第1図のX−X’線の断面図で
ある。 1 ・・・・・・絶縁基板、2・・・・・・導体パター
ン、3・・・・・・フリツプチツプ素子、4・・・・・
・接続端子。
FIG. 1 is a plan view showing essential parts of a hybrid integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line XX' in FIG. 1. 1...Insulating substrate, 2...Conductor pattern, 3...Flip chip element, 4...
·Connecting terminal.

Claims (1)

【特許請求の範囲】[Claims] 1 複数の突出した接続端子を有するフリップチップ素
子を前記接続端子に対応する部分に接続領域を有する絶
縁基板上の導体パターンに接続してなる混成集積回路装
置において、前記絶縁基板のうち前記導体パターンの接
続領域およびその近傍の導体の周辺部分を脆化させたこ
とを特徴とする混成集積回路装置。
1. In a hybrid integrated circuit device in which a flip chip element having a plurality of protruding connection terminals is connected to a conductor pattern on an insulating substrate having a connection region in a portion corresponding to the connection terminal, the conductor pattern of the insulating substrate 1. A hybrid integrated circuit device characterized in that a connection region and a peripheral portion of a conductor in the vicinity thereof are made brittle.
JP53022997A 1978-03-01 1978-03-01 Hybrid integrated circuit device Expired JPS5949719B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53022997A JPS5949719B2 (en) 1978-03-01 1978-03-01 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53022997A JPS5949719B2 (en) 1978-03-01 1978-03-01 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPS54115769A JPS54115769A (en) 1979-09-08
JPS5949719B2 true JPS5949719B2 (en) 1984-12-04

Family

ID=12098154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53022997A Expired JPS5949719B2 (en) 1978-03-01 1978-03-01 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5949719B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62199919A (en) * 1986-02-27 1987-09-03 Hino Motors Ltd Wall face temperature controller for piston combustion chamber

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4597177A (en) * 1984-01-03 1986-07-01 International Business Machines Corporation Fabricating contacts for flexible module carriers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62199919A (en) * 1986-02-27 1987-09-03 Hino Motors Ltd Wall face temperature controller for piston combustion chamber

Also Published As

Publication number Publication date
JPS54115769A (en) 1979-09-08

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