JPS5950126B2 - automatic gain control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay-type automatic gain control (hereinafter abbreviated as AGC) circuit.

Conventionally, this type of circuit has been widely used in multi-stage connected high-frequency amplification circuits and intermediate-frequency amplification circuits. It was difficult to achieve uniform characteristics through adjustment.

This will be explained using FIGS. 1 and 2.

FIG. 1 is a block diagram showing an example of the use of a conventional delay-type AGC circuit in a television receiver circuit.

The outline of its operation is that after the television signal received by antenna 1 is selected by tuner 2 and converted to an intermediate frequency,
, second and third intermediate frequency amplifiers 3, 4. 5, the output is detected by a detector 6, and then output to an output terminal 7.

This detection output is normally sent to a video amplification stage, a sync separation stage, a color signal processing stage, an audio signal processing stage, etc. (none of which are shown), but it is also sent to the tuner 2 and the first and second intermediate frequency The voltage is also input to a first comparator 8 for gain control of the amplifiers 3 and 4, and compared with the voltage of a reference voltage source 9.

The first comparator 8 generates an output according to the detected output and charges the capacitor 10.

Here, if it is desired to extract only the synchronization signal as the output of the comparator 8, a gate is included.

The terminal voltage generated at the capacitor 10, that is, the AGC voltage, is transferred to the second, third, and fourth comparators 11. 12. 13 and are respectively input to reference voltage sources 14. 15. The outputs of these comparisons become signals for controlling the gains of the tuner 2 and the first and second intermediate frequency amplifiers 3 and 4.

Note that the input of each comparator does not necessarily need to be taken out from the capacitor 10, but may be taken out from the output of another comparator.

In such a configuration, in order to perform delayed AGC operation by changing the respective AGC start levels, the voltages of the reference voltage sources 14, 15, and 16 must be made different, or the voltage of the compared signal must be divided. It must be made different by adjusting the level or shifting the level.

This delayed AGC operation will be explained using FIG. 2 showing the circuit configuration of the first and second intermediate frequency amplifiers 3 and 4 and the second and third comparators 11 and 12.

Note that in this figure, the input of each comparator is taken out from the output of other comparators.

First, all intermediate frequency amplifiers include two differentially connected transistors, and gain control is performed by changing the operating resistance of a diode connected to the emitter terminal of each transistor.

To explain in detail, the output of the tuner 2 is band-adjusted by the tuning circuit 21 in the first intermediate frequency amplifier 3, and then sent to the emitter follower transistor 26 via the coupling capacitor 22.
input to the base of

This transistor 26 is a differentially connected transistor 31
．． There is an emitter follower transistor 27 whose base terminal is AC grounded via a bypass capacitor 23 in order to provide input to one transistor 31 of 32 and to provide input to the other transistor 32, and these two transistors 26 Each of the bases of .27 has a resistor of 24
．． A bias voltage ° is supplied from a bias supply circuit 28 via 25.

That is, the outputs of the transistors 26 and 27 have their collector terminals connected to the power supply 60 via load resistors 37 and 38, respectively, and their emitter terminals connected to the resistors 33. and 34
A diode 3 which is grounded through the diodes 3 and whose terminals of the same polarity are connected so that they are oriented in opposite directions.
Transistor 3 differentially connected via 5 and 36
1 and 32 bases.

The collector outputs of the transistors 31 and 32 are input to the bases of emitter follower transistors 40 and 41 in the second intermediate frequency amplifier 4, respectively, and these emitter outputs are input to the bases of the emitter follower transistors 40 and 41 in the first intermediate frequency amplifier 3.
and 32, they are respectively input to the bases of differentially connected transistors 44 and 45.

Further, the collector outputs of transistors 44 and 45 are both sent to a third intermediate frequency amplifier 5 for amplification, and the output of this amplifier 5 is detected by a detector 6 and then sent to a first comparator 8 to be used as a reference. It is compared with the voltage of voltage source 9.

The capacitor 10 is charged by the output of the comparator 8.
The AGC voltage generated at the emitter terminal is resistor 55, 56.
, 57 to the base of the emitter follower transistor 53 which is grounded.

The emitter output of this transistor 53 has a collector terminal connected to the diodes 48 and 4 in the second intermediate frequency amplifier 4.
9, the base-emitter voltage VBE1 of the transistor 54 is (
Usually compared to 0.5 to 0.7 (V)).

The transistor 54 and the resistor 57 constitute a second comparator 11, in which the pace emitter voltage VBEI serves as a second reference voltage in place of the reference voltage source 14 of FIG.

Similarly to the second comparator 11, the voltage extracted from the intermediate node between the resistors 55 and 56 has a collector terminal connected to the intermediate node 75 between the diodes 35 and 36 in the first intermediate frequency amplifier 3 and the resistor 39. A transistor 5 connected to a power supply 60 and having an emitter terminal grounded via a resistor 59.
8 and is compared with the base-emitter voltage VBH3 of this transistor 58.

Here, the transistor 58 and the resistor 59 constitute the third comparator 12, and the base-emitter voltage VBE2 is the first
This is a third reference voltage that replaces the reference voltage source 15 in the figure.

Furthermore, the collector output of the transistor 54 is sent to the fourth comparator 13, where it is compared with the voltage of the reference voltage source 16.

Now, to explain the AGC operation in these circuits, first, the input to the intermediate frequency amplification stage increases, and as the output of the detector 6 increases accordingly, the output of the comparator 8 also increases.

Therefore, the AGC voltage generated in the capacitor 10 also increases, and the emitter voltage of the transistor 53 increases.
When the base-emitter voltage VBEI of the transistor 54, which is the reference voltage, is exceeded, the collector current of the transistor 54 increases.

As a result, the resistor 52 in the second intermediate frequency amplifier 4
Since the voltage drop at node 76 increases and the voltage at node 76 decreases, the current flowing through diodes 48 and 49 decreases, and as a result, the operating resistance of diodes 48 and 49 increases, and the gain of second intermediate frequency amplifier 4 becomes It gets lower.

On the other hand, in the first intermediate frequency amplifier 3 as well, the voltage at the intermediate node between the resistors 55 and 56, which is the input of the third comparator 12, becomes high, so the gain becomes low due to a similar operation.

Conversely, when the output of the tuner 2 becomes small, that is, when the output of the detector 6 becomes small and the AGC voltage generated at the capacitor 10 becomes small, the collector currents of the transistors 54 and 58 decrease, and the currents at the nodes 76 and 75 decrease. Since the voltage increases, the current flowing through the diodes 48, 49 and 35, 36 increases, the operating resistance decreases, and the gains of the intermediate frequency amplifiers 4 and 3 increase.

Note that the output of the comparator 13 controls the gain of the tuner 2.

By the way, the transistor 5 constituting the second comparator 11
The emitter voltage of the transistor 53 is applied to the base of the transistor 4, and the emitter voltage of the transistor 53 is applied to the base of the transistor 58 forming the third comparator 12. Transistor 54 starts operating earlier than transistor 58 with respect to the output, ie, AGC voltage.

Therefore, the two intermediate frequency amplifiers 3 and 4 have different AGC start levels relative to the input level of the intermediate frequency amplifiers, and a delayed AGC operation is performed.

Further, the values of the resistors 39 and 52 are set so that the maximum gain of the two intermediate frequency amplifiers 3 and 4 is obtained when the transistors 58 and 54 are cut off and the voltages at the nodes 75 and 76 reach the maximum voltage. ing.

However, such conventional AGC circuits have the following drawbacks.

First, the base-emitter voltage VBE of the transistor is used as the reference voltage of the first comparator, but since this voltage has a large temperature coefficient, the AGC start level may vary with respect to the input level of the intermediate frequency amplifier due to temperature changes. big.

Second, since the bias voltage supplied from the bias supply circuit 28 is used by feeding back the DC component from the third intermediate frequency amplifier 5, when the DC loop gain changes due to AGC operation, the bias voltage also changes, which causes the diode The current also fluctuates.

Thirdly, for example, in the first intermediate frequency amplifier 3, the emitter current of the transistor 31 is influenced by the temperature coefficient of the base-emitter voltage of the two transistors 26 and 31, whereas the current of the diode 35 is influenced by the temperature coefficient of the base-emitter voltage of the two transistors 26 and 31. It is not complementary because it is affected only by the temperature coefficient of its own forward voltage (equal to the base-emitter voltage of one transistor), and as a result, the current flowing through the diode 35.36 changes with temperature changes. However, the gain also changes.

For the reasons described above, variations occur in the maximum gain and AGC delay point as a differential amplifier, making it difficult to obtain an AGC circuit that is uniform and has desired characteristics even without adjustment.

In contrast, an object of the present invention is to provide an AGC circuit that makes it possible to eliminate variations in the maximum gain of a differential amplifier and AGC delay point by simple means.

According to the present invention, the first and second amplifiers each including a circuit in which two diodes connected in opposite directions to each other are connected between the emitter terminals of two differentially connected transistors as components of a multistage amplifier. and a circuit for obtaining the AGC voltage from the output of the multistage amplifier.
In the GC circuit, means for supplying a current that varies depending on the AGC voltage to respective connection points of two diodes in the first and second amplifiers, and one of the first and second amplifiers. means for shunting the current flowing into the connection point of the two diodes at
By changing the operating resistance of each of the diodes with a current that changes depending on the AGC voltage,
An AGC circuit is obtained, characterized in that the gains of the first and second amplifiers are controlled with a delay.

An embodiment of the present invention will be described below with reference to FIG.

FIG. 3 is a diagram showing the circuit configuration of the main parts of the delay AGC circuit when the present invention is applied to a television receiver circuit, similar to the example shown in FIG. , the detector 6, the comparator 8, the capacitor 10, etc. are the same as in FIG. 2, so their explanations are omitted. The following describes how the operating resistances of the diodes 35, 36, 48, and 49 in the second intermediate frequency amplifier are controlled, and the operation of such current sources is delayed.

First, the AGC voltage generated in the capacitor 10 is connected to the emitter terminal via the resistors 63 and 64, and the resistor 6
The signal is input to the base of the transistor 61 of the two transistors 61 and 62 which are commonly grounded through the transistor 5 and differentially connected.

A transistor 67 whose base and collector are short-circuited;
A transistor 6 whose collector terminal is connected to an intermediate node 76 between diodes 48 and 49 in the second intermediate frequency amplifier 4
8, and the intermediate node 75 between the diodes 35 and 36 in the first intermediate frequency amplifier 3 whose collector terminals are also connected to the shunt resistor 7.
The emitter terminals of the transistors 69 are connected to the power supply 7 through resistors 70, 71, and 72, respectively.
4, and their base terminals are connected in common to form a current mirror circuit.

The collector terminal of the transistor 62 is connected to the collector side of the transistor 67 which serves as the input terminal of this current mirror circuit.

The maximum current flowing through the current mirror circuit is determined by the emitter resistor 64 of the transistor 62, the common resistor 65, and the reference voltage source 66 connected to the base terminal of the transistor 62. When the collector current of the transistor 62 is maximum, the transistors 68 and 69 The collector current of the diodes 48, 49 and 35, 36 becomes maximum, and the operating resistance becomes the minimum, so that the gain of the differential amplifier in each intermediate frequency amplifier becomes maximum. The current of each part is set so that

Here, if the two differential amplifiers in the first and second intermediate frequency amplifiers have the same constant number, the currents flowing through the diodes 48, 49 and 35, 36 required to provide the maximum gain are the same value, Therefore, the collector current of the transistor 69 in the current mirror circuit needs to be larger than the collector current of the transistor 68 by the amount flowing through the shunt resistor 73.
The emitter area ratio of 7.68.69 and/or the emitter resistance ratio of 70, 71.72 is selected as required.

Now, in AGC operation, first, the input level of the intermediate frequency amplifier increases and the detected output increases, and as the AGC voltage generated in the capacitor 10 by the comparator 8 output increases accordingly, the collector current of the transistor 62 decreases. Therefore, the collector currents of the transistors 68 and 69 also decrease, and the currents flowing into the diodes 48, 49 and 35, 36 also decrease, and the operating resistance of each diode increases, so that the amplification gain of the differential amplifier decreases.

Conversely, the output of the tuner 2 becomes smaller, the detection output becomes smaller, and the A generated in the capacitor 10 due to the output of the comparator 8 becomes smaller.
When the GC voltage decreases, the collector current of transistor 62 increases, and each diode 48, 49 and 35, 36
The current flowing into the amplifier also increases, lowering the operating resistance and increasing the amplification gain.

FIG. 4 is a diagram showing the relationship between the AGC voltage VA generated at the capacitor 10 and the current Id flowing through each diode in the intermediate frequency amplifier. The current flowing into varies according to line 101.

As is clear from this figure, the timing at which the current flowing through the diodes in the two amplifiers starts to increase is different, and this is because a portion of the collector current of the transistor 69 is shunted to the shunting resistor 73.

That is, when the collector current of the transistor 69 is small, all of this current flows through the resistor 73 and the diode 3.
5.36 is a cutoff, and the current flowing through the diodes 35 and 36 increases after the collector current of the transistor 69 becomes larger than the current shunted to the resistor 73 (which will be described later, but is considered to be a constant current). .

By providing such a shunting means, delayed AGC is applied to the two amplifiers, and a wide AGC is applied to the input.
You can get a range.

Further, after the diodes 35 and 36 are turned on, the potential at the node 75 is higher than the emitter voltage of the transistors 31 and 32 by the forward voltage of the diode, and the DC voltage at this point is higher than the voltage fluctuation. Because it is sufficiently high, the relative change is small and this allows a nearly constant current to flow through the resistance 73.
flows to

On the other hand, in the example shown in FIG. 2, the DC voltage at the node 75 is lower than the voltage variation at the resistor 39, so the relative variation is large and a constant current cannot be obtained.

Note that by inserting a resistor, a diode, etc. in place of the resistor 73, it is possible to temperature compensate the current flowing through the diodes 35 and 36, and it is best to configure this as a constant current source as described above. However, in this case, the number of elements increases.

As is clear from the above, in the present invention, as a driving method for the diode in the differential amplifier, current driving is used as opposed to voltage driving in the example of FIG. Since the flowing current is determined only by the collector current of the transistor 62, variations in the maximum gain and AGC delay point due to base bias fluctuations and temperature fluctuations in the input transistor of the amplifier will not occur as in conventional examples. Since the delay point can also be set by selecting one resistive element, the circuit configuration becomes simple.

As described above, according to Honyoma, it is possible to easily achieve this without variations in maximum amplification gain or AGC delay point by using simple means, and as a result, an AGC circuit having uniform characteristics can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional delay-type AGC circuit, and FIG. 2 is a diagram showing the circuit configuration of its main parts.
Figure 3 is a diagram showing the circuit configuration of the main part of a delay type AGC circuit which is an embodiment of the present invention, and Figure 4 is a diagram showing the AGC voltage and the current flowing through the diode to explain the delay automatic gain control according to the present invention. FIG. The main reference numbers in the drawing are as follows: 2: Tuner, 3, 4
, 5: Intermediate frequency amplifier, 6: Detector, 8.11, 12,
13: Comparator, 9, 14, 15. 16, 66: Reference voltage source, 10: Capacitor, 21: Tuning circuit, 26. 27
．． 40. 41゜53: Emitter follower transistor, 31, 32. 44, 45: Amplification transistor, 28
: Bias supply circuit, 35, 36, 48, 49: Diode, 60, 74: Power supply.

Claims (1)

[Claims] 1 A first and second amplifier each including a circuit in which two diodes connected in opposite directions to each other are connected between the emitter terminals of two differentially connected transistors as a component of a multistage amplifier, and the multistage amplifier In an automatic gain control circuit including a circuit that obtains an automatic gain control voltage from an output of an amplifier, a current that varies depending on the automatic gain control voltage is supplied to each connection point of two diodes in the first and second amplifiers. means for
and means for shunting the current flowing into the connection point of the two diodes in one of the second amplifiers, and changing the operating resistance of each of the diodes by the current that changes according to the automatic gain control voltage. An automatic gain control circuit characterized in that the gains of the first and second amplifiers are delayed-controlled.