JPS5951002B2 - Sequence controller with counter function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence controller having a counter function.

Generally, in a sequence controller, sequence control information is read out cyclically.

Therefore, in order to provide a counter function by a program, it is necessary to detect a change in the logic value of the input signal to be counted from one operation cycle before, and then create a counter that reads only the detection signal of the change in logic value at each operation cycle. It counts based on the command, compares it with the count setting value, and outputs a count-up signal only when they match. The count value of the logical value change of the input signal and the counter setting value are generally stored in a dedicated register used for the counter, and the maximum number of usable counters depends on the capacity of this register. The number will be limited.
Therefore, depending on the sequence control object, a large number of counters may be required, but it is uneconomical to provide a large capacity register to satisfy the expected maximum number of counters. However, if the capacity of the register is made small, it may not be possible to secure the required number of counters, which may cause problems in reprogramming. In addition, in the case where count values and set values are stored in such a dedicated register, the designated address for the counter is a specific address, which is different from the input and output device addresses for general sequence control.

Therefore, it is more advantageous in terms of maintenance to allocate systematic input and output addresses to related sequence control systems, but it has been impossible to allocate systematic addresses to counters. In order to eliminate such conventional drawbacks, the present invention stores count values and set values in a sequence program memory, so that the number of required counters can be increased or decreased arbitrarily, and the counters are also related to the control system. Input signal states to be counted, count-up signals, etc. are stored and held in external storage elements that can be addressed in the same way as input and output devices so that arbitrary addresses can be assigned.

The present invention will be explained below using examples.

In FIG. 1, a schematic configuration of a sequence controller 100 is shown. 10 is a memory in which sequence control information is stored, 11 is a program counter that specifies the address of the memory 10, 12 is a memory gate, 13 is an instruction word register in which an instruction code is preset, and 14 is an address in which address data is preset. 1 is a register, 15 is a decoder for decoding the instruction code, 16 is an arithmetic control circuit, 1
7 is a data bus, 18 is an input circuit to which input devices 18a such as limit switches and push button switches are connected, and 19 is an output circuit to which output devices 19a such as output relays and solenoids are connected.

The input circuit 18 is composed of a signal conversion circuit 20 and a selection circuit 21, and converts the signal state of the input device 18a into the signal conversion circuit 20.
0, the selection circuit 21 selects one signal specified by the address data, and supplies it to the arithmetic control circuit 16 through the signal line 22. The output circuit 19 is composed of a signal holding/converting circuit 23, a decoding circuit 24, and a selection circuit 25. The operating state of the output device 19a is stored and held in the signal holding/converting circuit 23, and the decoding circuit 24 addresses this memory holding element. It is specified by data and set to a set state or a reset state by output signals SON and SOF given from the arithmetic control circuit 16. This signal holding conversion circuit 23 constitutes the external storage element. Further, the selection circuit 25 selects one of the signal holding elements and outputs its signal state to the signal line 22. As shown in FIG. 2, the sequence control information stored in the memory 0 consists of an instruction code and an address code. The instruction code specifies the content of the operation, and the address code specifies the input device 18a or output device 19a to perform the operation. The instruction code includes test instructions (TNA.TFA, TN
O. TFO. TNE. TFE), an output command (YON), and a counter command (CTR), and each command code is discriminated by a decoder 15 and controls the calculation contents of the calculation control unit 16.

26 is a crotter control circuit that generates timing pulses for performing calculations to be described later.

As shown in FIG.
Controlled by CL6. Memory 10 by CL1
is read out, and the data read out to the instruction register 13 and address register 14 are preset at CL3. If the instruction code is a test command, the signal state (the signal state of the input device specified by the address data) 8a given through the signal line 22 at CL5 is logically operated by the arithmetic control circuit 16, and the operation result is is stored in a test flag, which will be described later. If the instruction code is an output instruction, CL5 outputs an output signal S according to the operation result.
ON and SOF are applied to the output circuit 19 to energize or de-energize the output device 19a specified by the address data. By the way, if the instruction code is a counter instruction (CTR), the tally control circuit 26
Following L6, CL "~CL6" is generated, and one calculation cycle is performed with this series of taroks CL1 to CL6 and CL "~CL6".

Then, reading of memo 1 river 0 is performed again at CL1'', and C
The data read at L3'' is stored in A register 2 shown in FIG.
7 and B register 28. The A register 27 has a preset count value, and the B register 2
8 is preset with the current count value, and both registers 27
, 28 are compared by a comparator 29, and a count-up is detected. The B register 28 receives a count signal every time the arithmetic control circuit 16, which will be described later, detects a change in the logical value of an input signal to be counted.
At clock CL5'', the current value is counted up. Also, at clock CL5'', the contents of the B register 28 are written into the memory 10, and stored there until the counter instruction is read out again after one scan. The counter function is typically illustrated as in FIG.

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Todoroki f Todoro d6V-Vitov Furthermore, a circuit for clearing this counter is shown in FIG. 6, and when programmed, it becomes as shown in Table 3.

As can be seen from these program examples, three addresses, Y1, Y1+1, and Y1+2, are used for one counter function, and the input signal to be counted is stored in the address Y1 given with the counter instruction CTR. However, a signal for clearing the counter is stored in Y1+1, and these are provided as external storage elements.

This makes it possible to assign the counter instruction as well as the count up and counter clear addresses to any address related to the control system.The operation of the program shown in Table 1 can be briefly described as follows. n
The program TNAX1 read from the address is the input signal
This is an instruction for logically calculating whether or not 1 is on. The calculation control circuit 16 performs this calculation and stores the calculation result in the test flag.

The CTRY1 instruction at address n+1 is a counter instruction, and the output device Y1 is controlled at the timing of the clock CL5 in accordance with the calculation result of the input signal X1 stored in the test flag. That is, if the input signal X1 is on, Y1 is also controlled to be on, and if X1 is off, Y1 is also controlled to be off. On the other hand, the arithmetic control circuit 16 takes in the signal state of Y1 before changing to the on or off state, calculates the logical product of the taken-in signal of Y1 and the input signal X1, and changes the logical value (from off to on). change) is detected and stored in the test flag. In the case of a power count command, a clock CL "~CL6" is also generated following the clocks CL1 to CL6.
Reading of address n+2 is performed by clock CL'.
The count setting value 10 and the current value (initial value is 0) are stored in this memory address, and these values are read out and the setting value is transferred to the A register 27 and the current value to the B register 28 by the clock CL3''. If there is a logic value change detection signal from "0" to "1" stored in the test flag, a count signal is given to the B register 28 to increment the current value by one. Further, if there is no logic value change detection signal, no count signal is given. The contents of both registers 27 and 28 are compared by the comparator 29, so if a match signal is output, the first designated address Y is determined by the clocks CL1'' and CL3'' given to the address register 14, as will be described later.
The output device Y1+2, which has added 1 to +2, is set on to hold the count-up signal. At the same time, A. The contents of B registers 27 and 28 are written to memo 1 and 0. Therefore, if a matching signal is not output, output device Y1+2 will not be turned on and A. Only the contents of the B registers 27 and 28 are written. When the specified address Y1 is incremented by 1 by the clock CL1'', Y1+1 is specified in the address register 14.

This output device Y1+1 is set to ON when a condition for clearing the counter is satisfied by the program shown in Table 3. The arithmetic control circuit 16 calculates the signal state of Y1+1 at the clock CL3'', and controls whether or not to clear the contents of the B register 28 at the clock CL4'' based on the calculation result. Furthermore, the address register 14 is set to the specified address Y1+1 by CL4''.
is +1 and designates Y1+2. This specified address Y1
If a match signal is output from the comparator 29 at +2 as described above, a count-up signal is stored. Therefore, the system controlled by count-up. The sequence must address Y1+2 as shown at address m in Table 2 to test whether the count up signal is on. Next, the specific configuration of the arithmetic control circuit 14 will be explained with reference to FIG. This arithmetic control circuit 14 receives the test command TNA. T.F.A. TNO. TFO, TNE
．． AND operators 30, 31 and OR operator 3 that perform AND operations and OR operations on input signals based on TFE, and detect changes in logical values of input signals to be counted.
2, 33, and the output of this arithmetic unit 1, the output signal S
It is composed of a circuit 34 that outputs ON and SOF, a circuit 35 that outputs a count signal, and a circuit 37 that outputs a signal that clears the current count value, and the detection of the logical value change is performed by these circuits.
The logical product operators 30 and 31 are mainly composed of D flip-flops 40 and 41 and NAND gates 42 and 43.

The input signal applied to the terminal 39 connected to the signal line 22 is applied to the NAND gate 42 via the AND gates 4, 4 and the OR gate 45, and is ANDed with the signal of the D flip-flop 40 that stores the operation result. The result is triggered by the clock CL5 and sent to the D flip-flop 4 again only when the test command TNA is given.
Stored as 0. Further, the input signal is applied to the NAND gate 43 via the inverter 46, and is ANDed with the signal of the D flip-flop 41 that stores the operation result, and the result is used as the clock signal only when the test instruction TFA is applied. It is triggered by CL5 and stored in the D flip-flop 41 again. When the input signal is on, a signal with a logic value of "1" (hereinafter simply referred to as "signal") is input as is to the NAND gate 42, so that a logic value of "0" is input to the D terminal of the D flip-flop 40. Even if a signal (hereinafter simply referred to as signal "0") is applied and this flip-flop is triggered by a test command, the reset state is maintained and the establishment of the logical product is stored. If the input signal is off, a signal "1" is applied to the D terminal, and the D flip-flop 40 is set to store that the logical product does not hold. Further, when the input signal is off, the signal "1" inverted by the inverter 46 is input to the NAND gate 43, so that the signal "0" is given to the D terminal of the D flip-flop 41, and the reset state is maintained. Memorize logical product establishment.
If the input signal is on, a signal "1" is applied to the D terminal, the D flip-flop 41 is set, and the logical product failure is stored. That is, the AND operator 30 calculates whether the input signal is on, the AND operator 31 calculates whether the input signal is off, and the operation results of both the operators 30 and 31 are sent to the AND gate 47. It is output from OR operator The OR operators 32 and 33 are D flip-flops 50,
It mainly consists of 51 and OR Gates 52 and 53.

The input signal applied to the terminal 39 is applied to the OR gate 52, where it is logically ORed with the signal of the D flip-flop 50 that stores the operation result, and the result is used as the test instruction T.
No. D flip-flop 5 given TNE
Stored as 0. The input signal is also applied to the OR gate 53 via the inverter 46, where it is logically ORed with the signal of the D flip-flop 51 that stores the operation result, and the result is used as the test instruction TFO. If TFE is given, it is stored in the D flip-flop 51. When the input signal is on, the signal "1" is input as is to the OR gate 52, and the signal "1" is applied to the D terminal of the D flip-flop 50 via the AND gate 54, thereby issuing the test command TN.
When triggered by O or TNE, the D flip-flop 50 is set and stores the establishment of the OR. If the input signal is OFF, a signal "0" is applied to the D terminal, and the D flip-flop 50 maintains the reset state and stores that the logical OR is not established. Further, when the input signal is off, a signal "1" inverted by the inverter 46 is input to the OR gate 53, and the AND gate 55 is input to the D terminal of the D flip-flop 51.
The D flip-flop 51 is set by applying a signal flip ``1'' via the test command TFO or TFE, and stores the establishment of the logical sum. If the input signal is on, a signal "0" is applied to the D terminal, and the D flip-flop 51 maintains the reset state and stores that the logical OR is not established. That is, the OR operator 32 calculates whether the input signal is on, the OR operator 33 calculates whether the input signal is OFF, and the operation results of both the operators 32 and 33 are sent to the OR gate 56. The logic transfer circuit 6 which will be output and will be described later
given to 0. Logic Transfer Circuit Logic transfer circuit 60 includes AND gates 61 . or gate 45
When the logic transfer command SIFT is given, the signal "0" inverted by the inverter 62 is input to the AND gate 44 to block the signal given from the terminal 39, and the AND gate 61 receives the signal. "1" is input, and the signal of the operation result of the logical sum operators 32 and 33 is input to the AND gate 42 via the OR gate 45.

As a result, the AND operation result stored in the D flip-flop 40 and the logical sum operation result are computed and stored in the D flip-flop 40. Such logical transfer occurs at clock CL6, and D flip-flop 40
A trigger pulse is applied to the T terminal of the D flip-flop 50, through an AND gate 63 and an OR gate 64.
The T terminal of 51 has an AND gate 65 and an OR gate 66.
via and gate 67, or gate 68,6
A trigger pulse is provided via 9.

And at the D terminal of the D flip-flop 50, 5],
When the logic transfer command SIFT' is applied, the signal ``0'' is inputted through the AND gate 70 and the inverter 71. Since the signal ``0'' is applied from the AND gates 54 and 55, both flip-flops 50 and 51 are reset. Ru. As a result, when the logic is transferred when the logical sum is established, the D flip-flop 40 is kept in a reset state and the fact that the logical sum is satisfied is stored, and the D flip-flops 50 and 51 are reset. Further, in the logic transfer when the logical sum does not hold, the D flip-flop 40 is changed to the set state to store the logical AND failure, and the D flip-flops 50 and 51 are reset. Output determination circuit The output determination circuit 34 is an AND gate 4 that outputs the calculation result.
7 output signal FT, output command YON, and counter command CT
R is input, and the output control signal SON is output according to this signal FT.
Or output SOF, OR gate 71, 7
4, 75, and gate 72, 73, 81, 82
, an inverter 76, when the signal FT is "1", that is, the logic is established, the signal SON is output, and when the signal FT is "0", that is, the logic is not established, the signal SO is output.
F is now output.

Logic value change detection operation Next, the operation of detecting a logic value change of the input signal X1 to be counted will be explained.

As shown in FIG. 8, the scanning cycle for scanning the memory 10 is much shorter than the on/off time of the input signal X1, so it is necessary to generate a count signal only at the rising edge of the input signal X1 and count this signal. Must be. The logical operators 40 and 51 calculate and detect that the count signal is turned off at time t1 and turned on at time t2 as a condition for issuing such a count signal. That is, t
When the test instruction TNAX1 at address n is executed at one point in time, since the input signal X1 is off, the signal "O" is sent to the NAND gate 42 via the terminal 39 in FIG.
is given to the D terminal of the D flip-flop 40.
1" is applied and set, and the signal FT becomes "O". 1 Subsequently, when the counter instruction CTRY1 at address n+1 is executed, the signal FT is inverted by the inverter 76, and the signal "1" is input to the AND gate 73, and the OR gate 7
The output signal SOF is outputted through the output circuit 5, and Y1 of the output circuit 19 is inactivated.

Y1 immediately before this Y1 is deenergized is t. This means that the state of the input signal X1 at the time is stored, and this signal is inputted as a signal "1" to the OR gate 53 via the inverter 46. Then, the D flip-flop 5] is set, and the output terminal Q on the set side is connected to an OR gate 56, an AND gate 61 . A signal “1” is input to the NAND gate 42 via the OR gate 45. In addition, and gate 61
The transfer command SIFT given to the counter command CTR and the test command TNE. If TFE is given, the signal “
1”. Since the D flip-flop 40 has already been reset to 1 at the time of execution of the n address, the NAND gate 42 outputs a signal "1", and the D flip-flop 40 outputs a signal "1".
0 keeps the set state. That is, t. Input signal at time and t1
This means that the logical product of the input signals at the time is calculated and it is determined that the logic does not hold. Therefore, the signal FT becomes "0",
Since the AND gate 77 is not opened, no count signal is output from the circuit 35 that generates the count signal. However, at time t2 after one scanning, the input signal
T becomes "1" and Y1 of the output circuit 19 is energized. Since Y1 immediately before being energized is deenergized, the signal "0"
'' is applied to the terminal 39, and the signal 11'', which is inverted by the inverter 46, is input to the OR gate 53, and the signal ``1'' is applied to the D terminal of the D flip-flop 51 to set it. and logic transfer circuit 60 via OR gate 56.
And Gate 61. A signal “1” is input to the NAND gate 42 via the OR gate 45. Since the D flip-flop 40 is in the reset state, the signal applied through the logic transfer circuit 60 also maintains the reset state and the logic is established. As a result, the signal FT becomes "1", and the signal "1" is applied to the AND gate 79 via the AND gate 77, and this AND gate 79 receives the inverted signal of the coincidence signal A≦B and the clock signal CL4''. Ruand Gate 78
When outputs the signal "1", it outputs a count signal, which is applied to the count terminal of the B register 28 via the OR gate 80 and counted. In this way, the count signal will not be output in any subsequent scanning cycles from t3 to t11, and will be output again only at time t12. Generation of clear signal When the memory element Y1+1 designated by the address register 14 being incremented by 1 by the clock CL is turned on, the clear signal is generated by the AND gate 8 of the circuit 37.
It is output from 7.

Whether or not Y1+1 is on is determined in the calculation cycle CL3'' of the counter instruction. That is, the signal state of Y1+1 is given to the OR gate 53 via the signal line 22, the terminal 39, and the inverter 46, and if it is on, In this case, a signal “0” is applied to the D terminal of the D flip-flop 51.
is given, and even if it is triggered by clock CL3'', it remains in the reset state. Therefore, the signal ``is output from output terminal Q''.
When the clock CL4'' is applied, the signal ``1'' is applied to the clear terminal of the B register 28 through the AND gate 87. If Y1+1 is off, the D flip-flop 51 is set and the output terminal Q becomes a signal "0", so the B register 28 is not cleared. As explained in detail above, in the present invention, changes in the logical value of the input signal to be counted are detected and counted, this counted value is compared with a set value, and a count up signal is output only when they match. However, since the count value and set value are stored in the sequence memory, the number of counters can be set arbitrarily within the remaining area of the memory, and the maximum number of counters can be set depending on the hardware configuration. There are no restrictions on the number.

In addition, since the on/off state of the input signal to be counted, the counter reset signal, and the count up signal are stored in an external storage element, they can be assigned to any address of the external storage element during counter control.
Since the addresses can be unified according to the control system, there is an effect of increasing the advantage in terms of maintenance.

Further, since the counter reset signal and count up signal are each designated and stored at a specific address of the output circuit 19, there is an advantage that a counter reset program or a program based on count up can be programmed completely separately from the counter instruction. be.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram showing a schematic configuration of a sequence controller, FIG. 2 is a diagram showing the style of instruction words stored in memory, and FIG.
The figure shows a time chart of the calculation cycle and counter cycle. Figures 4, 5, and 6 are diagrams of the counter function shown by a relay circuit. Figure 7 is a circuit showing the specific configuration of the calculation control circuit. FIG. 8 is a time chart showing the relationship between the input signal and the count signal. 10...Memory, 11...Program counter, 13...Instruction register, 14...
... Address register, 16 ... Arithmetic control circuit, 18 ... Input circuit, 19 ... Output circuit, 27 ... A register, 28 ...・・・・・・
B register, 29... Comparator, 30, 31.
...Logic product operator, 32, 33...Logic sum operator, 34...Output judgment circuit, 35...
. . . Count signal output circuit, 36 . . . Clear signal output circuit.

Claims (1)

[Scope of Claims] 1. In a sequence controller that performs sequence control of a controlled object by cyclically reading out preprogrammed sequence control information from a memory 10, a counter command (C
At the initial stage of execution of RT), the count setting value stored in the memory is preset in the first register 27, and the count value stored in the memory 10 is preset in the second register 2.
8; second means for storing the count value of the second register 28 in the memory at the final stage of execution of the counter instruction; a comparator 29 for comparing the values of both registers; an external first storage element (Y_1) that stores the logic state of the input signal that can be specified by the counter instruction and is to be counted;
) detects a change in the logic value of the input signal to be counted and increases the count value of the second register by 1, and the count is increased by the match signal from the comparator 29. A sequence controller with a counter function and an external second storage element (Y_1_+_2) in which a signal is set. 2. The logic value change detection circuit includes a first control circuit 40 that temporarily stores the logic state of the input signal to be counted, and a logic value of the first storage element immediately before the logic value of the first storage element is inverted by the first control circuit 40. A second signal is input and temporarily stored.
a third control circuit 60 that performs a logical operation on the logic value input to the second control circuit 51 with the input signal and stores the result in the first control circuit 40; 2. The sequence controller with a counter function according to claim 1, further comprising a fourth control circuit (35) that determines the calculation result stored in the control circuit (40) and adds one to the count value of the second register.