JPS5951216B2 - Load switching circuit for multiple inverters - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a load switching circuit for multiple inverters that switches the output of multiple inverters to drive a load such as a bobbin winding induction motor. The purpose of the present invention is to provide a load switching circuit for multiple inverters, which does not become impossible to drive, allows synchronized load switching to be performed extremely easily, and is suitable for load switching of multiple inverters. .

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a schematic configuration diagram of a load switching circuit for multiple inverters according to the present invention. In the figure, 30 is a voltage setting device for a first oscillator 20 such as a 10 beam/f converter, and 30 is a voltage setting device for a first oscillator 20,
40 is a first inverter' which drives a load 50 such as a bobbin winding induction motor based on the output of the first ring counter 30.

Similarly, 110 is a voltage setting device for the second oscillator 120;
0 is a second ring counter, 140 is a second inverter, and 60 is a switching contact that switches the induction motor 50 to the first
This inverter 40 or the second inverter 140 is provided to switch the connection. Also, 100 is the first
A synchronization detection circuit for synchronizing the second oscillators 20 and 120, which includes output B of the first ring counter 30, output C of the second oscillator 120, and output A of the second ring counter 130. When the frequencies of the first oscillator 20 and the second oscillator 120 become approximately equal, a shift pulse signal fα based on a synchronization command D given from a detection circuit (not shown) is used as a condition. It is configured to give a switching command E to the switching contact 60 based on the generated output. The general configuration of the present application is as described above, and next, an example of a specific circuit configuration of the synchronization detection circuit will be explained with reference to FIG. 2.

In Fig. 2, the input terminal 1, I is connected to the synchronization command D described above.
However, the input terminals 11 and 11 similarly receive the output A of the second ring counter 130, the input terminal 111 receives the output B of the first ring counter 30, and the input terminal 1 receives the output A of the second ring counter 130. Second oscillator 12
The output C of 0 is input to the input terminals V, V, and the switching completion command F of the switching contact 60 is input to the input terminals V, V, respectively.

Also, R1 to R23 are resistors, C1 to C5, Cll, Cl2
are capacitors, D1 to Dll, D2l, and D22 are diodes, Trl to Tr4 are transistors, ICl to IC
19 is a NAND gate I gate, +V is a power supply potential, and COm is a common ground line. Also NAND gate ICl, IC3, I
C7, IC9, ICll, ICl2, ICl6, ICl
The aforementioned diode or capacitor is inserted into the enable terminal 8, and its inhibited state is released by applying a predetermined potential. A differential circuit is configured by a resistor R3 and a capacitor C1 after the input terminal 1, I (7), and a memory circuit R. S. FFL is configured. Also, input terminals 11, 11
For isolation of the input signal A, there is a photo coupler P. made up of a diode, a diode D2l, a D22 transistor Tr3. C. is inserted, and the resistor Rl5 and capacitor C3 at the stage subsequent to the NAND gate C7 constitute a differentiating circuit. Further, the NAND gates ICl2 and ICl3 connected to the rear stage of the input terminal 111 constitute a differentiating circuit, and the differential circuit is constituted by the resistor Rl9 and the capacitor C5 at the output terminal side of the NAND gate ICl7 after the input terminals V and V. has been done. Also, the input of the NAND gate IC9 constituting the logic control section is the output B of the first ring counter 30.
and the inverted signal C'' of the output C of the second oscillator 120, and the input to the enable terminal of the NAND gate IC is a preset input signal D'' obtained by differentiating the synchronization command D mentioned above. .S.FFl output D'''' (corresponding to shift pulse signal fα) and second ring counter 1
This is a signal A'' which is obtained by differentiating the output A of the memory circuit R.30.
S. FF2 is preset by the output H of this NAND gate IC, and is configured to drive the subsequent transistor Tr2, excite the relay RY, close the normally open contact 60 of the switching contact 60, and switch the induction motor 50. There is. Also R. S. A transistor Trl is connected to the rear stage of the other output terminal of FF4, and this transistor Trl
The configuration is such that the voltage set by the variable resistor VR is applied to the second oscillator 120 such as a V/f converter at the time of 0FF. One embodiment of the present invention is configured as described above, and its operation will be explained next.

For example, considering the control of a thread winding machine, the first inverter 40 is normally used to accelerate the induction motor 50, and when the induction motor 50 reaches a predetermined speed, it is then switched to the second inverter 140 for steady operation. Driving.

Assume that the switching contact 60 is now connected to the A side and the induction motor 50 is being driven by the first inverter 40. Third
Referring to the time chart in the figure, the output B of the first ring counter 30 input to the input terminal 111 is at time t-t.
1 and goes from L to H at time t=T4, the output of ICl3 becomes a rising differential output, and therefore the output B inverted by ICl4 becomes as shown in FIG. 3C.

Furthermore, the output C of the second oscillator 120 as shown in FIG. The passed output C'' becomes as shown in Figure 3f.The above outputs B'' and C'' become input to IC9 and are subjected to logical operations, but the inhibition of the enable terminal of IC is not released. and the above logical operation is not executed.If we refer to the input to the enable terminal of IC9, for example, if the synchronization command D is given to the input terminals 1 and I at time t=T3, as shown in FIG. Then, the rising edge is differentiated by the differentiating circuit formed by R3 and C1, as shown in FIG. S. As a result, a shift pulse signal fα having a predetermined pulse width is obtained as the output D″″, and this fα is input to one enable terminal of IC9.

At this time, as shown in FIG. 3d, the output A of the second ring counter 130 is connected to the photo coupler P of the input terminal 11,I.
．． C. When input to
A pulse as shown in FIG. 3e is generated at time t=T5, and this pulse is input to the other enable terminal of IC9. In the NAND gate IC9, the inhibited state is released only when the input to the enable terminal is H.

Therefore, time T in the time chart of FIG. ,t,
', the inhibited state is released at time T6, but the inhibited gate IC. The output becomes H due to the input signals B' and C' at time t=T. and at that time R. S. A preset input is given to FF2 and R. S. The output of FF2 becomes H and the transistor Tr,
is conductive, relay RY is excited, its contact 60a is closed, and switching contact 60 is switched from the A side to the B side. That is, in a state where the first and second oscillators are completely synchronized, the induction motor 50 changes from the accelerated operation by the first inverter 40 to the second oscillator.
The operation shifts to steady operation using the inverter 140. Further, when a switching completion command F is given to the input terminals V, V after a predetermined period of time after the switching contact 60 is turned on, for example at t=T, the resistors R, .
, capacitor C.

The signal differentiated by the differentiating circuit formed by R. S. A reset command is given to FF2 to invert the state again and change the output from H to L, so time t=T. In relay R
Y is demagnetized and the switching is completed, and it is in a standby state for the next switching. Note that in the above embodiment, the second oscillator 1
The pulse width of 20 corresponds to the commutation period width of the inverter,
That is, since the pulse rise time is made to coincide with the commutation start time, load switching can be performed during a period in which there is no load fluctuation.

Although the circuit configuration in Figure 2 is shown as an example of a synchronization detection circuit, it is possible to make various changes, and the load can be driven not only by induction motors but also by sequentially driving multiple inverters. applicable. As described above, the load switching circuit for multiple inverters according to the present invention drives a load by switching the outputs of the first and second inverters having separate first and second oscillators. Within the shift pulse signal given when the frequencies of the first and second oscillators become approximately equal, a synchronization detection circuit performs a logical operation on the signals based on the outputs of the first and second oscillators. Since the load is switched based on the logic operation output generated at the time of synchronization detection, the load can be switched synchronously with an inexpensive circuit configuration, and good load driving by the inverter can be realized. Even if the power-on detection circuit fails, the inverter will not be unable to operate.

The industrial value of this device is high because it is used in a device that sequentially drives a large number of inverters and frequently switches loads.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a load switching circuit for multiple inverters according to the present invention, FIG. 2 is a specific circuit example of the synchronization detection circuit in FIGS. 1 and 3, and FIG. 3 is a time chart of the circuit example shown in the figure. 20, 120...first and second oscillators, 30, 1, respectively
30...first and second ring counters, 40, 1, respectively
40...First and second inverters, respectively, 50...Load, 60...Switching contact, 100...Synchronization start detection circuit.

Claims (1)

[Claims] 1. In a device that drives a load by switching the outputs of a first and second inverter having separate first and second oscillators, a first ring provided between the first oscillator and the first inverter. a counter, a second ring counter provided between the second oscillator and the second inverter, outputs of the first and second ring counters, an output of the second oscillator, and a predetermined synchronization input; and a synchronization detection circuit that generates a command to switch the inverter output at the time of synchronization of the first and second oscillators based on the command, and the synchronization detection circuit has a differential signal of the synchronization startup command as a preset input. An inhibit state occurs when a first memory circuit that outputs a shift pulse signal and a pulse signal obtained by differentiating the shift pulse signal from the first memory circuit and the output signal of the second ring counter are input. is released, and a logic operation unit that takes an AND condition between the differential output signal of the first ring counter and a signal obtained by inverting the output of the second oscillator whose pulse corresponds to the commutation period of the inverter; A plurality of inverters comprising: a second memory circuit which uses the output of the second memory circuit as a preset input and is set by a switching completion command; and means for driving an inverter output switching contact by the output of the second memory circuit. load switching circuit.