JPS5951786B2 - timing signal detection circuit - Google Patents
timing signal detection circuitInfo
- Publication number
- JPS5951786B2 JPS5951786B2 JP51041492A JP4149276A JPS5951786B2 JP S5951786 B2 JPS5951786 B2 JP S5951786B2 JP 51041492 A JP51041492 A JP 51041492A JP 4149276 A JP4149276 A JP 4149276A JP S5951786 B2 JPS5951786 B2 JP S5951786B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- frequency
- controlled oscillator
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 title claims description 12
- 235000013162 Cocos nucifera Nutrition 0.000 claims 1
- 244000060011 Cocos nucifera Species 0.000 claims 1
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000010363 phase shift Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 241001062872 Cleyera japonica Species 0.000 description 1
- 241000269821 Scombridae Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 235000020640 mackerel Nutrition 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】
この発明はパルス通信方式においそ用いられるタイミン
グ信号検出回路に関し、特にパルス振幅変調信号から倖
相同期回路を用いてタイミング信号を検出する回路に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing signal detection circuit used in a pulse communication system, and more particularly to a circuit for detecting a timing signal from a pulse amplitude modulated signal using a phase synchronization circuit.
パルス振幅通イ鯖こおいては情報は一定gmMで生起す
るパルスの振幅あ、るいは極性の形で伝送される。Pulse Amplitude In mackerel, information is transmitted in the form of the amplitude or polarity of pulses occurring at a constant gmM.
この信号から受信側で正しく元の・1*報を識別するた
めには、伝送パルスのパルス繰返し周波数に関する情報
、つまりタイミング信号が必要となる。In order to correctly identify the original 1* signal from this signal on the receiving side, information regarding the pulse repetition frequency of the transmitted pulse, that is, a timing signal is required.
一般にはこのタイミング信号を受信信号の中から検出す
る方法が取られている。Generally, a method is used to detect this timing signal from the received signal.
この検出方法の一つとして従来から広く用いられている
方法は受信信号を微分し、その結果を両波整流した後狭
帯域フィルタで、タイミング信号成分を取り出すと共に
雑音を除去し、さらに1脣ツタで振幅を一定としてタイ
ミング信号を得る方法である。One of the conventionally widely used detection methods is to differentiate the received signal, double-wave rectify the result, then use a narrow band filter to extract the timing signal component and remove noise. This is a method to obtain a timing signal by keeping the amplitude constant.
また最近新たに提案された方法として上記の方法におい
て微分の代りにパルス繰返し周波数の2分の1の周波数
を中心周波数とする帯域通過フィルタを用いる方法もあ
る。Another recently proposed method is to use a band-pass filter whose center frequency is one half of the pulse repetition frequency instead of the differentiation in the above method.
後者の方法は前者に比べて検出されたタイミング信号の
位相ジッタが少なくな、るとされている。The latter method is said to reduce the phase jitter of the detected timing signal compared to the former method.
ところがこれら画方法共両波整流回路を不可欠な要素と
している。However, both of these imaging methods require a double-wave rectifier circuit as an essential element.
一般に両波整流回路はダイオードを用いて実現されるが
、回路実現上素子および回路に寄生リアクタンスが伴な
うのが不可避であるため、入力信号のレベルに依存した
出力の位相ずれが生じる。Generally, double-wave rectifier circuits are realized using diodes, but since parasitic reactance is unavoidable in the elements and circuits when realizing the circuit, a phase shift in the output occurs depending on the level of the input signal.
、この位相ずれは検出されたタイミング信号のジッタと
なり好まし、くない。, this phase shift causes jitter in the detected timing signal, which is preferable and not necessary.
特に受信信号が多値パルス振幅変調信号の場合には両波
整流回路への入力信号のレベルの変動範囲も広く問題も
大きい。Particularly when the received signal is a multilevel pulse amplitude modulation signal, the range of variation in the level of the input signal to the double wave rectifier circuit is wide and the problem is serious.
車な前記2つの従来技術において、雑音除去と振幅一定
化の働きをする狭帯域フィルタとリミッタに代えて位相
同期回路を用いる従来技術もある。In the above-mentioned two prior art technologies, there is also a prior art technology that uses a phase synchronized circuit instead of the narrow band filter and limiter that function to remove noise and stabilize the amplitude.
÷の方法は帯域を狭くすることが技術的に容易なことと
、振幅一定化の効果が理想的べあるとビ1う点で狭帯域
フィルタとリミッタを用いる方法十り優れているが反面
回路が複雑になるという欠点が西や。The ÷ method is superior to the method using a narrow band filter and limiter in that it is technically easy to narrow the band and the effect of constant amplitude is ideal, but on the other hand, the circuit The disadvantage is that it becomes complicated.
この発明の目的はこれらの問題を解決したタイミング信
号検出回路を提供することにある。An object of the present invention is to provide a timing signal detection circuit that solves these problems.
、この発明のタイミング信号休出回路はパルス繰返し周
波数fOのパルス振中声弯調信号舎対象とし、中心周波
数fO/2の帯域通過フイノし夕と、3次の非直線性を
有する非直線素子を含みこの素子に結合された第1およ
び第2の高周波信号端子と低周波信号端子とを備えた非
線形回路と、周波数foを中心とする周波数領域で動作
する電圧制御発振器とを含み、前記パルス振幅変調信号
を前記帯域通過フィルタを介して前記非線形回路の第1
の高周波信号端子に接続し、前記電圧制御発振器の出力
を同じく第2の高周波信号端子に接続し、前記非線形回
路の低周波信号端子から得られる信号を電圧制御発振器
にその周波数を制御すべく接続し、電圧制御発振器の出
力をタイミング信号として取り出すことを特徴とする。, the timing signal output circuit of the present invention is intended for a pulse oscillation tone signal structure with a pulse repetition frequency fO, and includes a bandpass filter with a center frequency fO/2 and a nonlinear element having third-order nonlinearity. a nonlinear circuit having first and second high frequency signal terminals and a low frequency signal terminal coupled to the element, and a voltage controlled oscillator operating in a frequency domain centered on a frequency fo, The amplitude modulated signal is passed through the bandpass filter to the first one of the nonlinear circuit.
the output of the voltage controlled oscillator is also connected to a second high frequency signal terminal, and the signal obtained from the low frequency signal terminal of the nonlinear circuit is connected to the voltage controlled oscillator to control its frequency. It is characterized in that the output of the voltage controlled oscillator is extracted as a timing signal.
この発明を用いれば、受信信号のレベル変化による位相
変化が少なく、かつ位相ジッタの少ないタイミング信号
検出回路が得られる。By using the present invention, it is possible to obtain a timing signal detection circuit that has little phase change due to level changes in a received signal and has little phase jitter.
また両波整流回路と位相比較器の働きが一体化された非
線形回路を有し構成が簡単な位相同期回路形のタイミン
グ信号検出回路が得られる。Furthermore, a phase-locked circuit type timing signal detection circuit having a simple structure and having a nonlinear circuit in which the functions of a double-wave rectifier circuit and a phase comparator are integrated can be obtained.
次に図面を参照してこの発明の詳細な説明する。Next, the present invention will be described in detail with reference to the drawings.
第1図は従来のタイミング信号検出回路を示すブロック
図である。FIG. 1 is a block diagram showing a conventional timing signal detection circuit.
入力端子1から加わったパルス繰返し周波数foのパル
ス振幅変調信号は中心周波数がfo/2の帯域通過フィ
ルタ2を通り、両波整流回路3で正負が折り返されるこ
とによって周波数fOの成分が発生する。A pulse amplitude modulated signal with a pulse repetition frequency fo applied from an input terminal 1 passes through a bandpass filter 2 with a center frequency of fo/2, and the positive and negative signals are folded back by a double-wave rectifier circuit 3, thereby generating a component with a frequency fO.
このfoの成分は乗積形位相検波器4へ加えられ、ここ
で周波数foを中心周波数とする電圧制御発振器5の出
力との間の位相差が検出される。This component of fo is applied to the product type phase detector 4, where the phase difference between it and the output of the voltage controlled oscillator 5 having the center frequency fo is detected.
この検出された位相誤差信号は低域通過フィルタ6で雑
音が除求され、電圧制御発振器の周□波数を位相誤差が
減少する方向に制御すべく帰還される。This detected phase error signal is subjected to noise removal by a low-pass filter 6, and is fed back to control the frequency of the voltage controlled oscillator in a direction that reduces the phase error.
電圧制御発振器の出力がタイミング信号として出力端子
7から得られる。The output of the voltage controlled oscillator is obtained from the output terminal 7 as a timing signal.
この従来例においては両波整流回路の入力レベルに依存
する移相特性が出力多イミングジツタに悪影響を及は゛
シンまた回路がエヒ較的複雑な点が欠点であることは先
述の通りである。As mentioned above, in this conventional example, the phase shift characteristic depending on the input level of the double-wave rectifier circuit adversely affects the output multi-timing jitter, and the disadvantage is that the circuit is relatively complicated.
□第2図はこの発明の一実施例を示すブロック図である
。□FIG. 2 is a block diagram showing an embodiment of the present invention.
構成要素1. 2. 5. 6.および7は第1図の従
来fiI:と同じものである。Component 1. 2. 5. 6. and 7 are the same as the conventional fiI: in FIG.
1参照数字800は3次の非直線性を有す非直線−子を
含む非線形回路であり、:承1および第2の高周波信号
端子801および802と低周波信号i子808および
非直線素子であるダイオード804,805を備えてい
る。1 Reference numeral 800 is a nonlinear circuit including a nonlinear element having third-order nonlinearity: first and second high-frequency signal terminals 801 and 802, a low-frequency signal I-terminal 808, and a nonlinear element. It includes certain diodes 804 and 805.
ダイオード804.および805の並列回路は第3図に
横軸に電圧を縦軸に電流を取ってその電圧−電流特性を
曲線9で示すごとく3次の非直線性を示す。Diode 804. The parallel circuits 805 and 805 exhibit third-order nonlinearity as shown by the voltage-current characteristic curve 9 in FIG. 3, where the horizontal axis represents the voltage and the vertical axis represents the current.
参照数字803は端子801における周波数fo/2近
傍の信号と端子802における周波数foの信号とをダ
イオード804,805へ結合させる働きをする分波器
である。Reference numeral 803 is a duplexer that serves to couple a signal at a frequency near fo/2 at terminal 801 and a signal at frequency fo at terminal 802 to diodes 804 and 805.
また抵抗806.コンデンサ807はダイオード804
.805両端に発生する低周波信号を周波数f。Also resistor 806. Capacitor 807 is diode 804
.. The low frequency signal generated at both ends of 805 has a frequency f.
およびfO/2近傍の高周波信号と分離して低周波信号
端子808から取り出すための低域通過フィルタである
。and a low-pass filter for separating the high-frequency signal near fO/2 and extracting it from the low-frequency signal terminal 808.
この発明のタイミング信号検出回路の動作は次のように
説明できる。The operation of the timing signal detection circuit of this invention can be explained as follows.
今端子801における信号をυ1とし端子802におけ
る信号をυ2とすると3次非直線性を示す素子にはυ1
十9□なる電圧が加わる。Now, if the signal at terminal 801 is υ1 and the signal at terminal 802 is υ2, the element exhibiting third-order nonlinearity has υ1.
A voltage of 19□ is applied.
この時非直線素子に流れる電流は(υ1 +υ2)3=
υY +3υ〒υ2+3υ1υイ+υ芽なる成分を含む
。At this time, the current flowing through the nonlinear element is (υ1 +υ2)3=
υY +3υ〒υ2+3υ1υi+υContains the bud component.
すなわちυ1はfo/2成分を含み、υ2は電圧制御発
振器5の出力であるのでfO酸成分含んでいる。That is, υ1 contains the fo/2 component, and υ2 is the output of the voltage controlled oscillator 5, so it contains the fO acid component.
すると (υ1十υ2)3を展開した後の各項において
は、第1項のυtは(3fo/ 2 )成分を含み、第
2項の3υむυ2は(fo±fo)成分□を含み、第3
項の3υ、・υくは(fo/2±2fo)成分を含み、
第4項のυ艮は3fo成分を含む。Then, in each term after expanding (υ10υ2)3, the first term υt contains the (3fo/2) component, the second term 3υ υ2 contains the (fo±fo) component □, Third
The term 3υ, ・υ contains the (fo/2±2fo) component,
The fourth term, υ, includes a 3fo component.
したがって、この電流の内で低周波成分を含む項は第2
項、すなわちυで・υbの項のみであることは容易に分
る。Therefore, the term that includes low frequency components in this current is the second term.
It is easy to see that there are only terms υ and υb.
この電流に比例する低周波電圧が端子808から得られ
る。A low frequency voltage proportional to this current is obtained from terminal 808.
このυ〒・υ2の項は明らかに帯域通過フィルタ2の出
力υ1を2乗(別の表現をすれば両波整流)した□もの
と電圧制御発振器出力υ2を掛けたものに等しいので非
線形回路800は第1図の榊来例にお□ける両波整流回
路3と乗積形位相検波回路4とを合わせた作用をするこ
とが分る。This term υ〒・υ2 is obviously equal to the product of the square of the output υ1 of the bandpass filter 2 (in other words, double-wave rectification) and the voltage-controlled oscillator output υ2, so the nonlinear circuit 800 It can be seen that the circuit functions as a combination of the double-wave rectifier circuit 3 and the multiplication phase detection circuit 4 in the Sakaki example of FIG. 1.
すなわち端子808からは端子801の信号を2乗した
信号と端子802の信萼との位相誤差を示す信号が得ら
れ、第1図の従来例と同様位相同期回路が構成される。That is, from the terminal 808, a signal indicating the phase error between the signal obtained by squaring the signal at the terminal 801 and the signal at the terminal 802 is obtained, and a phase synchronization circuit is constructed as in the conventional example shown in FIG.
このようにこの発明では両波整流と乗積形位相検波が一
つの構成要素で行なわれるため回路構成が簡単になる。As described above, in the present invention, double-wave rectification and multiplicative phase detection are performed by one component, so the circuit configuration is simplified.
また端子802に加わる電圧制御発振器出力を端子80
1に加わる信号に比べて充分に大きくしておけばダイオ
ード804.805に寄生するりアクタンスの効果は充
容に平均化されて、入力レベルに依存する位相変化を充
分に小さく抑えることができる。In addition, the voltage controlled oscillator output applied to the terminal 802 is connected to the terminal 80.
1, the effect of parasitic actance on the diodes 804 and 805 is averaged out, and the phase change depending on the input level can be suppressed to a sufficiently small value.
第4図は非線形回路の他の実施例を示す回路図である。FIG. 4 is a circuit diagram showing another embodiment of the nonlinear circuit.
構成要素801,802,804,805.806,8
07,808は第2図のそれらと同じものである。Components 801, 802, 804, 805, 806, 8
07,808 are the same as those in FIG.
本実施例においては高周波信号の結合手段として第2図
の実施例の分波器803に代えて抵抗809,810,
811および増幅器812からなる回路を用いている。In this embodiment, resistors 809, 810 are used instead of the duplexer 803 in the embodiment of FIG.
A circuit consisting of an amplifier 811 and an amplifier 812 is used.
この回路はよく知られた合成回路であり、端子801お
よび802に加えられた信号の和がダイオード804.
805に加わる点では前記実施例と全く同じであり、こ
のような結合手段を用いてもこの発明を構成できること
は明らかである。This circuit is a well-known synthesis circuit in which the sum of signals applied to terminals 801 and 802 is connected to diode 804 .
The points added to 805 are completely the same as those in the previous embodiment, and it is clear that the present invention can be constructed using such a coupling means.
以上説明したようにこの発明を用いれば構成が簡単でし
かもジッタの少ないタイミング信号検出回路を得ること
ができる。As explained above, by using the present invention, it is possible to obtain a timing signal detection circuit with a simple configuration and less jitter.
第1図は従来技術を示す回路図、第2図はこの発明の一
実施例を示すブロック図、第3図は第2図の実施例にお
ける非直線素子の電圧−電流特性図、第4図は非線形回
路の他の一実施例を示す回路図で゛ある。
第2図において、1は入力端子、2は周波数fo/2を
中心周波数とする帯域通過フィルタ、800は非線形回
路、5は電圧制御発振器、6は低域通過フィルタ、7は
出力端子である。FIG. 1 is a circuit diagram showing the prior art, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a voltage-current characteristic diagram of the nonlinear element in the embodiment of FIG. 2, and FIG. is a circuit diagram showing another embodiment of the nonlinear circuit. In FIG. 2, 1 is an input terminal, 2 is a band pass filter having a center frequency of fo/2, 800 is a nonlinear circuit, 5 is a voltage controlled oscillator, 6 is a low pass filter, and 7 is an output terminal.
Claims (1)
象とし、中心周波数fo/2の帯域通過フィルタと、3
次の非直線性を有する非直線素子を含みこの素子に結合
された第1および第2の杏周波信号端子と低周波信号端
子とを備えた非椰形回路と、周波数fOを中心とする周
波数印域で動作する電圧制御発振器ヤを含み、前記パル
ス振幅変調信号を前記帯域通過フィルタを介して前記非
響形回路の第1の高周波信号端子に接続し、前記電圧制
御発振器の出力を同じく:第2の高周波信号端子に接続
し、前記非線形回路の低周波信号端子がら得られる信号
を電圧制御発振器にそあ周波数音制御すべく接続し、電
圧制御発振器の中力をアイミング信号として、取り出す
ようにしだらとを特懲とするタイミング信号検出回路。1 A bandpass filter with a center frequency fo/2, which targets a pulse amplitude modulation signal with a pulse repetition frequency fo, and 3
a non-coconut circuit comprising a non-linear element having the following non-linearity and coupled to the element, first and second almond-frequency signal terminals and a low-frequency signal terminal; a voltage controlled oscillator operating in the frequency band, the pulse amplitude modulated signal being connected to a first high frequency signal terminal of the aphonic circuit through the bandpass filter, and the output of the voltage controlled oscillator also: A signal obtained from the low frequency signal terminal of the nonlinear circuit is connected to a second high frequency signal terminal, and a signal obtained from the low frequency signal terminal of the nonlinear circuit is connected to a voltage controlled oscillator for frequency control, and the middle power of the voltage controlled oscillator is extracted as an timing signal. Timing signal detection circuit with special punishment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51041492A JPS5951786B2 (en) | 1976-04-13 | 1976-04-13 | timing signal detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51041492A JPS5951786B2 (en) | 1976-04-13 | 1976-04-13 | timing signal detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52124849A JPS52124849A (en) | 1977-10-20 |
| JPS5951786B2 true JPS5951786B2 (en) | 1984-12-15 |
Family
ID=12609838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51041492A Expired JPS5951786B2 (en) | 1976-04-13 | 1976-04-13 | timing signal detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5951786B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2523383B1 (en) * | 1982-03-15 | 1985-11-22 | Thomson Csf | CLOCK FREQUENCY RECOVERY DEVICE IN DIGITAL TRANSMISSION |
| JPS59501090A (en) * | 1982-06-14 | 1984-06-21 | ウエスタ−ン エレクトリツク カムパニ−,インコ−ポレ−テツド | timing recovery circuit |
-
1976
- 1976-04-13 JP JP51041492A patent/JPS5951786B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52124849A (en) | 1977-10-20 |
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