JPS5952390B2 - Ultrasonic beamformer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in ultrasonic beam formers used in ultrasonic diagnostic equipment and the like.

゛Ultrasonic diagnostic equipment shines a pulsed ultrasound beam with a limited generation time into the body and detects the echoes.
This is displayed on the plan pipe, etc.

Therefore, in order to increase the resolution of the displayed image, it is necessary to focus the ultrasonic beam as narrowly as possible.

However, since the directivity of commonly used ultrasonic transducers (hereinafter abbreviated as transducers) is weak,
It was impossible to obtain the extremely narrow ultrasonic beam as described above using a single transducer.

Therefore, a beamformer has been proposed that utilizes the interference effect of each ultrasonic signal by arranging a large number of transducers in a straight line and transmitting the same ultrasonic signal from each transducer.

That is, by adjusting the phase of the ultrasonic signals sent out from each vibrator and matching the phases of the ultrasonic signals at a desired point, an extremely sharp ultrasonic beam is obtained.

(Phased Array Method) An example of such a beamformer that has been conventionally used is shown in FIG.

In the figure, DV is a drive device that generates a drive signal, and D
Ll, DL2. ....

DLn is a variable delay element that provides a delay of 2 to the above-mentioned drive signal, which is determined each time.

[Force, Trl, Tr2. ...Tr is a vibrator that converts an electric signal into an ultrasonic signal, and SG1. SG2.・・・
-SGo is a transmission signal generator that transmits a transmission signal to each of the vibrators Tr- in response to the delayed drive signal.

Here, the vibrator Tr1. Tr2. . . . Trn are arranged in a straight line, and each of them is continuously connected to a corresponding transmission signal generator SG and furthermore a delay element DL.

In this way, each channel has one resonator Tr-1.
Equipped with a transmission signal generator 5G-1 delay element DL-,
The n channels are driven by the same driver DV.

The amount of delay in each delay element DL- is determined as follows.

For example, when focusing an ultrasound beam on point P1, first, from point P1 to transducer Tr4. Tr2. ..., draw an arc R1 with a radius equal to the distance to the foot of the perpendicular line drawn toward the straight line on which Tro is arranged, and calculate the distance from each vibrator Tr- to this arc R1.

Due to this distance, it takes time t1 for the ultrasonic signal sent out from each transducer Tr- to reach the position of the circular arc R1.
t2...tn are calculated, and the maximum value tn is selected from among them.

This maximum value t in the delay element DL- of each channel.

Set the value obtained by subtracting - from the transmission time of the own channel as the delay time.

Therefore, delay element DL1 has (t, -tl), DL2
(t n tz), DL3 (tn ta)
)..., DL, is tn (in this case, t1 is the oscillator T
t because r is in contact with the arc R□.

−〇=1n), ..., DL has (tn-tn=o
) are set respectively.

Therefore, when a drive signal is sent from the drive device DV, the delay amount in the delay element DL is "0" in the n-th channel, so a transmission signal is immediately generated from the transmission signal generator SGo. As a result, an ultrasonic signal is transmitted from the transducer Trn.

Similarly, ultrasonic signals are transmitted from the channel with the shortest delay time each time the delay time elapses. An ultrasonic signal is sent out from the channel, and finally, after tnn, an ultrasonic signal is sent out from the first channel.

Therefore, the leading portion of each ultrasonic signal at this point will be in contact with this arc R1, and all the ultrasonic signals will arrive at the same phase at the 21 points that have propagated the same distance from here. .

That is, this P. Since all the ultrasonic signals are added at this point, the ultrasonic signals at this part become extremely strong and equivalently become a sharp ultrasonic beam.

Next, when focusing the ultrasound beam on another point P2,
Arrival time T1 to arc R2 drawn in the same manner as in the above case. T2. , Tn is calculated, and the difference between each of them and its maximum value (T1 in this case) is calculated, and this is applied to each delay element DL1 . DL2. ...Set DLn as a delay time.

After that, when the driving signal calyx is sent out from the driving device DV, ultrasonic signals are oscillated from the transducers Tr- one after another based on the delay time, and the ultrasonic signals from all the transducers Tr- are emitted at 22 points. They are added in the same phase, resulting in an equivalently sharp ultrasonic beam.

In this way, in the ultrasonic beamformer that has been commonly used until now, it is necessary to be able to set the delay amount arbitrarily for the delay element provided for each channel, and the variable step width of this delay amount is fine. In such cases, a high-precision variable delay line is required, and it is expensive, so providing one for each channel is a major medical burden, and it is difficult to use a general variable delay element. In this case, a mechanism for setting and controlling the delay amount is essential, and as the number of selections increases, the mechanism becomes complicated and expensive.

The present invention solves the above-mentioned drawbacks when transmitting a phased array using the pulse method by simultaneously controlling the transmission delay time and transmission pulse width of each channel using a counter and a matching circuit prepared for each channel. It provides a removed ultrasound beamformer, and will be described in detail below.

FIG. 2 is a block diagram for explaining the present invention in detail. In the same figure, CNT is a down counter that can be preset with the sent preset information PSI, and CMP is a down counter that can be preset with the received preset information PSI. This is a coincidence circuit which receives CPI as input, and the output of the down counter CNT is given to the other input terminal B, and detects coincidence between the two.

Here, the preset information PSI is a value Mk+L corresponding to the sum of the transmission pulse wave number and the transmission delay number, and the comparison information CP
I is information indicating a value Mk corresponding to the transmission pulse wave number.

The transmission pulse wave number Mk and the transmission delay number are quantities defined as follows.

That is, the transmission pulse wave number is equal to the duration T of the transmission output signal divided by the cycle Δd of the tarlock CK of the down counter CNT, Mk=T/Δd, and is expressed as an integer.

In addition, the number of transmission delays is equal to the relative delay time between channels required for beamforming, that is, the delay time τ for the earliest channel to be transmitted, divided by the period Δd of the clock CK, L= τ/Δd.

In this way, both of them are obtained by normalizing the pulse width and delay time shown in the transmission output signal waveform of FIG. 2 by the period Δd of the clock pulse CK.

In the figure, after the evening counter finishes counting Mk+L, it generates a transmission stop signal rs.

Further, the coincidence circuit CMP compares Mk input as CPI with the output of the down counter CNT, and when the output matches Mk, that is, when the down counter has finished counting the number of transmission delays, the transmission start signal st occurs.

In addition, in the same figure, SSG is activated by the transmission start signal st of the minus number circuit CMP, and the down counter C
This is a transmission signal generator that is reset by the transmission stop signal rs of the NT.

These devices are prepared for each channel and connected to a vibrator (not shown).

At the same time as the transmission is activated, a tarlock pulse CK is supplied to the counter CNT, and the counter CNT starts counting.

The counter CNT sequentially updates the preset value as the count progresses and transfers its contents to the coincidence circuit CMP.

The coincidence circuit CMP detects a coincidence between the comparison information CPI and this information, and outputs a transmission start signal st at the same time as detecting the coincidence.

That is, the counter CNT counts the number of transmission delays M, and outputs the transmission start signal st at the same time as detecting a match.

That is, the counter CNT counts the number of transmission delays M, and when the preset number of transmission pulse waves and the number of transmission delays (Nk+M) has changed to the number of transmission pulse waves Nk, the coincidence circuit CMP is activated.
A transmission start signal st is sent out.

The transmission signal generator SSG is activated by the transmission start signal st and starts transmitting the transmission output signal.

The counter CNT continues to count the clock pulses CK, and after counting the number of transmission pulse waves Nk, sends out a transmission stop signal rs.

The transmission signal generator SSG stops its operation in response to the transmission stop signal rs, and ends the transmission of the transmission output signal.

As a result, from the output terminal of the transmission signal generator SSG, a transmission output signal having a desired number of pulse waves is sent out with a delay time corresponding to the number of transmission delays after the drive as shown is started.

Next, such a down counter CNT and matching circuit C
Consider the number of bits required for MP.

Let the maximum value of the integer M required here be X (≦2 ji, the maximum value of the number of transmission delays be Y (52 m1), and the decomposition step of the number of transmission delays is 1/(2 m2) steps.

As can be seen from the above explanation of the principle of the present invention, there are two types of control signals to be sent by the counter CNT and the coincidence circuit CMP.

i) Transmission end signal (for example, sent when the value of the down counter CNT becomes a) 11) Transmission start signal (for example, sent when the value of the down counter CNT becomes b) The number line of the down counter CNT at this time is It is shown in Figure 3.

In the same figure, the dynamic range of the down counter CNT is indicated by a bold line, and normally 21091→"111.
@HOT “→”1” is repeated.

Here, 60' at the leftmost end indicates that the down counter CNT becomes all "1's" and returns to zero at the next tarok, and is the same as 0 at the rightmost end.

Next, the aforementioned value a is assigned on this number line.

This value a can be assigned to any point, but considering the ease of issuing a transmission end signal, it is appropriate to assign it to the 0' point.

Then, the value will be assigned to the position obtained by subtracting the transmission pulse wave number from the point ``0'' to which the value a was assigned.

Further, the point at which the transmission drive starts is assigned to the point corresponding to the value C obtained by subtracting the number of transmission delays from this value, but this point must not exceed the 0'' point.

Therefore, the part for counting the integer part of the transmission pulse wave number and the transmission delay number in this down counter CNT is 10g2(X 10Y)510g2(2N+2m1)≦m
A capacity of aj(N, ml) −1−1 bits is required.

Here the symbol maj is maj (A, B) = (A
(When A>B)/B (When A<B).

Further, the part for counting the decimal part of the number of transmission delays in the down counter CNT requires a capacity of 10g2 (2m2)-m2 bits.

Therefore, the down counter CNT as a whole requires a counting capacity of (m2+maj (N, I□) + 1) bits.

Here, if the ease of issuing the transmission end signal is taken into account as described above, it is better to add one more bit to make it (m2+maj (N, ITh) +2) bit.

Furthermore, this added 1 bit can also be used as a transmission enable/disable (hereinafter abbreviated as e/d) signal.

On the other hand, the required number of bits for the matching circuit CMP is (maj (N, ml) +1) since it is enough to code one point on the number line in FIG.

By setting N'=maj (N, ml), we can summarize the above results and rewrite them as follows.

1) Required number of bits of down counter CNT (N'+m
2+2) bits"i) Required number of bits for matching circuit CMP (N'+1)
Hereinafter, the present invention will be described in detail based on the embodiment shown in FIG.

FIG. 4 is a block diagram showing one embodiment of the present invention, and FIG. 5 does not explain its operation.

This is a time chart.

In FIG. 4, CNT is a down counter, which is preset to a value corresponding to the sum of an integer M and the integer part of the number of transmission delays, and a (N'+2) bit integer part counter cnti and a decimal number of the number of transmission delays. The value corresponding to the part is preset.

It is constructed by cascading m2-bit decimal counters cntd.

This integer part counter cnti and decimal part counter cn
An up counter is used as td, and the most significant bit MSB of the integer part counter cnti is the transmission e/
d signal is preset.

In addition, CMP is a value (N'+1) corresponding to the number of transmission pulse waves manually inputted to one input terminal A as comparison information CPI.
bit and the integer counter cnt to the other input terminal B.
Excluding its most significant bit MSB sent from i<
(N'+1) bits of count information, and when a match is detected, outputs a set signal st. G2 generates a clock pulse C by the transmission end signal rs sent when the counter CMT returns to zero or by the start signal ST instructing the start of transmission drive.
Gating K and clock pulses C only for desired time intervals
This is a gate that supplies the signal K to the counter CNT.

Furthermore, SSG is a transmission signal generator, which is set by a D/A converter dac that converts a 2-bit digital input signal into an analog signal of a predetermined level, and a set signal st from a matching circuit CMP, and an integer part. counter cn
It is reset by the negation signal of the transmission end signal rs output from MSB (the most significant pin of ti), and the output signal from the output terminal Q on the positive side is outputted from the A/D converter adc.
The alternating signal f outputted from the decimal part counter cntd is gated by the flip-flop ff supplied to the lower input terminal of the input terminal FF, and the output signal from the output terminal Q, and the output signal a is sent to the upper half of the A/D converter dac. Input terminal U
This is a transmission signal generator constituted by a gate g that supplies signals to the transmitter.

Next, its operation will be explained with reference to FIG.

It is assumed that the contents of the down counter CNT are initially cleared.

If the generation timing of the transmission stop signal rs is set to the point in time when the count value of the down counter CNT returns to zero as described above, the generation timing of the transmission start signal, that is, the transmission start signal st, is determined when the count value of the integer part counter cnti corresponds to 2 of N. This is when the complement number (hereinafter referred to as TCCM) is used.

Therefore, comparison input information C to input terminal A of coincidence circuit CMP
As PI, it is necessary to input TC.

Moreover, this timing corresponds to the case where the number of transmission delays is "0", so this down counter CNT
The preset information PSI for the PSI is a "1" level transmission e/d signal indicating the enable state and TC(M) +TC(L) =TC(M+L).

This preset signal PSI has lower m2 bits and upper (N
'+2) bits, and the fractional part of TC(L) is m
TC (M x L) is input to the 2-bit decimal counter cntd.
The integer part of is the lower part of the integer part counter cnti (N'+1)
bit, the transmitted e/d signal is the integer part counter cnt
The most significant bit of i) MSH is preset by the load signal LD, respectively.

After presetting all channels, start signal ST
becomes 1' at the timing shown in FIG.
is opened and a clock pulse CK is supplied to gate G2.

As mentioned above, the most significant bit of the integer part counter cnti is
Since MSB is at “1” level, gate G2
Therefore, the clock pulse CK passing through the gate G1 is sent to the decimal counter cnt as the counting signal CK.
d.

Since the decimal part of the TC (transmission delay number) is preset in the decimal part counter cntd as described above, the decimal part counter cntd returns to zero once it counts the count signal CK corresponding to the decimal part of the transmission delay number. , and then outputs an alternating signal f by normal counting operation, and then outputs an alternating signal f to the integer part counter cn.
ti counts this alternating signal f.

The integer part counter cnti always sends its lower (N'+1) bits to the coincidence circuit CMP, and the coincidence circuit CMP checks whether this information arriving at the input terminal B matches the comparison information CPI given to the input terminal A. Detection is in progress.

As mentioned above, the lower part of the integer part counter cnti (N'+1
) bit is preset with the integer part of TC(M+L), so when the number of alternating signals f corresponding to the integer part of the transmission delay number is counted, the counted content becomes TC(M).

Here, since the comparison information CPI is <TC(M) as described above, the information on the surface input terminals A and B of the matching circuit CMP match, and therefore the transmission start signal st is sent from the output terminal.

In the transmission signal generation circuit SSG, the transmission start signal st sets the flip-flop ff, and since the output from its positive output terminal +Q becomes "1", the gate g is opened.

Therefore, the alternating signal f sent from the counter CNT is gated and output as an output signal a, which is supplied to the upper input terminal U of the A/D converter adc.

Further, the output signal from the positive output terminal Q of the flip-flop ff is supplied to the lower input terminal of the A/D converter adc.

This A/D converter adc is at a negative level when the input levels of input terminals U and L are 0゛@l 191;
．． In the case of H094, O level, "l 99.
In the case of tel I9, a positive level signal is output.

Therefore, when the flip-flop ff is set, the burst signal OU alternates between positive and negative in synchronization with the alternating signal f.
T is output.

The counter CNT continues its counting operation thereafter, and returns to zero after counting the number of alternating signals f corresponding to the number of transmission wave pulses.

Therefore, the transmission end signal rs outputted from the most significant bit MSB becomes 44011, and the gate G2 is closed to stop the block signal CK, and the flip-flop ff whose negative signal is supplied to the terminal CL is reset.

Therefore, the counter CNT stops counting, and the burst signal OUT also returns to 0 level.

After the transmission of all channels is completed in this way, the start signal ST falls to "0" and this state continues until the next preset information PSI is preset in the counter CNT and the start signal ST is generated.

As described in detail above, according to the ultrasonic beamformer according to the present invention, only a simple digital circuit such as a counter and a matching circuit is provided for each channel. Not only can it be realized at an extremely low cost compared to the conventional method, but also the delay time and pulse width can be arbitrarily set by simply setting a value corresponding to the number of transmission delays and the number of transmission pulses in a counter.

[Brief explanation of drawings]

Figure 1 is a diagram to explain the ultrasonic beamformer, Figure 2 is a diagram to illustrate the principle of the present invention, Figure 3 is a number line to explain the bit capacity of the counter, and Figure 4 is a diagram to explain the present invention. FIG. 5 is a block diagram showing one embodiment of the invention and a time chart explaining its operation. CNT...down counter, cnti...
...Integer part counter, cntd... Decimal part counter, MSB... Most significant bit, CMP...
... Matching circuit, SSG ... Transmission signal generator,
ff...Flip-flop, adc...
・D/A converter, g, G1. G2...Gate.

Claims (1)

[Claims] 1. Using a transducer array consisting of a plurality of ultrasonic transducers,
Drive each transducer in an ultrasound beamform that forms an ultrasound beam in a desired direction by controlling the relative transmission time (hereinafter referred to as "delay time") of the transmission pulse signal that drives each transducer. a down counter that counts the sum T+τ of the delay time τ and the transmission pulse signal time width T, and generates a transmission step signal when the counting of the time is finished; A matching circuit detects that the time τ has been counted and generates a transmission start signal, and the transmission is started by the transmission start signal generated by the minus number circuit, and the transmission is ended by the transmission stop signal generated by the down counter. If the clock period △d for driving the down counter is an integer fraction of the carrier wave period (reciprocal of the carrier frequency) △C of the transmission signal, △c=l(△d(k is an integer greater than or equal to 1), the delay time is selected as τ-L△d, the transmission pulse signal time width is selected as T=M・△C, and M is set in the down counter.
An ultrasonic beamformer characterized in that a transmission delay time τ and a transmission signal pulse time width T are digitally controlled for each drive circuit by setting k+L.