JPS5952840B2 - Speech synthesizer interpolation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speech parameter interpolation device used in a speech synthesizer based on a human speech production model.

The above-mentioned type of speech synthesizer is generally known as a terminal analog type or linear prediction (LPC) type synthesizer.

Parameters such as the formant frequency, the pitch period of the voiced sound source, and the amplitude are given to a synthesizer to produce a voice. Usually the above parameters are 20ms or 10m
It is treated as the same value for about s frames. However, this frame length is insufficient, and better sound quality can be obtained by setting parameters with an even shorter frame length, but this naturally results in an increase in the number of bits. For this reason, it is generally possible to obtain high-quality speech without increasing the number of bits by setting the frame length to a certain extent and performing interpolation in units of about 2.5 ms within the speech synthesizer. Are known. FIG. 1 is a block diagram of a commonly used interpolation circuit.

In the figure, data stored in a memory 1 is calculated by an interpolation calculation section 3 and stored in a memory 4. in this case,
Two sets of memories, memory 1 and memory 2, are required to store data serving as reference points for interpolation, and three sets of memories are required when including memory 3, which stores interpolation results.

Since the number of bits per frame used by the speech synthesizer is quite large, the memory capacity is large. The present invention solves such problems and furthermore makes it possible to easily vary the speech rate of the speech synthesizer by adding a modification to the interpolation circuit.

Hereinafter, the present invention will be explained based on illustrated embodiments. FIG. 2 is a block diagram for explaining the basics of the present invention. In the figure, 5 is the first register, 6 is the second register, and 7 is the first register.
is a subtracter, 8, 9, 10 are each 1/2, 1/4, 1/8
Divider 11 is an adder 0 Parameters used for speech synthesis are input to the first register 5 for each frame O At the end of the frame, the data in the first register 5 is directly input to the second register 6 sent to. Therefore, at the beginning of each frame, the second register 6 stores the data of the previous frame. At the interpolation point, the data in the first register 5 and the data in the second register 6 are subtracted by a subtracter 7, and then passed through one of the dividers 8, 9, and 10. Since the divider creates a change in the interpolated value, if the data in the second register 6 and the output of the divider are added together in the adder 11 and stored in the second register 6, the data in the second register 6 can obtain interpolated data one after another. FIG. 3 is a block diagram showing an embodiment of the present invention.

In the same figure, the first
The register 20 and the second register 21 are made up of shift registers and shift data to the least significant bit (L) according to the clock.
SB). 29 is an interpolation calculation unit, and the first
The data in the register 20 and the second register 21 are taken in, and the interpolation result is sent to the second register 21.

22 is a subtracter which operates the data from the first register 20 and second register 21 bit by bit in synchronization with the clock and inputs the result to the adder 25.

23 and 26 are delay circuits which operate in synchronization with a clock by connecting unit delay circuits in series.

24 and 27 are selectors that can output the output of each stage of the unit delay circuit in each of the delay circuits 23 and 26 as required.

The output of selector 24 is input to adder 25. The output of adder 25 is input to delay circuit 26. 28 is a selector which selects the output of the selector 27 and the output of the register 20 and sends it to the second register 21. The zero delay circuit 23 delays the output of the second register 21.

The delay time is adjusted by the selector 24. Subtractor 22
The difference between the delay time of the adder 25 and the delay time of the delay circuit 23
The timing of the data of the subtraction result by the subtracter 22 and the data from the first register 21 that reach . The selection of dividers 8.9 and 10 in FIG. 2 is made by adjusting the delay time. The delay circuit 26 and the selector 27 are provided to adjust the timing difference generated between the delay circuit 23 and the selector 24. The selector 28 is provided to create a path directly sent from the first register 20 to the second register 21 at the end of the frame. The following table shows the selection of the divider of FIG. In the case of a 20 ms frame and in the case of a 10 ms frame, interpolation is performed at intervals of 2 and 5 ms, respectively.

Therefore, interpolation is performed at 8 points for a 20 ms frame and at 4 points for a 10 ms frame. This is shown in the case of normal mode in the table above. In a 20ms frame, from the first interpolation point to the third interpolation point, a divider of 14 is used, from the fourth interpolation point to the sixth interpolation point, a divider of Z is used,
At the seventh interpolation point, a Z divider is used.

FIG. 4 is a graph showing interpolation results according to an embodiment of the present invention.

The horizontal axis is time, and the numbers shown are the intraframe numbers of interpolation points. The vertical axis is the interpolated value. Interpolation point O and interpolation point 8
The interpolated value is data sent to the first register from the outside. When performing interpolation with the above algorithm, point a
Interpolated values from to point i are sequentially obtained. In the case of a 10 ms frame, interpolated values from point 0 p to point t shown in FIG. 5 are obtained.

Although the interpolated values cannot be perfectly linear interpolated, parameter interpolation of the speech synthesizer is sufficient and does not affect the quality of the sound from the speech synthesizer. By adding a device to the control of the interpolation circuit as described above, the speech rate can be easily controlled.

This will be explained. When the speed of capturing parameters for speech synthesis changes, control of the speaking speed is realized. In a speech synthesizer based on a speech generation model, the sound source and vocal tract are separated, so the parameters of the vocal tract can be changed quickly or slowly without changing the pitch of the voiced sound source, so it is possible to change the parameters of the vocal tract quickly or slowly without degrading the sound quality. Mouth speech becomes possible. In the table above, in the case of fast speaking in a 20ms frame, the 6th
An example is shown in which the interpolation point is set as the final interpolation point, the contents of the first register are directly transferred to the second register, and the next frame is entered. The interpolated value is the value from point a to point J in FIG. The speaking speed increases by 2570 points. On the other hand, in the case of slow transfer, the direct transfer from the first register to the second register at the end of the frame is extended, and interpolation continues during that time. In the case of the 20 ms frame delay in the table above, the frame is extended by two interpolation times, and the interpolation through the 1/2 divider continues at the 8th and 9th interpolation points. As a result, the interpolated value takes a value ranging from point a to point m in FIG. The frame stretches 2570, so 2
5? Becomes a slow talker. The above table and FIG. 5 show the conditions and changes in interpolated values for achieving 25% of the same speed and slow speed using parameters set to a 10 ms frame. In general, it is a frame of Xms, and in normal mode there are N frames (however,
N is a positive integer) interpolation points are set, and interpolation is obtained for each ΣMs. In fast and slow speaking modes, N±M interpolation points (where M is a positive integer) are set and the same as above is performed. The utterance rate N can be easily adjusted by calculating interpolation for each time and changing the frame period every Mx(1±-)Ms.

In addition, the previous example showed an example of 20ms frame and 10ms frame, but if you use the interpolation circuit of 10ms frame using the parameters set for 20ms frame, you can get twice as fast speech, and vice versa. You get twice as slow.

As is clear from the above description, according to the present invention, three memories are not required as in the conventional example shown in FIG. 1, and two memories, for example, the first register and the second register, are sufficient. Therefore, it is advantageous for cost reduction, and it is also possible to easily change the speaking speed with a relatively simple configuration, which is a very excellent effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional example, Fig. 2 is a block diagram for explaining the basics of the present invention, Fig. 3 is a block diagram of an embodiment of the present invention, and Figs. 4 and 5 are block diagrams of the present invention. It is a graph showing the progress of interpolated values according to an example. 5, 20... 1st register, 6, 21...
...Second register, 7, 22...Subtractor, 8,
9, 10... Divider, 11, 25...
Adder, 23, 26...Delay circuit, 24, 27
, 28... Selector, 29... Interpolation calculation unit.

Claims (1)

[Claims] 1. By serially connecting a subtracter and an adder that perform operations bit by bit starting from the least significant bit of data in synchronization with a clock and sequentially output the operation results, and a unit delay circuit. It is equipped with a delay circuit that operates in synchronization with a clock, and a first register and a second register, and data is updated in the first register every frame period, and the data in the first register and the second register are the lowest. bits to the subtracter, and the output of the subtracter and the output of one of the first register and the second register are supplied to the adder through the delay circuit, thereby forming an interpolation calculation section. , by changing the delay time of the unit delay circuit in the delay circuit, a change in interpolation value is created, an interpolation value corresponding to the number of interpolations within a frame period is calculated in an interpolation calculation section, and the interpolation results are sequentially processed. An interpolation device for a speech synthesizer, characterized in that the interpolation device is configured to serially transfer data to the second register. 2. In the statement of claim 1, the voice parameters of the voice synthesizer are set every x milliseconds, and
In the second mode, the frame period x (ms) is read into the first register and N (N is a positive integer) interpolation points are obtained within one frame. In the second mode, the frame period x (1 ±M/N) milliseconds (where M is a positive integer), the data is input into the first register, and is operated to obtain (N±M) interpolation points within one frame. 1. An interpolation device for a speech synthesizer, characterized in that the rate of speech from the speech synthesizer can be adjusted in a first mode and a second mode.