JPS5953732B2 - Out-of-sync detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for detecting out-of-synchronization in a phase-locked circuit.

Phase-locked circuit (hereinafter abbreviated as P, L, L).

) Various types of circuits are known for detecting out-of-synchronization.

One of them is a voltage controlled oscillator (hereinafter abbreviated as V, C, O).

) is known.

An example is shown in FIG. In FIG. 1, 1 is a phase comparator, 2 is a low-frequency P-wave device that extracts the DC component, and 3 is V, C, O, and its output frequency f.

is controlled by the direct current output from the low-frequency P-wave device No. 2.

4 is an N frequency divider, and the output frequency f of V, C, and O.

is divided into 1/N, and its output is phase-compared with the reference frequency f ref by one out-of-phase comparator.

5 and 6 are voltage comparators, respectively, and 7 is an AND gate.

FIG. 2 shows the control voltage-oscillation frequency characteristics of v, C0O, and FIG. 3 shows the phase difference-voltage characteristics of a phase ratio softener of 1.

The voltage comparator 5 outputs a high voltage when the control voltages of V, C, and O are equal to or less than a predetermined voltage of ■2.
If it is 2 or more, the voltage becomes Low.

In addition, the voltage comparator 6 outputs a high voltage when the control voltage is higher than the predetermined V1.
In the following cases, the voltage becomes Low.

Now, the oscillation frequency f of V and C0O. is fl<f. <f2, the outputs of voltage comparators 5 and 6 are High.
h voltage, and the output of the AND gate 7 becomes a High voltage.

Also, fo is f2<f. < f max or f man
In the case of <fo≦f1, the output of one of the voltage comparators 5 and 6 becomes a low voltage, and the output of the AND gate 7 becomes a low voltage, and v and C0O are approaching the limit of the frequency control range, This is detected as an out-of-synchronization and a warning is displayed.

max By the way, assume that the reference frequency f ref is f ref N.

In this case, the oscillation frequency f of V and C0O. is f. 〉f m
ax, but f is outside the control range.

cannot be synchronized.

Therefore, f rer>N, and the output of the phase comparator 1 is f.

In the case of the characteristic shown in FIG. 3, the phase difference changes in the direction of increasing the phase difference.

However, even if the phase difference becomes π, f re, > fB a
Since it is x, the phase difference is further increased to N.

However, when the phase difference exceeds π, the output of phase comparator 1 changes from VC to OV, and the voltage again follows an upward curve.

This situation is shown in FIG. Here, the required phase difference is the integral of the transient frequency.

At first, the V, C, O control voltages rise, and at time T8, ■2
When it reaches , the output of voltage comparator 5 becomes Low voltage,
An out-of-synchronization alarm is issued from the AND gate 7.

Furthermore, the V, C, and O control voltages continue to rise until ■ at time Tb.

After reaching , it becomes 0■. Along with this, the output of voltage comparator 5 changes from Low to High voltage, and voltage comparator 6
The output from High becomes Low voltage, and the alarm from the AND gate of 7 is maintained.

V, C, O control voltage rises from OV, and at time Tc
1, the outputs of voltage comparators 5 and 6 go High.
If the alarm is canceled despite the out-of-synchronization state, the alarm will be intermittent.

Now f ref will be exactly the same.

As a method for dealing with this, conventionally, a time constant circuit is provided at the output of the voltage comparators 5 and 6 or the output of the AND gate 7, so that once the alarm is sent out, there is a time delay in canceling the alarm. is being used.

However, especially when the reference frequency is a little low, the period of intermittent alarm T.

was quite long, making it difficult to implement a time constant circuit.

Furthermore, since the C0O control voltage fluctuates in a sawtooth pattern as shown in FIG. 4, there is a problem in that the oscillation frequency of V, 0.0 also fluctuates in the same way.

Therefore, the present invention is intended to improve the above-mentioned drawbacks of the prior art.The purpose of the present invention is to continuously send an alarm during an out-of-synchronization period, and to maintain an oscillation frequency of v, 0.0 even during the alarm period. f.

The objective is to provide an out-of-synchronization detection circuit that fixes the control frequency range to the upper limit (when the reference frequency f ref is high) or the lower limit (when the reference frequency f ref is low) of the control frequency range. When the control voltage reaches the upper limit (or lower limit), the low-frequency P-wave device and Monitor the output of the filter, P, L
, L is in the synchronized state, the alarm is canceled and the connection between the low-frequency 2-channel transducer and V, C, and O is restored.

Examples will be described below with reference to the drawings.

FIG. 5 is a block diagram of an embodiment of the present invention.
Items with the same numbers as those in the block diagram of Fig. 1 indicate the same functions, 8 is a detector that obtains information from voltage comparators 5 and 6 and detects out of synchronization, and 9 and 10 are 8 respectively. According to the information from the detector, ■, is a switch that disconnects the 0.0 control voltage from the low-pass filter at 2, and 11 is a battery, whose voltage is ■, the upper limit of the 0.0 control voltage, ■.

is set to .

The operation of this circuit will be explained.

Ru.

At this time, the output waveform of the low-pass filter 2 becomes similar to that shown in FIG.

In other words, at time T8, the output of voltage comparator No. 5 changes from High to Low voltage, and further at time Tb, voltage comparator No. 5 changes from Low to High voltage, and voltage comparator No. 6 changes from High voltage.
The voltage changes from to Low voltage.

Detector 8 detects this change, switches 10 to disconnect V, C, and O from low-pass filter 2, and
Connect to the battery No. 1, fix the control voltage 0.0 to its upper limit, and send out an alarm from the AND gate No. 7.

At this time, even though the oscillation frequencies of V, C, and Q are in the f max state, the output of the low-pass filter 2 draws an upward curve as shown in Figure 4,
The alert will be maintained.

Next, the alarm canceling operation will be explained.

Since the alarm is released when P, L, and L return to the synchronized state, the reference frequency fref is always f■, and the oscillation frequency of C0O is fixed at fmax, so the low frequency filter is The output voltage of wave generator 2 draws a downward curve, and once it reaches 0■, it becomes VC, and then continues to draw a downward curve.

At this time, the output of the 6 voltage comparators goes from High to Low voltage when the output voltage of the low-pass P wave generator 2 crosses ■1, and the voltage changes from OV to ■.

When the voltage becomes low, the voltage changes from low to high.

Also, at this time, the output of voltage comparator 5 changes from High to Low.
voltage.

Detect this change with the detector 8, change the switch 10, connect V, C, O and the low-frequency offshore transducer 2, and connect the AND of 7.
Release the gate output alarm.

When the output voltage of wave generator 2 draws a downward curve and changes from 0 to VC, detector 8 is activated and switch 9 is switched to separate V, C, and O from low-pass filter 2, and V, C, O
The control voltage is fixed at Ov, the alarm is ANDed with 7,
At this time, the output voltage of low-frequency P wave generator 2 draws an increasing curve,
(2) When changing from o to 0 (2), this change causes a change in the voltage comparators 5 and 6, and the detector 8 detects this change and performs an alarm canceling operation.

FIG. 6 shows a specific circuit example of the detector No. 8.

In Fig. 6, IN 1 and IN2 are respectively 5th
Connected to voltage comparators 5 and 6 in the figure.

Further, 0UT1 and 0UT2 are connected to the control terminals of switches 10 and 9 in FIG. 5, respectively.

12 and 15 are diodes, 13 and 16 are resistors, 14
and 17 are capacitors, and these I% and 17 are respectively IN
The human power of I and IN2 constitutes an integration circuit that delays the change in voltage from Low to High.

18 and 19 are inverters, INI and I, respectively.
The input of N2 is inverted.

20 and 21 are JK flip-flops (hereinafter referred to as JK-
It is abbreviated as FF.

) and the clock is a positive edge.

22 is an AND gate, 23 to 25 are resistors, and 26 to 28 are capacitors, and these resistors and capacitors respectively provide the output of 22 AND gates, 20 JK, -F-
It constitutes an integrating circuit for the inverted output of F (times) and the inverted output of 21 JK-F-F.

FIG. 7 shows waveforms for explaining the operation of the detection circuit of FIG. 6. B-Hl and IN1 of FIG. IN
2.0UT1.0UT2 represents the waveform of the same character portion in FIG. 6, and A is the output waveform of the low-frequency P wave generator 2 in FIG.

The operation of the circuit shown in FIG. 6 will be explained.

Let's say it's Tsuta.

At this time, the output of the low-frequency P wave device draws an upward curve as shown in A in Fig. 7, and the output of the voltage comparator 5 becomes High-+Low-.
(see FIG. 7, INI)), and then the output of the voltage comparator 6 changes from High-+Low to High (see FIG. 7, IN2).

These changes are 12 and 15 diodes, 13 and 1
The waveform changes as shown by BE in FIG. 7 after passing through the resistor 6, the integral composed of capacitors 14 and 17, and the inverter 18 and 19.

Due to this change, the JK-F-F output of 20 changes from OW to High voltage at time T1 (waveform of F), and 0UTl
changes from High to Low voltage, switches 10 switches, separates V, C, O and low frequency door divider 2, and
C, O control voltage to its upper limit■.

Fixed to. It is assumed that the output of the 20 JK-F-F has a reference frequency fI-ef of fr8f>.

At this time ■, 0.0 control voltage is its upper limit ■.

Since the oscillation frequency is fixed at its upper limit fm8X, the output voltage of the low-pass filter 2 draws a downward curve as shown in FIG. 7A.

As a result, the output of the voltage comparator No. 6 and then the output of the voltage comparator No. 5 change to High-+Low-*High (see FIG. 7, INI and IN2).

This change causes a change in the waveform shown in Figure 7 at the point B-E, and due to this change, the output of 21 JK-F-F changes from Low to High voltage at time T3 (the waveform shown in Figure 7G). ).

At this time, since the output of JK-F-F 20 is also High voltage, the output of AND gate 22 is also High voltage, and 2
The waveform of the integrating circuit configured with the resistor 3 and the capacitor 27 becomes a high voltage with a time delay, as shown in FIG. 7H, and resets the JK-F-Fs 20 and 21.

As a result, the waveform of 0UT1 changes from Low to High voltage, switches 10, connects V, C, and O to the reduction filter 2, and enters a synchronized state.

Also, at this time, 0UT2 does not change from High to Low voltage because it is an integrating circuit composed of 25 resistors and 26 capacitors.

Next, at time Tf, the reference frequency f ref becomes f
The output voltage of the low-pass filter of I-6 and 2 draws a downward curve, and the output voltage of the voltage comparator of 6 and the voltage comparator of 5 change to High or High.
h-+Low-+High (see INI and IN2 in Figure 7), due to this change, the output of JK-FF 21 changes from Low to High voltage, and 0UT2 becomes High.
gh to Low voltage, switch 9 is switched to separate V, C, O from the low-frequency P wave generator 2, and V, C, O
The control voltage is fixed at its lower limit, 0■.

is fixed at Ov and the oscillation frequency is its lower limit f m1n, so the output voltage of low-pass filter 2 draws an increasing curve, the output of JK-F-F 20 becomes High voltage, and 2
The AND gate output of 2 also becomes a High voltage.

This change passes through an integration circuit consisting of a resistor at 23 and a capacitor at 27, resets JK-F-F at 20 and 21, 0UT2 changes from Low to High, and the switch at 9 switches to V, C. , O and the low-pass filter 2 are connected to enter a synchronized state.

In the above embodiment, in the case of out-of-synchronization, V, C,
■ Set the O control voltage to 10.

, or fixed at 0■ with switch 9, but it is not necessarily necessary.

For example, V. It is also possible to set v2 instead of , and set ■1 instead of Ov.

However, in this case, the detection circuit has steresis.

In the case of a detection circuit having this hysteresis, if the reference frequency f ref control voltage is fixed at 2 by the switch 10.

At this time, the oscillation frequency/wave number of V, 0.0 is f2.

This state pressure is fixed at v2, but P, L, L
As a result, the output voltage of the low-pass filter 2 traces an increasing curve to raise the oscillation frequency of O, and the output voltage of the low-pass P-wave filter traces a decreasing curve to generate a synchronized state. It will return and the alarm will be canceled.

The present invention reliably detects the out-of-synchronization of P, L, and L, and detects the upper limit (if it is shifted upward) or the lower limit (if it is shifted downward) of the control range in the out-of-synchronization state. Since it has the function of stably oscillating at different frequencies, it can be widely used in general P, L, and L synchronization alarm circuits.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional phase-locked circuit, and Figure 2 is a block diagram of a conventional phase-locked circuit.
, C00 control voltage vs. oscillation frequency characteristics, FIG. 3 is a diagram showing the phase difference vs. voltage characteristics of the phase comparator, and FIG. 4 is a diagram showing the characteristics of the output voltage of the low-range two-door wave generator in the case of out-of-synchronization. 5 is a block diagram of a phase locked circuit according to an embodiment of the present invention, FIG. 6 is a specific circuit example of the detector 8 in FIG. 5, and FIG. 7 is an explanatory diagram of an embodiment of the present invention. . 1... Phase comparator, 2... Low-frequency P-wave device, 3... Voltage controlled oscillator, 4... N frequency divider, 5, 6・・・・・・Voltage comparator, 7・・・・・・
AND gate, 8...detector, 9.10...
...Switch, 11...Battery, 12,15.
...Diode, 13,16...Resistor,
14゜17...Container, 18,19...
...Inverter, 20.21...JK flip-flop, 22...AND gate, 23
~25...Resistor, 26.28...Capacitor.

Claims (1)

[Claims] 1. A voltage controlled oscillator, a phase comparator that detects the phase difference between its output signal or frequency-divided signal, and a reference frequency signal, and a DC voltage extracted from the error signal of the output of the phase comparator and applied to the voltage control. In a phase-locked circuit having a low-pass filter that applies voltage to an oscillator, a switch inserted between the low-pass filter and the voltage controlled oscillator, and a change in the DC voltage of the output of the low-pass filter and the DC voltage A detecting means for detecting whether the voltage is within the control voltage range of the voltage controlled oscillator is provided, and when the DC voltage of the output of the low frequency door is outside the control voltage range of the voltage controlled oscillator, the synchronization is determined to be out of synchronization. The switch separates the low-frequency P-wave generator and the voltage-controlled oscillator, and also applies the upper or lower limit of the control voltage to the voltage-controlled oscillator, and also controls the DC voltage of the output of the low-frequency P-wave generator detected by the detection means. An out-of-synchronization detection circuit characterized in that when a synchronization state is confirmed from the change, the switch restores the connection between the low frequency side wave generator and the voltage controlled oscillator.