JPS5953755B2 - Multi-channel remote control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a remote control system that can also be made wireless using radio carrier means, has multiple channels, and can individually select any receiver from a large number of receivers. This invention relates to a multi-channel remote control system that can be remotely controlled.

First, a conventional example of a multi-channel remote control system, which is a forerunner of the present invention, will be explained.

In addition, in this conventional example, a large number of pairs of transmitters 1 and receivers 2 are provided in a one-to-one correspondence, and address data for selecting the corresponding receiver 2 is transmitted from any one transmitter 1. The receiver 2 receives the control signal containing its own address data and transmits it by a wireless carrier, and the receiver 2 determines whether the control signal containing its own address data has been received and controls the load 3. It is also possible to make a plurality of receivers 2 correspond to the receiver 1, create a control signal for each receiver 2 in the transmitter 1, and call and control each receiver 2 individually, similar to the conventional example below. It was realized by a circuit. FIG. 1 shows a circuit diagram of the conventional transmitter 1 described above, and shows an address setting section 7 formed of something like a pinboard, and a modulation section formed of an arithmetic processing LSI such as a microcomputer. A wave generation circuit 8 and an oscillation frequency 30 that supplies a reference clock signal to the modulated wave generation circuit 8.
A reference signal generation circuit 9 of about 0KH2, a carrier wave generation circuit 10 having an oscillation frequency of about 300MH2, and a modulation circuit 11 connected in series to this carrier wave generation circuit 10 and controlled by the output of the modulated wave generation circuit 8, It is configured.

Therefore, the modulated wave generation circuit 8 is connected to the fourth row 6 of the address setting section 7.
Each of the modulation frequencies F, -F is connected to each terminal of the column, and is connected to each of the four rows of the address setting section 7. The unit time of 6 units is set by selecting , and specifying the respective timing in time series in each of the 6 columns. The read timing, that is, each unit time is sequentially specified, and the address-set row in the specified column (that is, the specified data of the modulation frequencies F1 to F4 to be generated at that timing) is read into the modulated wave generation circuit 8, and this reading is performed. The frequency of the reference clock signal output from the reference signal generation circuit 9 is divided based on the received data signal, and a predetermined modulation frequency signal is output. In this way, the modulation frequency signal that changes moment by moment for each unit time in the time series obtained as the output of the modulated wave generation circuit 8 becomes a control signal for calling and controlling the corresponding receiver 2, and this modulation frequency The signal is input to the modulation circuit 11, and the 300 MHz carrier wave generated by the carrier wave generation circuit 10 is modulated by a modulation frequency signal (i.e., a control signal) in which four modulation frequencies F1 to F4 are combined and arranged in six unit times. is emitted into space from the antenna that also serves as the oscillation coil 12.
Therefore, the transmitted radio waves have four modulation frequencies F for each of the first to sixth unit times in the time series, as shown in Figure 2a.
It is sent out as a signal modulated with one of the frequencies 1 to F4, and normally these 6 unit time time series modulated frequency signals are used for the purpose of improving the reliability of signal transmission and preventing malfunction. is sent out repeatedly as a control signal multiple times. If the receiver 2 called up by the above-mentioned control signal needs control data that determines its control contents, this control data is added in addition to the time unit arrangement of the control signal consisting of the above-mentioned address data. One or more time units for data will be added, but if the load 3 controlled by the called receiver 2 is uniquely determined and there is only one control content, , there is no need to send out separate control data, and the address setting of each receiver 2 is performed using a control signal consisting only of the address data part. A control command for the load 3 will be transmitted by the receiver 2, and when the control signal consisting of a time-series modulated frequency signal as shown in FIG. 2 is received by the receiver 2 a set number of times, this The receiver 2 at the address specified by the control signal detects its own call by determining whether the received control signal/signal matches its own set address, and thereby controls the load 3 on and off. . FIG. 2b shows the modulation frequency F1 of the control signal set by the address setting section 7.
This is a pattern diagram of the ~F4 array, and the modulated wave generating circuit 8 creates a control signal of the unit array as shown in FIG. FIG. 3 shows a circuit block diagram of a conventional receiver corresponding to the oscillator 1 described above. A gain amplifier 14 set to about 80 dB, four band-pass filters 41...44 whose center frequencies are set to F1 to F4, and the outputs of these filters 41...44 are determined, respectively. the comparators 151...154, the address setting unit 16 formed of something like a pin port, and the comparators (151)...154 formed of an arithmetic processing LSI like a microcomputer. 154) A discriminating circuit 6 inputting the output of the group and the output of the address setting section 16, and the converters 151...154
This discriminator circuit 6 has a built-in memory 5 that reads and temporarily stores the output of the transmitter 1 in synchronization with a clock signal corresponding to the unit switching frequency on the transmitter 1 side. The self-call is detected by comparing the setting contents of the section 16.

The discrimination circuit 6 which has thus detected the call further discriminates the added control data as required, and drives the speaker as the load 3 to produce a chime sound. Relay 1 that controls the speaker force drive circuit 20 and appropriate external loads
The relay output circuit 18 having a relay output circuit 7 is controlled in accordance with the contents of the received control data. Therefore, a control signal consisting of a modulated carrier signal received by the receiving antenna 19 is amplified and demodulated by the front end 13, and is inputted in parallel to each filter 41...44 via the gain amplifier 14. The filters 41...44 correspond to each of the four modulation frequencies F1...F4, and the filters 41...44 match the frequency of the demodulated signal received at that time.
・Output is generated from 44 and comparators 151...15
4, it is determined whether or not an output has occurred in each of the corresponding filters 41...44, and therefore, one of the comparators 151 is selected according to the frequency of the demodulated signal received at that time.
. . . An output is generated at the terminal 154 and input to the discrimination circuit 6. The discrimination circuit 6 includes the comparator 15 as described above.
1...154, and sequentially designate column signals to the pin port matrix of the address setting section 16, so that the output from the row in which the address setting in the designated column has been performed is read. As described above, the memory contents of the memory 5 and the address setting section 16 are inputted with the outputs of the comparators 151...154 and stored once.
It compares and discriminates the input contents from and when the two match, it discriminates whether it is calling itself, and this discrimination signal directly controls the load 3 or sets the discrimination circuit 6 to the control data reception mode. and controls the load 3 according to the content of the control data determined to have been received. Note that when controlling the load 3, when controlling the illustrated speaker drive circuit 20, a signal obtained by appropriately frequency-dividing the internal clock signal is given from the discrimination circuit 6, and the speaker is caused to sound by this frequency-divided signal. be. By the way, in the conventional system as mentioned above, there are multiple units (6 in the above column).
Each receiver 2 receives a control signal consisting of a combination of frequency signals, and determines whether or not the arrangement pattern of each frequency signal matches the setting address pattern set by the address setting section 16. In this case, as mentioned above, the outputs of the comparators 151...154 are
The clock signal of the frequency corresponding to the unit switching frequency on the transmitter 1 side is read sequentially, and the read frequency arrangement pattern of each unit, that is, the memory pattern stored in the memory 5 and the setting pattern in the address setting section 16, is The structure is such that it compares and discriminates.

However, it is not only difficult to make the clock signal on the receiver 1 side completely match the unit switching frequency on the transmitter 1 side, but also to determine the exact cycle between the unit switching timing and the clock signal generation timing. The problem was that it was completely impossible to do so. That is, for example, a control signal is sent from the transmitter 1 in a unit arrangement pattern of FlF2F3F4F2F4, and each comparator 15 on the receiver 2 side has a mutual time relationship as shown in FIG.
1,15. ...154, and if the clock signals for reading the outputs of the comparators 151...154 are generated in the discrimination circuit 6 with the timing relationship as shown in the figure e, each The storage contents in the memory 5 in which the frequency signals F1 to F4 correspond to rows and each time unit corresponds to columns are as shown in FIG. 5, and a pattern is stored with data completely different from the data of the transmitted control signal. Therefore, the pattern cannot be matched with the pattern set by the address setting section]6, and reception becomes impossible. In the conventional example, it is impossible to accurately match the timing relationship between the transmitter and receiver 1 and 2, so the reference frequency signal generation section in the transmitter and receiver 1 and 2 is controlled by crystals, etc. Therefore, even if the unit switching frequency and the frequency of the clock signal are made to match as much as possible, there is a problem that the above-mentioned reception is not possible. The present invention has been provided in view of the above-mentioned points, and the present invention prevents reception failure even when the synchronization timing between the transmitter and the receiver differs from each other. The object of the present invention is to provide a multichannel remote control system that can be remotely controlled and has improved reliability. An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 6 shows a block diagram of the main parts of the receiver 2 according to an embodiment of the present invention, and the other circuit parts of the receiver 2 and the transmitter 1 are constructed in the same manner as in the conventional example described above. However, in the embodiment circuit, in the receiver 2,
A plurality of memories 5, 5 are provided in the discrimination circuit 6, and a plurality of types of clock signals A, B having mutually different phases are created as clock signals for reading the outputs of the comparators 151...154. .
, B to each corresponding memory 5,
It will be stored in 51. That is, when output signals are generated in the comparators 151...154 with the time relationships as shown in FIG. 7a to d, as in the case of FIG. 4, the output signals A as shown in FIG. , B types of clock signals are used to read the outputs of these comparators 151...154 into the discriminating circuit 6.
The read signal from the clock signal B is stored in the memory 5, and the received data is stored in a pattern as shown in Figure 8A, and the read signal from the block signal B' is stored in the memory 51, and the received data is stored in the pattern shown in Figure 8B. The received data will be stored in a pattern. Thereafter, the discrimination circuit 6 detects that the memory contents of the memory 5 include a blank time unit (no modulation frequency signal) and cancels the memory contents of the memory 5, while canceling the unit arrangement of the memory contents of the memory 51. It determines that the pattern matches the pattern of address data set by the address setting section 16, and determines and detects its own call. Since the present invention is configured as described above, among the data stored in each memory that is generated in different phase relationships and read into the corresponding memory using a plurality of types of clock signals, the data stored in any one of the memories The data pattern exactly matches the transmission signal pattern, and therefore, the receiver called up at this time uses the pattern of the stored contents of one of the memories mentioned above and its own address set in the address setting section. When the data pattern matches, the matched memory contents can be determined as a regular control signal and the receiver can perform load control operations. This has the effect that no matter what kind of synchronization error occurs, reception is not impossible, and highly reliable remote control can be performed.

[Brief explanation of the drawing]

FIG. 1 is a plotter diagram of a conventional transmitter, FIG. The figure is a block diagram of a receiver corresponding to the above transmitter, Figures 4 a-e are time charts for explaining the operation of the above circuit, Figure 5 is a pattern diagram of data storage contents in the same memory, and Figure 6 7 is a block diagram of a main part of a receiver according to an embodiment of the present invention, FIGS. 7a to 7e are time charts for explaining the operation of the same, and FIG. In the figure, 1 is a transmitter,
2 is a receiver, 3 is a load, 41, 42... are filters,
5 is a memory, and 6 is a discrimination circuit.

Claims (1)

[Claims] 1 One or more transmitters and multiple receivers are provided, and a control signal created by assigning a combination of multiple frequency signals to each unit time of multiple units is transmitted at any one time. In a multi-channel remote control system, the frequency of each frequency signal included in the control signal is transmitted from the control signal and received by an arbitrary receiver selected by the address data included in the control signal to control the load. A plurality of filters each distinguishing the components, and the output state of each of the filters is determined in synchronization with a plurality of types of clock signals having a frequency substantially matching the unit switching frequency on the receiver side and having mutually different phases. A memory corresponding to each of the above clock signals to be read and stored, and received data that includes data that matches the address data assigned to the own receiver from among the received data stored in these memories are selected and extracted, and reception control data is generated. A multi-channel remote control system comprising a receiver equipped with a discrimination circuit.