JPS596546B2 - Frequency division method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency division method, and more particularly to a frequency division method in a frequency modulation circuit in which a modulation frequency is obtained by dividing the output of a high frequency oscillator.

The conventional circuit for frequency modulating binary input data is 2.
One possible method is to prepare seed frequencies and to switch and output these frequencies using input data o'' and 1'', one example of which is shown in FIG.

In the method shown in FIG. 1, the output of a high frequency oscillator 1 is divided into different frequencies fH and fL by frequency dividing circuits 2a and 2b, and these are divided into gate circuits 3a, 3b and 3b by input data 0 and 1. It is outputted via the gate circuit 4. However, this circuit is an analog circuit using an analog high frequency oscillator using a capacitor or a coil, and requires an oscillator or frequency dividing circuit for each frequency. Therefore, if a large number of frequencies are required depending on the data speed of the line or the model, a frequency dividing circuit must be prepared for each frequency, which increases the circuit scale and is difficult to implement. Furthermore, since analog circuits were used, it goes without saying that this would be an obstacle in implementing LSI in the future. The purpose of the present invention is to perform frequency division using a type of oscillator and a type of frequency divider circuit at a frequency division ratio including decimal numbers to obtain various required frequencies, and to digitize it to be suitable for LSI. The object of the present invention is to provide a frequency division method.

According to the present invention, a frequency modulation circuit that divides a fundamental frequency signal into another frequency signal in accordance with input data includes a presettable counter to which a frequency division value is preset, and a first frequency dividing circuit that divides the fundamental frequency signal based on the frequency of the fundamental frequency signal; and a second frequency dividing circuit that includes means for counting the frequency divided output of the first frequency dividing circuit and that generates a plurality of counted outputs within a fixed period. a frequency dividing circuit; and a frequency dividing ratio variable means for storing a preset value to be inputted to the first frequency dividing circuit corresponding to the input data, the line speed data, and the output count value from the second frequency dividing circuit. A frequency division method is proposed, characterized in that the frequency division ratio of the first frequency division circuit is changed based on the periodic count output from the second frequency division circuit.

Embodiments of the frequency division method according to the present invention will be described in detail below with reference to FIG. 2 and subsequent figures.

The gist of the present invention is to use a presettable counter as a frequency divider circuit to obtain various required frequencies using one type of oscillator and one type of frequency divider circuit, and to adapt it to each input data of each necessary model. The idea is to change the setting of the frequency division ratio by switching between different modes to transmit various frequencies.

One embodiment is shown in FIG. In FIG. 2, a high frequency oscillator 11 generates high frequency clock pulses, and a frequency dividing circuit 12 connected thereto uses a presettable counter that can appropriately select the setting of the frequency dividing ratio. The frequency division ratio variable circuit 13 supplies the frequency division circuit 12 with input data and a preset input for controlling the frequency division ratio of the frequency division circuit 12 by changing the mode of the model or the like. The output of the frequency dividing circuit 12 is counted by a counter 14 using a known method, converted into an analog signal by a DA converter 15, and outputted through a filter 16 as frequencies FH and fL. In the circuit configured as shown in FIG. 2, when obtaining a desired frequency from the high frequency oscillator 11 by frequency division, it is necessary to select the oscillation frequency of the high frequency oscillator 11 to be a common multiple of a plurality of carrier frequencies.

However, since the types of carrier frequencies are generally limited, it is possible to select a main oscillation frequency that is a common multiple of the carrier frequencies, but it is possible to use a single high-frequency oscillator to change the carrier frequency of many models by simply switching modes without changing the frequency. If desired, it is difficult to select a high frequency oscillator having a common multiple of a large number of carrier frequencies, for example, 5 to 10 types. Here, it would be convenient if the desired frequency could be obtained by performing frequency division using a frequency division ratio that includes decimal numbers, rather than relying on an integer frequency division ratio. A feature of the present invention is that the frequency division ratio including decimal numbers can be set in the frequency division circuit 12 shown in FIG.

FIG. 3 shows the mutual relationship between the frequency dividing circuit 12 and the frequency dividing ratio variable circuit 13 of the present invention. In FIG. 3, the frequency dividing circuit 12 is
It is configured to include a frequency dividing circuit 21 and a second frequency dividing circuit 22. In the circuit of FIG. 3, setting of a frequency division ratio including a decimal number is performed by first approximating the decimal part with a fraction.

In other words, in terms of the circuit, the output of the first frequency dividing circuit 21 is further divided into 1/8 by a second frequency dividing circuit that counts, and the output of each frequency dividing element 22a, 22b, 22c of the frequency dividing circuit is divided by the frequency division ratio. The frequency dividing ratio from 1/8 to 8/8 as shown in FIG. 4 is set by inputting the signals to the variable circuit 13 and controlling the gate conditions of their outputs.
Then, one selected from among these frequency division ratios from 1/8 to 8/8 is applied to the first frequency division circuit 21 as a decimal fraction. The first frequency divider circuit 21 is formed using a presettable counter.

For example, to divide the frequency by 20.375, in other words, to divide the frequency by 201, input the output of FIG. Input 5 cycles and 3 cycles alternately. Then, the frequency of output 2 will be 2 at the output of the second frequency divider circuit 22.
The frequency is obtained by dividing by 0 five times and dividing by 21 three times, and the output 1 obtains a frequency approximately divided by 20.
The frequency waveform of output 1 is applied to counter 14 . Fifth
The figure shows a timing chart of waveforms in each part of the frequency dividing circuit 12. FIG. 5a shows the clock pulse waveform of the high frequency oscillator 11, FIG. The waveforms appearing at elements 22a, 22b and output 2 are shown.

In addition, in Fig. 5 f, 5 cycles and 3 cycles are alternately displayed.
FIG. 5g, which shows a pattern in which frequency division by 0 and division by 21 are repeated, shows the preset input, that is, the minimum bit position. FIG. 6 shows the contents of the storage device included in the frequency division ratio variable circuit 13,
Stores input data, speed, ie model mode, division ratio conditions, and output data.

and (a) input data O'' or S1'', (b)
Output data is output to the preset terminal by addressing the line speed condition and (c) frequency division ratio condition.
As explained in detail above, according to the present invention, frequency division is performed using a frequency division ratio variable circuit, one oscillator, and one frequency division circuit, with a frequency division ratio that includes decimal numbers, regardless of the integer frequency division ratio. Not only can a wide variety of frequencies be generated corresponding to each model, but the circuit according to the present invention can be processed entirely digitally, so it can be configured compactly using an integrated circuit, and is suitable for LSI. However, the effects of the present invention are still significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a conventional frequency dividing circuit, FIG. 2 is a block diagram of a frequency dividing method according to the present invention, and FIG. 3 is a block diagram of an example of a frequency dividing circuit and a variable division ratio circuit in FIG. Detailed block diagram, Figure 4 is a waveform diagram of the preset input of the frequency divider circuit in Figure 3, Figure 5 is a waveform diagram of each part in the block diagram in Figure 4, Figure 6 is the frequency division ratio variable diagram in Figure 3. Shows the contents of the circuit's memory. In the figure, 12 is a frequency division circuit, 13 is a frequency division ratio variable circuit, and 2
1 is a first frequency dividing circuit, and 22 is a second frequency dividing circuit.

Claims (1)

[Claims] 1. A frequency modulation circuit that divides a fundamental frequency signal into another frequency signal in accordance with input data, which includes a pull-settable counter to which a frequency division value is preset, a first frequency dividing circuit that divides the frequency of the fundamental frequency signal based on a value; and a first frequency dividing circuit that includes means for counting the frequency divided output of the first frequency dividing circuit and that generates a plurality of counted outputs within a fixed period. 2 frequency dividing circuit, the input data, line speed data,
and frequency division ratio variable means for storing a preset value to the first frequency divider circuit corresponding to the output count value from the second frequency divider circuit, A frequency division method characterized in that the frequency division ratio of the first frequency division circuit is changed based on a count output. 2. The frequency division method according to claim 1, wherein the frequency division circuit is constituted by means for dividing the basic signal by an integer. 3. The variable means counts the period of the frequency-divided signal of the frequency dividing circuit, and changes the frequency division ratio of the frequency dividing circuit according to the counted value, or Second
Frequency division method described in section.