JPS597226B2 - Charge injection method into charge-coupled devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a charge-coupled device (Charge-Coupled Device).
The present invention relates to a charge injection method for CCD devices (CCDs), and more particularly to a charge injection method for injecting a uniform charge into a plurality of CCD channels driven by a single-phase pulse.

In recent years, with the rapid development of semiconductor integrated circuit technology, charge-coupled devices have been developed that are characterized by the ability of carriers in a thermal nonequilibrium state to freely move within a silicon substrate. A wide range of applications have been proposed for this device (CCD), one of which is analog delay lines. The figure of merit of a CCD is the non-transfer efficiency, which is the proportion of carriers that are left behind when carriers are moved between potential wells localized under the electrodes by controlling a pulse between two adjacent electrodes. .
Ideally, the efficiency would be 0, but it is known that it actually becomes about 10-4 due to various factors. It has been experimentally confirmed that when operated as a delay line, the response at high frequencies is reduced due to this efficiency. In order to minimize the reduction in response, multiple CCs
It is known that it is effective to arrange D channels in parallel to reduce the number of elements per channel. It has been reported that in this configuration method, providing a single carrier injection section and a single carrier detection section is effective in eliminating differences in characteristics between the channels (1971).
(Lecture number 339) at the annual National Conference of the Institute of Electronics and Communication Engineers. On the other hand, CC
Since the electrode structure of D is essentially equivalent to a MOS capacitor, the source of the pulses supplied to the electrode is a capacitive load.

The capacitive load increases to 10 as the degree of CCD integration increases.
It may even reach 0OPF. Generally, when a capacitive load is driven with a rectangular wave pulse, there is no power consumption in the load section, and power consumption occurs only in the internal impedance of the pulse generation source. It is known that this power consumption is proportional to the drive pulse repetition frequency, the load capacity, and the square of the pulse amplitude.
It may even reach W. Such high power consumption
This is a big problem when driving a CD. The inventor has already published JP-A-47-27630 (JP-A-46-20885).
, he invented and proposed a driving method that uses a DC power source to reduce the number of pulse generators, thereby reducing the power consumption and cost of the CCD peripheral circuit. If the invention is applied to a conventional two-phase drive type CC1), it can be driven by a single pulse generator and a single DC power supply, and the plurality of CCD channels described above can be arranged in parallel. In combination with this construction method, it is possible that an analog delay line can be constructed very easily. However, this method of construction has the disadvantage that the conventionally known carrier injection method cannot be used, so that the construction of the delay line cannot be realized. The object of the present invention is to eliminate such drawbacks and to provide a charge-coupled device for stably and low-noise carrier injection into two parallel CCD channels, driven by a single pulse generator and a single DC power supply. The object of the present invention is to provide a charge injection method.

Next, a detailed explanation of the present invention will be given with reference to the drawings.
The figure is a diagram explaining that a two-phase drive type CCD is driven by a single pulse generator and a single DC power supply.

In the same figure a, 1 is a P-type silicon substrate, 2 is an insulating film such as thermally oxidized silicon, and 3, 3', 3'''' are first layer electrodes made of polycrystalline silicon, molybdenum, etc., and are connected to a common wiring 5. It is connected. Reference numerals 4 and 4' denote a second layer electrode group made of polycrystalline silicon, aluminum, etc., and are connected to a common wiring 6.

Furthermore, although the ends of the first and second layer electrodes overlap with each other through a portion of the insulating film 2, they are electrically insulated. Furthermore, as shown in the figure, the thickness of the insulating film under the electrode is not uniform, and there are parts where the insulating film thickness is locally large. Such an asymmetric structure under the electrode causes a difference in the interfacial potential between the substrate 1 and the insulating film 2 when a voltage is applied to a single electrode, e.g. It has the effect of localizing it in the region under the electrode where the insulating film thickness is small. That is, the interfacial potential between 1 and 2 under the electrode changes approximately in a step-like manner in portions where the thickness of the insulating film differs, creating a potential barrier. The height of the barrier is determined by the difference in thickness of the insulating film 2. On the other hand, it is well known that the height of such a barrier can also be controlled by providing a region on the surface of the substrate 1 with a different impurity concentration from that of the substrate, as shown at 7. FIG. 1d shows the pulse and DC potential for driving the CCD (a (7)) once. In the figure, reference numeral 15 is a pulse that alternately generates voltage levels of 0V and 20V, and is applied to the wiring 5. On the other hand, 16
is applied to the wiring 6 at a DC potential of 10V. In addition, 15
, 16 are shown as examples, and are not limited to these values. However, 15
Preferably, the pulse peak value of (eg 20V) is twice the DC voltage level (eg 10V). Figure 1B,
c shows the magnitude of the interfacial voltage between 1 and 2 at times Tl and t2 in d of the same figure, respectively, corresponding to the structure of a in the same figure. CC composed of 3 and 4, 3'' and 4'
If we pay attention to the element part in the unit D, the voltage is maximum within one period of the pulse 15 (in B and c, the downward direction in the drawing is shown as a positive voltage, so that it is easy to understand the concept of the potential well mentioned above). ing.

) is clearly swapped. That is, a well with the deepest potential is formed under the electrode 4 at time t1 and under the electrode 3 at time T2, and carriers are localized in these regions. As a result, it is clear that the two-phase drive type CCD of FIG. 1a can be driven by the pulse of the drive waveform and the DC voltage shown in d. FIG. 2 schematically shows a plan view of a carrier injection section when two two-phase drive type CCDs shown in FIG. 1a are arranged in parallel.

In the figure, 20 is a diffusion layer buried in a silicon substrate and has a different conductivity type from the substrate, 21, 22, 23 are electrodes, 24, 25, 24', 25' and 26, 27, 26.
', 27' are electrodes constituting the CCD, and as shown in the figure, four wirings 28, 28', 29,
29'. Also, 24, 25, 26, 2
The diagonal lines on the electrode parts such as No. 7 indicate that there is a part with a large insulating film thickness or a part with an impurity concentration different from that of the substrate as shown in Figure 1a below. It shows. Figure b shows a timing chart of pulses applied to each part to explain the operation of point a. In the same figure, 38, 39 are 28, 28' and 2, respectively.
Pulses 33 and 30 applied to the wirings 9 and 29' have pulse waveforms applied to the wirings 23 and 20, respectively. Time T shown in the figure. Since the diffusion layer 20 is slightly reverse biased by 30, carriers move from this region to under the appropriately biased electrodes 21 and 22. Next, at time t1, 20 is again strongly reverse biased, so a portion of the carrier below 22 returns to 20 using the interface potential below 21 as a barrier. As a result, the number of carriers corresponding to the difference between the voltages applied to 21 and 22 is accumulated under 22. Next, at time T2, a pulse 33 is applied to the electrode 23. At this time, a voltage is applied to the electrode 24 and 26 is at ground potential, so the carrier moves from 22 to 23 and only to part 24. Similarly, the carrier that has moved down 22 at time T3 moves only to section 26 through 23 at T4. Details of the carrier injection method for such a structure are described in the Television Society of Japan's Television Electronic Device Research Group Material Electronic Device Research No. 265. Second
The CCD delay lines of the configuration shown in the figure are 28, 28', 29
, 29', the two-phase pulse 38, 3 whose phase is delayed by 180
It is possible to operate if 9 is supplied. However, 2
8, 28' or 29, 29', and a DC voltage is applied to the other one, that is, the operation mode illustrated in FIG. When doing so, it can be seen that carrier injection into either region 24 or 26 is not achieved. As a result, in the configuration example shown in FIG. 2, it becomes difficult to reduce power consumption in peripheral circuits such as a pulse generator. Fig. 3 is Fig. 5 for explaining one embodiment of the present invention;
The same numbers as in the figures indicate the same components. In FIG. 1A, 40 is an electrode corresponding to 23, which is located between the electrodes 22, 24, and 26. Below the electrode, a difference in oxide film or a difference in substrate impurity concentration occurs in the shaded area. Figure b is a diagram for explaining the operation of an embodiment of the structure shown in figure a, and 48 is a diagram showing 28 and 2.
8', and 49 indicates the DC voltage level supplied to 29 and 29'. 41 is a pulse waveform applied to the electrode 40.

Figures 4A and 5b are A-A' and B-B of Figure 3a, respectively.
3 is a diagram illustrating a cross-sectional structural diagram at a portion indicated by ' and a substrate-insulating film interface potential at each time shown in FIG. 3b in correspondence with the cross-sectional structural diagram; FIG. Note that the structural diagram is drawn as a model, and the electrodes 540, 24,
Shaded areas 25, 26, and 27 are indicated by differences in insulating film thickness. The carrier injection method will be explained below using FIGS. 3 and 4. At time T5, the diffusion layer 20 is slightly reverse biased by the pulse 30, so that the electrodes 21, 2 to which a DC voltage is applied by an appropriate reverse bias means 4
Carrier flows under 2. Next, at time T6, 30 becomes 2.
0 is again strongly reverse biased, carriers 50 corresponding to the difference in the voltages applied to 21 and 22 are accumulated in the potential well below electrode 22. Note that 40 is 41 at that time.
Since the potential barrier 51 is formed corresponding to the thicker insulating film portion below the insulating film 40, the carrier 50 is prevented from flowing into the CCD channel region. Next, at time T7, since a positive voltage is applied to 40 by 41, the barrier 51 moves to the position shown at 52, and the barrier 50 disappears. As a result, at time T6, the carrier 50 localized below 22 flows into the area below 40 and becomes carrier 50'. Furthermore, the time T7
, since a larger positive voltage is applied to 24 than to 26, 50' moves to a region below 24 where the insulating film thickness is small. However, as shown in Figure 4b, at time T
In 7, since there is a barrier 53 in the region with a large insulating film thickness below 26, 50' cannot overcome 53, so the CC composed of 26, 27, 26', and 27'
No carrier injection occurs in the D channel. Of course, in order for such operation to occur properly, the voltage level of 52 is preferably at a more positive potential with respect to the pressure level of 53, i.e., 53 can act as a barrier to the carrier. As such, the voltage relationships to 22, 40, and 26 must be maintained. Since the relationship changes depending on the element structure, element dimensions, or manufacturing process, it is difficult to unambiguously set the potential relationship, but it is possible to set the relationship by referring to the description in this specification. This is easy for many engineers. Next, after time T7, the voltage applied to 40 becomes the ground potential, and 20, 21, 2
The carrier injection portion consisting of 2 is electrically isolated from the channel region by a potential barrier 54. At this time, 20 is again slightly reverse biased and the carrier flows into the 21 and 22 regions. At time T8, since 20 is strongly reverse biased, carrier 55 corresponding to the difference in voltage applied to 21 and 22 is accumulated under 22 and does not cross over barrier 54. At time T, a positive voltage is applied to 40 by 41, so the barrier 54 disappears as in the case of time T7, and the carrier 55 flows into the region below 40 where the insulating film thickness is small, and the carrier 55 '. However, at time T9, compared to time T7, 24,
The magnitude relationship of the voltages applied to 26 is reversed. For this reason, the carrier 55r cannot overcome the respective potential barriers 56 and 57 existing below 24 and 26, and remains localized below 40. After time T9, in the process of the pulse 41 returning to the grounding position, the interfacial potential of the region where 55' is localized approaches the grounding potential. In this process, 55' moves to a region below 26 where the insulating film thickness is small, as indicated by a broken line 58. However, in this process, since 56 necessarily acts as a potential barrier, 55' does not move to the lower region of 24. Following this action, the carrier 55
is injected only into the CCD channel consisting of 26, 27, 26', and 27'. As described in detail above, according to the present invention, carriers can be alternately injected into two parallelly arranged CCD channels driven by a single pulse generator and a single DC power supply, so that the peripheral circuit This has the great advantage of simplifying the process and reducing power consumption. FIG. 5 is a diagram showing another embodiment of the present invention, and FIG.
A feature is that the electrode 40 in the figure is divided.

In FIG. 3A, the same numbers as in FIG. 3 indicate the same parts. In diagram a, the electrodes 60 and 61 may be at either the first-layer wiring level or the second-layer wiring level, but it is preferable that their ends overlap each other with an insulating film interposed therebetween. moreover,
The element structure may be such that there is no difference in the interface potential when the same voltage value is applied to 60 and 61. In the case of such a structure, 70 and 71 are added to 60 and 61, respectively.
It is necessary to apply pulses with different DC levels as shown in FIG. That is, the pulse 71 has the same waveform as the pulse 70, but is characterized in that a direct current positive voltage is superimposed thereon. It is clear that the direct current positive cage pressure causes a difference in the interfacial potentials under 60 and 61, similar to the structural asymmetry under 40. Incidentally, pulse groups such as 70 and 71 can be easily generated by the circuit configuration shown in FIG. 5c. In the figure, 75 is a Parnu generator, which generates a pulse 70 via a terminal 72. 76 is a DC blocking capacitor, 77 is a clamping diode, and 74 is a DC IE voltage application terminal.

It is clear that according to the circuit configuration, the pulse 71 can be obtained via the terminal 73. According to the configuration shown in FIG. 5, the present invention can be implemented without complicating the peripheral circuits. The present invention has been described above in detail by giving examples.

In the explanation, an n-channel surface channel type CCD is used as an example, but it is clear that the present invention can be widely applied to a p-channel CCD, a balta channel type CCD, a multiphase drive type CCD, etc. by modifying the voltage relationship. . Furthermore, since the lattice structure of a two-phase, one-drive type CCD is irrelevant to the essence of the present invention, the present invention is applicable to elements of various structures. Furthermore, the voltage relationships and timing relationships used in the description are merely examples, and may be widely modified as long as the operations described in this specification are normally achieved. Note that the part consisting of 20, 21, and 22 in FIG. 3 is a carrier injection section, and when it is desired to modulate the carrier amount with an external signal (delayed signal), the signal can be superimposed on 22 (,). . On the other hand, there are many known structures for the implantation part, such as a structure in which a diffusion layer is buried under the 22, or a structure in which the 22 is not present, but the structure of the injection part itself is unrelated to the present invention. The thing is,
This is clear from the description in this specification.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a CCD1 driving method performed by a single PURNU generator and a single DC power supply. FIG. 2 is a diagram illustrating a conventional carrier injection method when two two-phase drive type CCD channels are arranged in parallel.
FIG. 3 is a diagram illustrating an embodiment of the present invention, in which a is a schematic drawing showing the structure and b is a drive timing chart. FIG. 4 is a drawing for explaining in detail carrier injection in the embodiment of FIG. 3. FIG. 5 is a diagram showing another embodiment of the present invention. In addition, the same numbers indicate the same parts in the above drawings. In the figure, 1: p-type silicon substrate, 2: thermally oxidized silicon, 3, 3', 3': first layer electrode group, 4, 4': second layer electrode group, 5, 6, 28, 28' ，
29, 29'; Wiring, 7: Conductive layer opposite to the substrate, 20:
Diffusion layer, 21, 22, 23, 24, 24', 25, 25
′, 26, 26゛, 27, 27′, 40, 60, 61:
Electrode, 72, 73, 74: terminal, 75: pulse generator,
76: Shows DC blocking capacitor, diode for 7J lagoon lamp.

Claims (1)

[Claims] 1 A plurality of electrodes are arranged on a semiconductor substrate having an insulating film on the surface, and each of the electrodes includes two regions with different structures under the electrode, and the electrode has two regions, a first and a second. a charge-coupled device arranged to form a signal channel, the channel driven by a single pulse generator and a single DC voltage, provided at one end of the first channel and the second channel; A charge injection method into a charge coupled device, characterized in that the amount of carrier injection from a single carrier injection source is controlled by an external signal, and the carriers are alternately moved to the two channel regions each time the charge is injected.