JPS597983B2 - Data guide - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing method for controlling the exchange of data between a data processing device having a predetermined machine cycle time and an external device whose machine cycle time is not necessarily synchronized. be.

The external device referred to here refers to a unit or device that operates at independent timing, such as a memory unit or an input device. Since the present invention is related to machine cycle time as mentioned above, let me explain this point first.Most data processing devices have a certain set of machine cycles, and one machine cycle per machine cycle. Perform basic movements.

This basic operation is defined by a microprogram read from the control storage unit. Specifically, a timing pulse is created that repeats every machine cycle, and the unit address is sent to the control storage unit by the timing pulse, and the data at that address is read out.
The operation indicated by the data is executed. During execution or as a result of execution, basic operations are executed by changing the states of various registers and flip-flops by the timing pulses. This machine cycle is also called an arithmetic cycle. When processing data by combining a data processing device with a certain machine cycle time and a memory unit with a certain access time, the memory access time is an integral multiple of the machine cycle time of the data processing device. It is desirable to be familiar. Generally, the access time of a memory unit is made constant. However, even with such a configuration, the access time seen from the data processing device cannot be said to be constant.
This is because, in addition to the data processing device, a channel device is connected to the memory unit, and if the data processing device is in use, a request for use from the data processing device will have to wait until the access by the channel device is completed. be. Therefore, in conventional devices with such a configuration, as will be explained in detail later, the microphone port program becomes large, and when creating it, careful attention must be paid to the relationship with the access time of the memory unit. Various inconveniences have been caused by stopping the pulse. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a data processing method that makes it easy to create a small microprogram and eliminates the need to stop timing pulses.

In the data processing method of the present invention, a signal is sent from a data processing device to a memory unit that stores data using a storage element, and based on this signal, data is read from the storage element and sent to the data processing device. In a data processing method in which data processing is performed, a 51st signal sending means (within the data processing device) sends a memory unit starting signal mainly for reading instructions to the memory unit; A first storage means (inside the memory unit) that stores the data specified from the read set as a read set, and the data will be set in the first storage means shortly before the time at which the above-mentioned data is set. A second signal sending means (inside the memory unit) for sending out a response signal as a notice to the data processing device, a second storage means (inside the data processing device) for setting and storing this response signal, and a second signal sending means (inside the data processing device) for setting and storing this response signal. determination means (within the data processing device) for determining whether or not the storage means is stored in the storage means of No. 2; after the cycle of calculations or after an arbitrary time, a data reading means ( This is a data processing method that includes (within a data processing device).

In the above data processing device, when the state of the second storage means is determined and it is determined that the response signal is not stored, the data read gate signal is sent even if the data is not read as a result. When it is determined that the response signal is stored by alternately repeating the sending of the response signal and determining whether the response signal is stored, or by repeating only the determination of whether the response signal is stored. The above-described data reading operation is then performed. Next, a detailed description will be given with reference to the drawings.

FIG. 1A and FIG. 1B are diagrams showing an example of access time in a conventional data processing system shown to clarify the features of the present invention.

In FIG. 1A, at time a of machine cycle 2, a memory unit activation signal designating reading is sent to the memory unit. The timing pulses in the data processing device are cycle 2, cycle 3, cycle 4, cycle 5, etc.
...occurs continuously. However, if there is no longer any need to read data from the memory unit, the timing pulse continues to be generated and the execution operation of the data processing device is stopped. If data is sent from the memory unit at time b in the middle of cycle 5, it will not arrive in time for cycle 5 and will be used after cycle 6. In order to be used after cycle 6, data must be set in a register within the data processing device at the start of cycle 6. In order to set the register at the beginning of cycle 6, the gate of the register to be set must be opened by the microprogram read at the end of cycle 4 or at the beginning of cycle 5. The actual access time is 4 cycles from 2 to 5. However, this method is good as long as the memory access time is always constant, for example, 4 cycles, but problems arise when the value changes. That is, for example, as shown in FIG. 1B, at time a of cycle 2, a memory unit activation signal specifying readout is sent to the memory unit, and in cycle 4,
If data is sent from the memory unit at time b, it will not arrive in time for cycle 4 and will be processed after cycle 5, but in order to be processed after cycle 5, the first
Using the same concept as in Figure A, the gate of the register to be set must be opened by the microprogram read at the end of cycle 3 or the beginning of cycle 4. In other words, the actual access time is 2~
There will be 3 cycles of 4. Although not shown in the figure, if the memory access time takes until time b of cycle 6, in order to set it in the register at the start of cycle 7, read it at the end of cycle 5 using the same concept as before. The gate of the register to be set must be opened by the microprogram executed, and the actual access time is 5 cycles (2 to 6). This means that the microprogram that should open the gates of the registers to be set in the data processing device will start from the end of cycle 3 to cycle 5.
This shows that there is a drawback that the data must be read repeatedly until the end of the process. In other words, it is necessary to read out a microprogram that always opens the gate of the register from the minimum time to the maximum time of the memory access time, which has the disadvantage of requiring a large microprogram. FIG. 1C shows another example of access time in a conventional data processing system.

In this method, the timing pulse is stopped after a certain period of time (the second cycle in the figure) or immediately after sending a memory unit activation signal specifying readout to the memory unit at time a of cycle 2, The timing pulse is restarted at time b when data is sent from the memory unit. In this method, it is necessary to stop the timing pulse, which is inconvenient if other circuits within the data processing device require the timing pulse during the memory access time. Also, if you want to stop only the timing pulses related to memory access and leave other timing pulses generated,
This has the disadvantage that a phase difference occurs between the timing pulse related to memory access and other timing pulses, making it impossible to use the memory answer data in circuits for other timing pulses. FIG. 1D shows an example of the access time in the data processing method of the present invention, and shows that even after the memory unit activation signal, which mainly specifies readout, is sent to the memory unit at time a of cycle 2, the timing remains unchanged. Timing pulses are generated continuously in cycle 3, cycle 4, etc. without stopping the pulse.

Then, a response signal is received from the memory unit a predetermined time t before time b of cycle 4 when data is sent from the memory unit, that is, at the start of cycle 4.
This response signal is only accepted by the data processing device and does not have any active effect on data processing within the processing device. When the processing to be performed during memory access in the data processing device is completed or when it becomes necessary to use memory answer data, a response signal is generated at the end of cycle 4 or the start of cycle 5. If you know that
A circuit that can immediately set data from a memory unit in a register in a data processing device by reading the contents of address (N) of a control storage unit containing a microprogram that opens the register in which memory answer data is to be set. It provides: FIG. 1E shows still another example of the access time in the data processing method of the present invention, in which the timing pulse is not stopped after the memory unit activation signal designating reading is sent to the memory unit at time a of cycle 2. Timing pulses are generated continuously in cycle 3, cycle 4, and so on. Then, a response signal is received a fixed time t before time b when data is sent from the memory unit. As in the case of FIG. 1D, this response signal is only accepted by the data processing device and does not have any active effect on data processing within the data processing device. The response signal in FIG. 1E is at the end of cycle 5 and is about two cycles longer than the response signal in FIG. 1D. This means that the access time of the memory unit as seen from the data processing device is extended. Memory answer data should be set when the processing to be performed during memory access in the data processing device is completed or when it becomes necessary to use memory answer data, that is, at the end of cycle 4 or at the beginning of cycle 5. The contents of the address (N) of the control storage unit containing the microprogram that opens the data in the register are read. However, since there is no response signal at this point, the answer data from the memory unit is not set in the register in the data processing device, and the contents of address (N) of the control storage unit are read again by the circuit shown in the embodiment of the present invention. Read out. This continues automatically until a response signal is received. As shown in FIG. 1E, if there is a response signal at the end of cycle 5 or the start of cycle 6, the answer data from the memory unit is stored in the register in the data processing device at the end of cycle 6 or the start of cycle 7. Set. In this example and the example shown in Figure 1D, we used the same expression as the signal used in conventional devices as the first signal sent to the memory unit, ``memory unit start signal for specifying readout'', but it is clear from the above explanation. It should be noted that the present invention does not require a read gate signal for sending the read set data to the data processing device, which was included in the conventional signal. It is also possible to use it as is. Figure 2 is a diagram showing an example of a control storage unit containing a microprogram for controlling a data processing device in the data processing system of the present invention. 10
0 input is the microinstruction register (MI
R) 103 and a register (REG) 101. The output of the address creation 100 is that the signal line 200 is
”, the N
When the A part is output and the signal line 200 is "1", REGlO
Output l. The output of address creation 100 is REGl
It is connected to the storage unit 102 with Ol and becomes the address of the storage unit 102. Are the contents of the address indicated in the address creation 100 read from the storage unit 102? It is set to Tiger 1R103. R
EGlOl and MIRlO3 are set by I-phase pulses at the same timing. The one-phase pulse will be explained later in the explanation of FIG. 6.

Figures 3A-1 to 3A-3 and related Figures 3B to 3E respectively show the configuration of the microinstruction set in MIR1O3 in Figure 2 and the contents of instructions for each part. Also, FIG. 4 shows a memory unit control circuit within the data processing device.

The NA section shown at the right end of FIGS. 3A1 to 3A-3 indicates the address of the next microinstruction.
As shown in Fig. 3D, the M part indicates "O" indicating no memory request, and "1" indicates there is a memory request.The W part indicates "00" indicates no specification, and "01" indicates no specification, as shown in Fig. 3E.
” specifies the IR2Ol in FIG. 4, and “10” specifies the buffer register (BR) 202 in FIG. A
Section C is constructed as shown in FIG. 3C. 0P1 part,
The 0P2 part and the D part are arranged as shown in FIG. 3B.

Further, 400 at the left end in FIGS. 3A-1 to 3A-3 is connected to the AND gate 203 and the second input gate 218 in FIG. The structure of the microinstruction related to the present invention is as shown in FIGS. 3A-1 and 3A-2. FIG. 3A-3 is used to perform control other than memory unit related control within the data processing device. Of course, Figure 3A-1, Figure 3A-2, Figure 3A-
The distinction in FIG. 3 does not strictly exist, and there is no problem even if FIG. 3A-3 and FIG. 3A-1 or FIG. 3A-3 and FIG. 3A-2 are executed simultaneously. For convenience of explaining the present invention, Figures 3A-1, 3A-2, and 3A-3 have been distinguished. The operation of the memory unit control circuit itself of FIG. 4 will be explained at various points later in connection with other explanations.

FIG. 5 shows a memory unit 300.

A data processing device, a channel device, etc. are connected to the memory unit, but these are omitted from this figure. Memory address 301 is the output of a memory address register (not shown) in the data processing device, write data 320 is data to be written to the memory element 311 at the address indicated by memory address 301, and control signal 302
is a signal that instructs the memory unit to perform a read operation, a write operation, etc., and these memory addresses, write data, and control signals are all supplied from a data processing device (not shown) as necessary. Memory unit activation signal 303 is sent through AND gate 215 in FIG. Read gate signal 304 is the output of delay flip-flop 209 of FIG. 4 and is connected to control circuit 310 and AND gate 313. A control circuit 310 performs various controls within the memory unit. That is, it receives the memory unit start signal 303 from the data processing device, sends the memory address 301 to the memory element 311, and then sends the memory address 301 to the memory element 311.
Control is performed such as opening the gate of the register 312 at the time when data is read from the register 11 and setting the data in the register 312. AND gate 313 is signal line 304
When there is a read gate signal at , the contents of the register 312 are outputted to the signal line 307 as read data. The response signal 306 is output from the control circuit 310 and is connected to the second input gate of the AND gate 213 in FIG. FIG. 6 is a diagram showing machine cycle time and time charts of gates, flip-flops, etc. in FIG. 4. Machine cycle time refers to the period from one I-phase pulse to the next I-phase pulse. From this I-phase pulse to the next I
Divide up to the phase pulse into four equal parts, and call each of them, in order, a phase pulse, a phase pulse, and a phase pulse. FIG. 7A shows a time chart of a microprogram that matches the time chart of FIG. 6.

Cycles 1, 2, 3, 4, etc. in Figures 6 and 7A
... indicates the same time. Figure 7A shows time a of cycle 1.
Address creation 100 in Figure 2 from to time b
It is shown that an address n is created in , and its contents are read from the storage unit 102 from time b to time c. The read data is set in MIRIO3 in FIG. 2 at time c and is used for various controls within the data processing device. Also, at time c, the output of address generation 100 in FIG. 2 is set to REGlOl. Time c of cycle 1 is the same time as time a of cycle 2, and in cycle 2, as in cycle 1, address X is created from time a to time b, and its contents are read at time c. Similarly, cycle 3, cycle 4, cycle 5
The data processing device sequentially reads out the microprograms and executes data processing, which will be explained in detail after the next embodiment. FIG. 7B shows a time chart of a microprogram in a special case, the details of which will be explained after the next embodiment.

Next, the operation of the data processing method of the present invention will be explained in FIGS. 2 to 7A.
The explanation will be centered on FIG. 4 with reference to the drawings. Assume that address n is output in address creation 100 in FIG. In cycle 1 of FIG. 7A, address n is supplied to storage unit 102. The contents of address n of the storage unit 102 are output to the MIRlO3 at time c of cycle 1 in FIG. 7A. The output is shown in Figure 3A-1, where the signal line 400 is "o", W is [00], and M
is [1], and NA points to address X. Since M is "1", that is, there is a memory request, the signal line 210 in FIG. 4 is enabled.Signal line 21
0 enables request control circuit 250. The request control circuit 250 controls whether the control of the previous memory request has been completed, but it is not related to the present invention and can be considered as a mere through circuit. The output of this request control circuit 250 is the AND gate 21
5 second input gate and a delay type flip-flop (hereinafter simply referred to as FF, shown as a single circle in the figure) 206
It is connected to The first input of the AND gate 215 is a phase pulse, and when the output of the request control circuit 250 is enabled and the phase pulse is output, the memory unit activation signal line 303 is enabled. FF2O6 is set when the output of the request control circuit 250 is enabled and an l-phase pulse is output, and the output is sent to a set-reset type flip-flop (hereinafter simply referred to as FF, indicated by a double circle in the figure) 207. tell.

In this figure, the above-mentioned 20
In addition to 6, there are 208, 209, and 204, and in addition to 207, there are 205 and 204 in the set-reset type flip-flop.
There are 01,202. FF2O7 holds the signal and transmits it to delay type FF2O8 and the first input gate of AND gate 213 when a phase pulse is generated. F
F2O8 is set by the l-phase pulse after FF2O7 is set. AND gate 213 is the response signal 306
The condition is not satisfied until FF2O is set-reset type.
It never sets 5. The output of FF2O8 is connected to the second input gate of AND gate 211 and request control circuit 250. The first input gate of AND gate 211 (old, is the output of FF2O5.FF2O
5 also includes a request control circuit 250 and an AND gate 21.
8 and the first input gate of AND gate 211, respectively. The input of FF2O5 is the output of AND gate 2.13. And Gate 213. The first input gate is FF2O7, which is currently "1", and the second input gate is the signal line 306, which is currently "O" since there is no response signal from the memory. Therefore, the condition of AND gate 213 is not satisfied and FF2O5 is not set. Therefore, in the AND gate 211, the second input gate 208 is "1", but the first input gate is "o", so the condition does not hold. The output of AND gate 211 is connected to the second input gate of OR gate 212 . The first input gate of OR gate 212 has a SET signal set, which is enabled only when initializing the circuit, such as when power is applied to the circuit. That is, initially it is "1", but when this circuit is operating normally, it is "o". i.e. orgate 2
Condition 12 is not satisfied, so FF2O7 continues to be set. Memory unit start signal line 303
As can be clearly seen in Figure 6, is the pulse of the cycle 2 phase,
Control circuit 310 in memory unit 300 in FIG. 5 is activated.

The control circuit 310 stores the memory address 301 in the storage element 31.
1 and controls reading or writing to the storage element 311 by the control signal 302.
The control signal is now designated as read. Further, the control circuit 310 transfers the read data to the register 310 after a certain period of time determined by the delay of the element itself after starting the read operation.
Therefore, the time can be predicted and the response signal 306 is sent to the data processing device a certain period of time before that time. What you should pay attention to here is the memory unit activation signal 30.
3, the time until this response signal 306 is not constant. This is because a channel device, etc. is connected to the memory unit in addition to the data processing device, and while the channel device, etc. is in use, the time until this response signal 306 is not constant. This is because the information is held until the access of the channel device etc. is completed. This holding control is performed by the control circuit 310. Therefore, if the response signal 306 is from the middle of cycle 3 to the middle of cycle 4 as shown in FIG.
Since it is connected to the second input gate of FF2O5, the condition of AND gate 213 is satisfied, and the I-phase pulse causes FF2O5 to
Set. The first input gate of the AND gate 213 is the output of FF2O7, which is "1". The output of FF2O5 is the first input gate of AND gate 203, FF2O
5 is inverted and connected to the first input gate of the AND gate 218, the first input gate of the AND gate 211, and the request control circuit 250. and gate 21
The second input gate of 1 is the output of FF2O8 and is set during cycle 4, so the AND gate 211
The condition is satisfied and the second input gate of the OR gate 212 is entered. The first input gate of OR gate 212 is the reset signal, which is "o". Thus, the output of OR gate 212 is generated by the second input gate and resets FF2O7 with the pulse of the subsequent phase. When FF2O7 is reset, the condition of AND gate 213 is no longer satisfied.
This prevents future response signals 306 from being accepted.
Since FF2O7 is reset, FF2O8 is also reset by the next I-phase pulse. Therefore, the condition of the AND gate 211 is no longer satisfied. The above time chart is summarized in Figure 6. In this figure, the arrow a-+b from FF2O5 to 207 is FF2O5
This shows that FF2O7 is reset by FF2O7. Further, FF2O5 is set by a response signal 306 as described later. Therefore, the time that 207 continues to be set is until the response signal 306 is received. Next, looking at FIG. is set to MIRlO3 at the beginning of cycle 2.

The set data controls various gates, flip-flops (FF), etc. in the data processing device during cycle 2.
The data set in RlO3 has the configuration shown in FIG. 3A-1. If there is work unrelated to the memory unit in the data processing device while the memory unit is being read, the microprograms at addresses X, x+1, and x+2 must be executed. Therefore, the NA section of the data at address n indicates address x in FIG. 3A-1, the NA section of the data at address X indicates address x+1, and the NA section of the data at address x+1 indicates address x+2. x from address x
The structure of the data at address +2 is as shown in FIG. 3A-3, where 400 is "O". However, in cycles 2, 3, and 4 of FIG. 7A, addresses of microprograms X, x+1, and x+2 are created, and various gates, flip-flops, etc. in the data processing device are created in cycles 3, 4, and 5. By controlling this, when there is no more work to be done in the data processing device, or when it becomes necessary to use data from the memory unit, address n+1 of the microprogram is read. The microprogram at address n+1 is MIRlO3 at the start of cycle 6.
is set to . The data set in MIRIO3 has the configuration shown in FIG. 3A-2. i.e. 400
is "1", and the register in which the data from the memory unit is to be set is specified in the W section. Note that the n+1
The address does not necessarily have to be the n+1 address, but may be any address, as long as it has the configuration as shown in FIG. 3A-2. The second inputs of AND gates 218 and 203 in FIG.
If 00 is [0], neither condition is satisfied. 7th
At the beginning of cycle 6 in Figure A, the contents of address n+1 are read to MIRIO3. 400 in FIG. 3A-2 showing the contents of this address n+1 is "1", and the signal line 400
enable. Signal line 400 is connected to the second input gate of AND gate 203 in FIG. The first input gate of the AND gate 203 is FF2O5, which is set as shown in FIG. 6 at the beginning of cycle 6, so the condition of the AND gate 203 is met and the AND gate 204 is set by the pulse of the next phase. The first input of AND gate 218 is an inversion of FF2O5, and if FF2O5 is set, that is, when a response signal is received from the memory, FF2O5 becomes "1" and the first input of 218 becomes "0". becomes.

Therefore, the signal line 200 remains at "0", and the data at address n+1, that is, the address indicated by the NA part in FIG. 3A-2, becomes the output of the address generator 100, and the data processing device proceeds.FF2O4 When set, it enables the second input gate of OR gate 214. The first input gate of OR gate 214 is the reset signal, which is "o". Therefore, the condition of the OR gate 214 is satisfied by the second input gate, and FF2O5 is reset by the pulse of the next phase. This situation can be seen from 204 to 2 in Figure 6.
It is indicated by an arrow C→D pointing to 05. FF2O4 is also I
Set FF2O9 with phase pulse. When FF2O9 is set, signal line 304 is enabled. Signal line 3
04 is a read gate signal to the memory unit in FIG. 5, and outputs the contents of the register 312 of the memory unit to the signal line 307. Signal line 307 is connected to the second input gate of AND gates 216 and 217 in FIG. On the other hand, the first input gates of AND gates 216 and 217 are connected to 204. Part W in Figure 3A-2, more specifically, M in Figure 2 from which Figure 3A-2 was read out.
The W portion of IRlO3 sets or resets FFs 23O and 231 in FIG. FF23O again. The data in 231 is decoded by a decoder 232 and interpreted as shown in FIG. 3E, and in the case of IR designation, the signal line 233 is enabled. In the case of BR designation, the signal line 234 is enabled. The signal line 233 is connected to the third input gate of the AND gate 216, and the signal line 234 is connected to the third input gate of the AND gate 217. Therefore, since the data in FIG. 3A-2 is read and FF2O4 is set, the condition of AND gate 216 or 217 is satisfied,
Insert memory unit 3 in Figure 5 into IR2Ol or BR2O2.
Data from 00 is set. These time charts are also shown in FIG. FIG. 7B shows a time chart when there is no work to be done within the data processing device during a memory unit read, or when data from the memory unit is used in the next cycle.

In cycle 1, address n is specified in the storage unit 102 in FIG. 2, and at the beginning of cycle 2, the address in FIG.
3. The contents of the microprogram in the configuration shown in FIG. 3A-1 differ from the previous case in that the NA section indicates address n+1, but the rest is the same.
That is, 400 is "o", W is "00", and M is "1". Since M is "1", it means that there is a memory request, and therefore, the fourth signal line 210 is enabled. Signal line 210 enables request control circuit 250. Hereinafter, the operation shown in FIG. 4 is performed in the same manner as the time chart shown in FIG. 6 described above. The timing at which the response signal 306 is returned from the memory unit 300 in FIG. 5 is also set from the middle of cycle 3 to the middle of cycle 4, as in FIG. In cycle 2, 400 in Figure 3A-1
is "O", the condition of the AND gate 218 in FIG. 4 is not satisfied, and the signal line 200 is "O". Signal line 2
If 00 is [0], the address generator 100 of FIG. 2 outputs the NA portion of MIRlO3. In this case, the NA part is n
+1 address is specified. Address n+1 is specified in cycle 2, and address 3A- is specified at the beginning of cycle 3 in FIG. 7B.
2 is read out to MIRlO3. 4 in Figure 3A-2
00 is “1” and enables the signal line 400. Signal line 400 is connected to AND gates 203 and 218 in FIG. The first input of AND gate 218 is the inverted signal of FF2O5. At the beginning of cycle 3, it can be seen from FIG. 6 that FF2O5 is not set. When FF2O5 is not set, that is, when there is no response signal from the memory, FF2O5 becomes "
Since the first input gate of the AND gate 218 becomes [1] due to the inversion of FF2O5. Now the signal line 400 is “
Since the signal is "1", the condition of the AND gate 218 is satisfied, and the signal line 200 becomes "1". When the signal line 200 becomes "1", the address creation 100 is R at the beginning of cycle 3.
The contents of EGlOl are sent to the storage unit 102. REGlOl
In cycle 3, data indicating address n+1 is contained, and the data at address n+1 is read out to MIRlO3 again. This can be understood by the fact that the output of address creation 100 in cycle 3 is shown as n+1 in FIG. 7B. Since the data at address n+1 is the data shown in FIG. 3A-2, 400 is "1" and the signal line 400 is enabled again. Then, the conditions of the AND gate 218 are checked again. This is memory unit 30
It continues automatically from 0 until there is a response signal. Naturally, unless FF2O5 is set, the AND gate 211 does not satisfy the condition and does not enable the OR gate 212. Therefore, FF2O7 and 208 remain set. Similarly, the condition for AND gate 203 is not satisfied, so FF2O4 is not set. If there is a response signal 306 from the middle of cycle 3 to the middle of cycle 4, FF2O is activated by the next I-phase pulse.
5 is set.

Since the first input gate of AND gate 218 is the inverse of 205, AND gate 218 fails and therefore does not enable signal line 200. signal line 200
is "0", the address creation 100 in FIG.
The NA part of lO3, ie, the NA part in FIG. 3A-2, is its output. If the NA part in FIG. 3A-2 specifies address X+3, address x+3 will be the output of address creation 100. This is address 100 at site 4 in Figure 7B.
This is shown by the output being at address x+3.
The operations shown in FIG. 7B are such that the data in the control storage unit at address n+1 can be the same whether or not there is a memory response signal 306 at that time, and the microprogram can be executed without being aware of the access time of the memory unit. This shows that it is possible to create . As explained above, according to the present invention, the following advantages can be obtained.

In other words, there is no need to prepare and execute a microprogram with the same configuration from the minimum memory access time to the maximum memory access time when reading a microprogram that opens a register gate. There is no need to disturb other circuits that use the timing pulse since it does not require stopping, and furthermore, there is no need to be aware of the access time of the memory unit when creating a microprogram. Furthermore, another advantage is that memory access can be performed smoothly even if the microprogram is executed continuously for an arbitrary period of time or executed word by word.

[Brief explanation of drawings]

FIGS. 1A, 1B, and 1C are diagrams showing the access time of the conventional method, and FIGS. 1D and 1E are diagrams showing the access time of the present invention. The following are all related to the present invention, and FIG. Block diagram illustrating an example of a control storage unit, Part 3
Figure A-1, Figure 3A-2, and Figure 3A-3 are diagrams showing the structure of the microprogram, Figures 3B, Figure 3C, Figure 3D, and Figure 3E are Figures 3A-1 and 3A-3. Figure 2, 3A-3
4 is a diagram showing an example of a memory unit control circuit in a data processing device, FIG. 5 is a diagram showing an example of a memory unit, and FIG. 6 is a diagram showing an example of a memory unit control circuit. FIG. 4 shows time charts of gates and flip-flops, and FIGS. 7A and 7B show time charts of microprogram addresses and their data in two examples, respectively. Explanation of symbols: 1 to 8 are cycle numbers, 100 is address creation, 101 is a register (REG), 102 is a memory section, 103 is a microinstruction register (MI
R), 200 is a signal line, 201 is an instruction register (R), 202 is a buffer register (BR), 2
10 is a signal line, 250 is a request control circuit, 300 is a memory unit, 301 is a memory address, 302 is a control signal, 303 is a memory unit activation signal, 3
04 is a read gate signal, 306 is a response signal, 307 is read data, 310 is a control circuit, 311 is a storage element,
312 indicates a register.

Claims (1)

[Claims] 1 A signal is sent from a data processing device to a memory unit that stores data using a storage element, and based on this signal, data is read from the storage element and sent to the data processing device, thereby performing data processing. In the data processing method, first signal sending means is provided in the data processing device and sends a memory unit activation signal to the memory unit, and a first signal sending means is provided in the memory unit,
a first storage means for reading, setting, and storing data from the storage element based on the memory unit activation signal; and a first storage means provided in the memory unit to give advance notice that the data will be set a certain period of time before the data is set. a second signal sending means for sending a response signal to the data processing device; a second storage means provided in the data processing device for setting and storing the response signal; a determining means for determining whether or not the response signal is stored in the second storage means; provided in the data processing device, after the determination determines that the response signal is stored; A data processing system characterized by comprising a data reading means for sending a data reading gate signal to the first storage means and reading data stored in the first storage means.