JPS598104B2 - Bit phase adjustment circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a bit phase adjustment circuit.

In general, in various digital devices, it is often necessary to match the changing points of a plurality of signals that are synchronized in frequency but not synchronized in phase to have the same phase.

Conventionally, when such a request was made, a clock extraction circuit was provided for each signal, and phase synchronization was achieved based on the clocks extracted by these clock extraction circuits.
Therefore, a large number of clock extraction circuits are required, which has the disadvantage of hindering miniaturization of the device and increasing the cost of the device. Therefore, it is an object of the present invention to provide a bit phase adjustment circuit that can match changing points of signals that are frequency synchronized but not phase synchronized to the same phase using a simple circuit.

A feature of the present invention for achieving the above object is that in a bit phase adjustment circuit for aligning change points of a plurality of data signals whose frequency is synchronized but whose phase is not synchronized to the same phase, means for extracting a clock from any one of the signals; multiphase clock generation means for generating a clock having a phase different from the extracted clock;
an adjustment circuit provided corresponding to each of the data signals and supplied with M multiphase clocks from the multiphase clock generation means, the adjustment circuit corresponding to the timing of the M multiphase clocks. The present invention comprises a storage means for storing the level of the data signal, a majority decision means for taking a majority vote of the outputs of the storage means, and a means for reading out the result of the majority decision means at a predetermined timing. Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 shows an embodiment of the invention.

The bit phase adjustment circuit 1 receives a plurality of data signals 51 and 52 that are frequency synchronized but not phase synchronized.
, 53 change points to the same phase,
A clock extraction circuit 2 is provided for extracting a clock from a data signal 51, which is one of three data signals. The clock CL from the clock extraction circuit 2 is input to a multiphase clock generation circuit 3, where a multiphase clock G having the same frequency as the clock CL but different phases is generated. In the illustrated example, the multiphase clock G consists of six clocks φ1 to φ6 that have different phases every 60 degrees, and the multiphase clock G includes an adjustment circuit 4, which is provided corresponding to each data signal S1 to S2. 5 and 6, respectively. Adjustment circuits 4 to 6 each have a multiphase clock G.
This circuit determines the level of the data signals S1 to S3 in the time slot of interest by majority vote, and thereby performs phase synchronization of the change points of each data signal at a specific clock timing. FIG. 2 shows the multiphase clock generation circuit 3 and the adjustment circuit 4 in more detail.

The multiphase clock generation circuit 3 is made up of delay circuits 31 to 35 that delay the input signal by 60 degrees, which are connected in series, and the phase is sequentially changed to 60 degrees as shown in FIGS. 3b to 3g.
Clocks φ1 to φ6 shifted by 0 degrees are obtained as a multiphase clock G. On the other hand, the adjustment circuit 4 includes D-type flip-flops 41 to 45 and these D-type flip-flops.
It consists of a majority circuit 46 to which the Q outputs of flops 41 to 45 are input and which takes the majority. A data signal S1 as shown in FIG. 3a is applied to each input D of the D-type flip-flop, and clocks φ, to φ5 are applied to each clock terminal C of the D-type flip-flop as shown. The level of the data signal S1 at the rising edge of each clock is determined by each D-type flip-flop 41 to 4.
5 is stored. The clock φ6 is applied as a timing signal to the majority decision circuit 46, and at the rising edge of the clock φ6, a majority decision is made on the level of the input signal, and the level of the output signal Sa is changed in accordance with the result. Therefore, for example, if we focus on the series of rising points of clocks φ1 to φ5 at time t=Tl, t2, ......, T5, at the rising point of clock φ1 at T, the data signal S1 becomes Since this is a changing point, the output contents of the flip-flop 41 are indeterminate, but at the rising edge of each clock φ2 to φ5 at T to T5, the data signal S
Since the level of , is "1", flip-flop 4
The output contents of 2 to 45 are all "1", and when clock φ6 rises at time T6, flip-flop 4
A majority vote is taken for the output contents from 1 to 45, and the output signal Sa
The level changes to "1" (see Figure 3h). Since the other adjustment circuits 5 and 6 are configured similarly to the adjustment circuit 4 shown in FIG. 2, the times Tl, t2, . . .
An operation similar to the above-described operation at T6 is performed on the data signal S2.
, S3, and therefore, the level changes of the output signals Sb, Sc are set every time the clock φ6 rises, and the levels of the signals Sl, S2, S3, which are synchronized in frequency but not synchronized in phase, are set. It is possible to obtain output signals Sa, Sb, and Sc whose changing points are in the same phase.

In the above embodiment, an example is shown in which a 6-phase polyphase clock is used, but the clock is not limited to 6 phases, but may be an M-phase (M2N) polyphase clock that divides one time slot of the input data signal into N. be able to.

According to the present invention, as described above, when data signals having the same bit rate are regenerated, relayed, or bit synchronized, it is not necessary to have a clock extraction circuit for each and adjust the phase, but a simple clock extraction circuit can be used. Can be adjusted to any phase using a circuit. Furthermore, even if there is jitter in the input data signal, this jitter will not appear in the output signal.

[Brief explanation of drawings]

Fig. 1 is a block diagram of one embodiment of the present invention, and Fig. 2 is a block diagram of an embodiment of the present invention.
Detailed block diagrams of the main parts of the apparatus shown in the figures, and FIGS. 3a to 3h, are time charts for explaining the operations of FIGS. 1 and 2. 1...Bit phase adjustment circuit, 2...Clock extraction circuit, 3...Multiphase clock generation circuit, 4, 5, 6...Adjustment circuit, 31 to 35...
...Delay circuit, 41 to 45...D-type flip-flop, Sl, S2, S3...
Data signal, Sa, Sb, Sc...output signal,
φ, to φ6...Clock.

Claims (1)

[Claims] 1. A means for extracting a clock from any one of the data signals in a bit phase adjustment circuit for aligning the change points of a plurality of data signals that are synchronized in frequency but not synchronized in phase to the same phase. , multiphase clock generation means for generating a clock having a phase different from the extracted clock, and adjustment provided corresponding to each data signal and supplied with M multiphase clocks from the multiphase clock generation means. circuit, the adjustment circuit comprises a storage means for storing the level of the data signal corresponding to the timing of the M multiphase clocks, a majority decision means for taking a majority decision of the outputs of the storage means, and a majority decision means of the majority decision means. A bit phase adjustment circuit comprising: means for reading out a result at a predetermined timing.