JPS59844B2 - I/O device control method - Google Patents

Description

Detailed Description of the Invention The present invention relates to an input/output device control method for a data processing device that operates in a synchronous operation mode.

In a conventional system of this type, when a synchronous operation mode is adopted, an order is sent from a central processing unit (CPU) of one system to an input/output device, and a response signal is received by the CPUs of both systems.

When receiving data, the receiving gate is first opened, data is received from the I/O device, and the gate is closed after a certain period of time. The received data is then read out (window method). With this method, if the certain period of time is too short, one side of the data may not be received, and if it is too long, the transfer capacity with the I/O device is reduced. As a second example of the prior art, there was a method in which data transfer was performed by synchronizing between the CPU and the I/O device.

In this system, it is difficult to synchronize the devices, and it is impossible, especially when the distance between them is long. This invention solves the above-mentioned drawbacks by having the central processors of both systems receive the response signals from the I/O devices and cross-connect them with the central processors of the other systems, and provides an I/O device control system that corrects the phase deviation caused by the response signals from the asynchronous I/O devices between the central processors of both systems.

The present invention is characterized in that in a data processing device 15 in a synchronous operation mode, response signals from the input/output devices to the central processing units (CPUs) of both systems are received by the CPUs of both systems at the same time, and a priority is selected based on a predetermined condition (for example, the received signal of the master CPU is given priority over that of the slave CPU), and the priority selected received signal is sent to the CPU of the other system by a crossover means with the CPU of the other system, and the response signals from the input/output devices are corrected so that there is no phase shift in the CPUs of both systems.

Next, an embodiment of the present invention will be described with reference to the drawings.

In the figure, 2 and 3 are central processing units CPUO operating in synchronous mode.
, CPU1, and for the sake of explanation, CPU0 is the master system and CPU1 is the slave system, but this is not restrictive.

Here, an operation will be described in which an order is sent from the CPUO of the master system (not shown) to the input/output device (10) 1 and a response signal is received by the CPUO and CPU1. First, the CPUO and CPU1 operate on a synchronized clock.
The period is assumed to be sufficiently longer than the propagation delay time of the crossover signal between the first and second terminals.

CPU 01, which receives an order from CPU O, returns a response signal to the CPUs of both systems.
There is a difference in the time it takes for the response signal from 10 to reach the target signal between UO and CPU1. For this reason, when the response signals from 10 are normalized by the clock in CPUO and CPU1, it is not possible to obtain signals of the same phase at the clock level. The present invention is designed to prevent this phase shift from occurring during normalization. First, the response signal from 10 is latched into flip-flops (FF) 4 and 5. It is then delayed by delay circuits 6 and 7, which are synchronized by the clock.
Also, the FFs 4 and 5 are reset by the output signals of the DLs 6 and 7, so that the output signals of the DLs 6 and 7 have a constant pulse width synchronized with the clock.
Since UO is the master system and CPU1 is the slave system, if ACTO=1 and ACT1=0, then multiplexers 8 and 9 will select the output signal of DL6 of CPUO, and the outputs of multiplexers 8 and 9 will be signals of a constant pulse width synchronized at the clock level.
The same explanation can be given for the case where CPU1 is the master system. As explained above, in this example, it is possible to synchronize the response signal from 10 by crossing the output signals of DL 6 and 7 to CPU0 and CPU1. As explained above, the present invention has the effect of correcting the variation in the response signals from the I/O devices between the central processors of the system and enabling synchronized operation of the I/O processing by configuring the response signals from the I/O devices to cross between the central processors.

[Brief description of the drawings]

The figure is a circuit diagram partially showing an embodiment of the present invention in a block diagram.
5: flip-flop; 6, 7: delay circuit;
8, 9...Multiplexer.

Claims (1)

[Claims] An input/output device control method in which, in a data processing device synchronized at the clock level and operating in a synchronous mode, each of two central processing units has a flip-flop which receives a response signal from an input/output device, and a delay circuit which inputs and delays the received output from this flip-flop in synchronization with the clock, and by resetting the flip-flop with the output signal of this delay circuit, the output signal of the delay circuit is made to have a constant pulse width synchronized with the clock, and the output signals of this delay circuit are input to the selection circuit of the central processing unit of the other system, and one of the outputs from the delay circuits of the own system and the other system is selected by a preset signal to obtain the same output, thereby correcting the variation between the two central processing units in the timing of receiving the response signal from the input/output device.