JPS59888B2 - data encoder - Google Patents

Description

[Detailed description of the invention] The present invention relates to data encoders.

When recording digital information on a high-density magnetic recording medium (tape, disk, etc.), the digital information must be encoded in a manner that allows it to be reliably reproduced.

Various encoding techniques have been developed and are well known to those skilled in the art. One effective encoding method is Modified Phase Modulation (MFM).
modified phase module)
It is. Hereinafter, this encoding method will be referred to as MFM encoding. Midfielder
M encoding is performed using various random logic elements. Furthermore, when recording digital information on a magnetic disk,
Bit shifting occurs as the recorded magnetic flux reversal moves from high-density areas of the track to low-density areas.

Such movement is not evident in practice, ie it is actually a time displacement caused by the properties of the magnetic medium. write pre-compensation
A technology known as ion) has been developed and is well known to those skilled in the art. Such techniques prevent shifting of read data bits by equal and opposite time shifts of the write bit data stream. Write pre-correction is typically performed with analog or digital delays. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a new and simplified data encoder for converting a serial bit stream into an MFM coded and write precorrection coded serial bit stream. Other objects and advantages of the invention will become apparent from the following description with reference to the accompanying drawings.

The present invention is an electronic circuit that performs MFM encoding and write pre-correction in one go.

The invention also eliminates the need for analog and digital delay lines, greatly reducing the number of required electronic components. In the present invention, data encoded by the MFM encoding algorithm and the write precorrection encoding algorithm is stored in a read-only memory (ROM).

To determine the output of the encoding circuit, the bit to be encoded, the two previously encoded bits, and the next bit to be encoded are examined. Such a test is performed using a series-parallel type shift register. The four output lines of the shift register are used to address specific portions within the ROM where appropriately encoded data bits are stored. R
The fifth address line to OM reads the encoded data. This data has been pre-write corrected when pre-write correction is required. Each encoded data bit stored in ROM consists of eight equal time segments. Four sections represent logical ones and the other four sections represent logical zeros.

The write precorrection algorithm determines where the data bits are contained within the four sections. The eight time segments are read from memory in parallel form and returned to the original serial bit stream.

FIG. 1 is a circuit diagram of a preferred embodiment of the present invention, which includes a 4-bit serial-to-parallel shift register 2, a 256-bit read-only memory (ROM) 4, an 8-bit parallel-to-serial shift register 6, D. Type flip-flops 8 and 10 are shown.

This circuit receives a stream of encoded serial bits on input line 12 and outputs encoded data on output line 22. The present invention converts each bit of digital information into an MFM code.

It is known to those skilled in the art that the MFM encoding process is as described below. That is, each input bit is logical 1.
An output pulse is generated when the input bit is a logic zero, but an output pulse is generated even if the next input bit is a logic zero only if the previous input bit is a logic zero. As shown in FIG. 2, each section 50 of the encoded output bit is divided into two 1/2 bit sections 52 and 54. The pulse in the 1/2 bit interval 52 is a logic 0 output bit, and the pulse in the 1/2 bit interval 54 is a logic 1 output bit.

The invention further divides each 1/2 bit interval into four time intervals of 250 nanoseconds each.

The encoded output bit period is thus divided into eight 250 nanosecond time periods. These eight time intervals are used to encode the write pre-correction information. Logic 1 or O bit pulse is “NORMAL”
When placed in the time interval marked , the encoded bits are not write precorrected. However, the pulse is [-2
50, the encoded bits are precorrected by -250 nanoseconds. That is,
Such encoded bits occur 250 nanoseconds before normal encoded bits representing the same information occur. When placed in the time interval marked ``Pulse+250'', the encoded bits are precorrected by +250 nanoseconds. That is, it is delayed by 250 nanoseconds. When determining whether write pre-correction is required for an internal track of a magnetic disk, it is necessary to examine the bit to be encoded, the two previously encoded bits and the next to be encoded bit.

As is well known to those skilled in the art, this test is necessary because only certain patterns of bits require pre-correction when writing bits to internal tracks. The bit pattern required for pre-correction and the amount of pre-correction required is tabulated below. In the table, bit A is the next bit to be encoded, bit B is the bit to be encoded, and bits C and D are the two previously encoded bits.

The operation of the present invention will be explained with reference to the circuit diagram in FIG. 1 and the timing waveform diagram in FIG.・Receive a stream, and subsequently receive such bits.
Convert the stream to a parallel 4-bit pattern.

Input line 112 is connected to serial data input terminal SI of shift register 2. Commercially available 74 is used for shift register 2.
A LS164 type shift register is preferred. shift·
A data clock, such as signal B in FIG. 3, on input line 14 connected to clock input CLK of register 2 shifts the serially applied bits through shift register 2. The frequency of data clock B is typically 500 KHz. The data clock is further supplied to the clock input terminal 2CLK of a flip-flop (hereinafter referred to as FF) 8. Each change in the data clock from a low level to a high level shifts the input bit one position to the right. The output of each stage of shift register 2 is used. Output QB, signal F in FIG. 3, is the bit to be encoded. Output QA, signal 2E in FIG. 3, is the next bit to be encoded, and outputs Qc and QD, signals G and H in FIG. 3, are the two previously encoded bits.
Output terminals QA, QB, QC and QD of shift register 2
respectively address line A.

, Al. Connect to ROM4 via A2 and A3. The output of shift register 2 thus addresses the contents of ROM 4. The input line 16 supplies an external on/off control signal (pre-correction signal) for the write pre-correction algorithm, and is connected to the fifth address line A4 of the ROM 4. ROM4 is a 256-bit ROM configured as 32 8-bit loads, preferably a commercially available 7-bit ROM.
It is a 4S288 type ROM.

A bit pattern corresponding to the MFM encoded and write precorrected input serial data bits is stored in ROM 4. ROM 4 is used to generate output words from input words. The input word (address) generated by shift register 2 is decoded by circuitry in ROM 4 and outputs a corresponding output word, indicated by signal 1 in FIG. 3, on output line B. −
Occurs in B7. The output words and corresponding input words from ROM4 at the 32 storage locations within ROM4 are shown in the following table. Addresses 0-15 contain bits encoded by both the MFM and write precorrection algorithms, while addresses 16-31 contain bits encoded by both the MFM and write precorrection algorithms.
Contains bits encoded only by the algorithm.

As can be seen from the table above, write prefix encoding is selected when the signal at address input A4 is a logic zero. Parallel-serial shift register 6 has ROM at its input terminals A-H.
4 output terminal B.

- Receives the encoded 8-bit output word from B7 in parallel form. The shift register 6 converts these parallel inputs into serial outputs, and a commercially available 74LS166 type shift register can be used. shift register 6
input line 18 connected to its clock input terminal CLK.
Shift/Load clock signal. This clock signal is shown as signal C in FIG. 3, and its frequency is eight times that of the data clock. A shift/load clock signal is also provided to the clock input terminal CLK of FFLO. Loading of data into the shift register 6 is controlled by D-type FFs 8 and 10. As mentioned above, FFlo
is clocked by the shift/load clock signal, while F
Clock F8 with the data clock signal.

The high logic level I applied to the D input terminal of FF8 is transmitted to the Q output terminal with a low to high level change of the data clock. Connect the Q output terminal of FF8 to the D input terminal of FF1O. The inverted logic level of the D input of FFLO is transferred to the ζ output terminal with a low to high transition of the shift/load clock. These FFs 8 and 10 serve as control signal generating means for generating shift/load control signals. This o output terminal is connected to the clear input terminal CLR of FF8 and the shift/load input terminal SHI of shift register 6.
Connect to FT/LOAD. The shift/load control signal on line 20 is shown as signal D in FIG. This control signal consists of negative going pulses with a pulse width equal to one period of the shift/load clock pulse and a repetition rate equal to that of the data clock. A shift/load control signal is provided to the shift/load input terminal of shift register 6. When this control signal is low, it energizes parallel data input terminals A through H, and output line B on the next low to high transition of the shift/load clock. - Load the 8-bit word of B7 into shift register 6. shift/
When the load control signal is high level, the parallel input terminals A-H
and shift/load the contents of the shift register
Each change from low to high level of the black ivy shifts one position to the right. The result is the desired encoded serial bit stream on output line 22. The encoded serial bit streams are shown in signals J and K of FIG. Signal K is the result of the same series input signal as signal J, but signal K includes write pre-correction. In the present invention described above, the storage means stores an N-bit parallel digital signal with or without pre-correction applied to each bit of the serial digital input data, and the storage means stores the N-bit parallel digital signal with or without pre-correction applied to each bit of the serial digital input data. and the bits before and after it,
and the storage means are addressed by the precorrection control signal.

The N-bit parallel digital signal from the storage means is then converted into serial digital data during one bit period of the serial digital input data. Therefore, according to the present invention, each bit of serial digital input data is decomposed into periods of 1/N of its bit period, and MFM encoding and, if necessary, pre-correction are performed at once. can be done. Although the preferred embodiments of the invention have been illustrated and described, those skilled in the art will recognize that various modifications and changes can be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a preferred embodiment of the present invention, and FIG.
The figure shows various parts of the encoded data bits,
FIG. 3 shows a timing/waveform diagram for explaining the operation of the circuit of FIG. 1. In the figure, 2 is a serial-parallel shift register, 4 is a read-only memory, 6 is a parallel-serial shift register, and 8 is a parallel-to-parallel shift register.
and 10 are D-type flip-flops.

Claims (1)

[Claims] 1. In a data encoder that performs MFM encoding of the serial digital input data in order to record the serial digital input data on a magnetic recording medium, the serial digital A serial/parallel shift register that shifts input data and converts it into parallel digital data, an N-bit parallel digital signal (N is an integer of 2 or more) subjected to pre-correction according to the MFM encoding, and the MFM An N-bit parallel digital signal corresponding to the encoding and without the above pre-correction is stored, and the pre-correction control signal and the above-mentioned serial/digital signal are stored.
storage means for generating parallel digital signals addressed by said parallel digital data from a parallel shift register; and receiving a second clock signal having a frequency N times the frequency of said first clock signal and said first clock signal. , control signal generating means for generating a shift/load control signal every time N second clock signals are generated;
a parallel-to-serial shift register for loading and shifting the parallel digital signal from the storage means to convert it into serial digital data by a clock signal and the shift/load control signal; 2. A data encoder, wherein said serial digital data is MFM encoded data selectively subjected to said pre-correction.