JPS598911B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device in which a read operation is made faster by setting the read level of a bit line to an appropriate value.

Conventionally, there has been a device of this type as shown in FIG.
FIG. 1 focuses on one column of the memory cell array, and only one memory cell is shown to simplify the explanation. In FIG. 1, 10 and 11 are enhancement type MOS field effect transistors (hereinafter referred to as MOSFETs), each drain of MOSFETIO and 11 is connected to a power supply terminal via a load resistor 14 and 15, respectively, and each source is Grounded. Also,
The gate of MOSFETIO is connected to the drain of MOSFET11, and the gate of MOSFETI1 is connected to the drain of MOSFET11.
A bistable circuit, ie, a flip-flop, is connected to the drain of TIO. As described above, a 1-bit memory cell is configured. Note that Vss is the ground potential. Also,. In this example, MOSFETIO 11 will be explained as an N-channel non-channel type. The drains and sources of MOSFETs 12 and 13 for gates, which have write and read control functions, are MOSFET I, respectively.
connected to the drain of MOSFET II (the source or drain is connected to the bit line 2
0, 21, and the gate is connected to word line 22
It is connected to the.

Similarly, multiple memory cells are MOSFEs for gates.
It is connected to the bit line via T. bit line 2
One end of 0 and 21 is an enhancement type M.
Connected to the sources of OSFETs 18 and 19, and MOSFE
The drains and gates of Tl8 and 19 are connected to the power supply. Further, the other ends of the bit lines 20 and 21 are connected to the I/O line via enhancement type MOSFETs 16 and 17, respectively. The gates of MOSFETs 16 and 17 are connected to the column decoder output. With the above configuration, one column of the memory cell array is formed. Next, the operation will be explained.

A large number of MOSFETs 12 and 13 for memory cells and gates are arranged in a matrix, and a predetermined memory cell is selected by the random access method and information is written and read therein. In the storage state, the word line 22 is at a potential close to zero, the MOSFETs 12, 13 are in a non-conducting state, and the MOSFETs 10, 11 are isolated from the bit lines 20, 21. MOSFETlO
One stable state is when the gate of MOSFET1O is at 'HI', and at this time MOSFET10 is conductive and its drain is at 'LI', so MOSFET11 has its gate 'LI'
The bit lines 20 and 21 are bridged to the potential (VDD-VTH) by the MOSFETs 18 and 19. Here, I is the potential and VTH is the potential of the MOSFETs 18 and 19.
is the threshold potential of Also, normally the 1/O line is also VD.
Breached near D. In order to read information from the memory cell in this state, the word line 22 is charged to a predetermined potential. As a result, M,OSFETl
2 and 13 become conductive, and the stored information in the memory cell is immediately sent to the bit lines 20 and 21. At the same time MOSF
The column decoder output input to the gates of ETl6 and l7 is whisper LI! CH". As shown in Figure 3, the level of the bit line 20 changes from level 31 to level 3.
2, and the level of bit line 21 maintains approximately the bridge charge potential (VDD-VTH). Column decoder output level 35 and bit line 20 level 32
At the time TON when the difference between the two becomes VTil, the MOSFET 16 is turned on and the signal on the pit line 20 is transmitted to the I/O line. After this, the word line 22 is discharged to end the read operation. Normally, in such a semiconductor memory device, since the drive ability of the memory cell is small, the L'' level of the bit line becomes high during reading, and the MOS
The disadvantage is that the turn-on of FET 16 or 17 is delayed, and therefore the signal transmission from the bit line to the I/O line is delayed, which ultimately significantly delays the RAM access time.

In order to eliminate this drawback, by applying a predetermined voltage lower than the power supply level to the gate of the load transistor of the bit line, the SH'' and SLI levels of the bit line at the time of reading are shifted to a lower potential.・MOSFE connected to decoder output
A semiconductor memory device has been proposed that can speed up the turn-on of T and improve the read speed. That is, in FIG. 2, the same reference numerals as in FIG. 1 indicate the same parts.

The gates and drains of the enhancement type MOSFETs 23 and 24 are connected to the power supply terminal, and the sources are connected to the MOSFETs 23 and 24.
It is connected to the gates of SFETs 18 and 19. The rest of the configuration is the same as in FIG. 1. The operation of such a circuit configuration will be explained with reference to FIG.

In the memorized state, MOSFETlO is turned on and the MOSFET1O is turned on.
The drain of ETlO is at a potential close to zero and stores SO'', and MOSFETll is turned on and the MOSFET
The drain of ll stores SI'' at a potential close to the power supply voltage. The bit lines 20 and 21 are bridged to a potential (VDD-2TH) shown at level 33 in FIG. The I/O line is bridged near VDD. When word line 22 is charged and a read operation is initiated, MOSFET l2, l
3 is turned on, and as shown in FIG. 3, the potential of the bit line 20 goes to the 1L" level and the bit line 21 goes to the 'H" level. In this case, two MOSFETs l8, 23
Since the impedance of the load on the bit line 20 is large, the bit line 20 is at a potential level 34, which is lower than that obtained in the conventional configuration, and the bit line 21 is approximately at the precharge potential (V
DD-2VTH) and the potential is lower than the level (DD{TH) obtained with the conventional configuration, which means that the 1L'' level has been lowered without increasing the bit line amplitude. Therefore, At the point in time when the difference between the rising column decoder output level and the SL'' level of the bit line becomes VTH, t'0N & CMOS FET 16 turns on and transfers the signals on bit lines 20 and 21 to I/O faster than in the conventional configuration.
Can be transmitted to the line. After this, the word line 22 is discharged, ending the read operation. By the way, the circuit shown in FIG. 2 described above has one stage of MOSFET 23 and a load MO
The potential of the bit line 20 is set to DD- by SFETl8.
There was a drawback that the voltage could only be lowered to 2VTH.

This invention provides a semiconductor memory device in which the level of the bit line during reading can be shifted to a lower potential by connecting MOSFETs 23 in multiple stages, thereby further improving the reading speed. .

An embodiment of the present invention shown in FIG. 4 will be described below.

In Figure 4, 25, 27, 29 and 26, 28, 30
are MOSFETs connected in series in multiple stages.

Similarly to MOSFETs 23 and 24 in Fig. 2, each MOST
The gate and drain of E may be short-circuited, or it may be biased with a reference voltage generated inside the chip. When the gate and drain are short-circuited, the level of the bit line during reading in this embodiment is DD-(n+1)TH (n is the load MOSFET l8, l
The number of MOSFETs connected in series to the gates is 9), and a faster successive output speed can be obtained.

In the above embodiment, an N-channel MOSFET is used, but a P-channel MOSFET can be used in the same manner.

In this case, the polarity of the voltage is reversed. Although a resistor is used as the load, a MOSFET can also be used instead of the resistor. As explained above, according to the present invention, since the MOS transistors connected in series in multiple stages are connected between the gate of the load transistor of the bit line and the power supply terminal, it is possible to accurately shift the level of the bit line to an arbitrary low level. Therefore, there is an advantage that the lower level of the bit line can be lowered without increasing the amplitude of the bit line, and high-speed read operation can be realized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional semiconductor memory device, FIG. 2 is a circuit diagram of a semiconductor memory device for explaining the present invention, FIG. 3 is an explanatory diagram of circuit operation, and FIG. 4 is an embodiment of the present invention. FIG. 2 is a circuit diagram of a semiconductor memory device showing an example. In the figure, 10, 11, 12, 13, 16, 17, 18, 1
9, 23, 24, 25-30, 36-41 are enhancement type MOSFETs, l4, l5 are resistors, 20,
21 is a bit line, 22 is a word line, 31 is the SH'' level of the bit line in the conventional configuration, 32 is the L level of the bit line in the conventional configuration, 33 is the SH'' level of the bit line in the configuration shown in FIG.
4 is the SLll level of the bit line in the configuration shown in FIG. 35 is the column decoder output level.

Claims (1)

[Claims] 1 A memory cell in which a first and second transistor constitute a bistable circuit, a third and fourth transistor for a gate whose source or drain is connected to each drain of the first and second transistors, and this third transistor. and a bit line having a common write information line and a read information line connected to the drain or source of the fourth transistor, respectively, and a common write and read selection line connected to the gates of the third and fourth transistors. In a semiconductor memory device comprising a word line and a constant voltage generating means for DC-applying a predetermined potential lower than a power supply voltage to the gate of a load transistor of the bit line, the constant voltage generating means includes a multi-stage MOS transistors connected in series are provided, and the gate electrodes of the MOS transistors are connected to respective drain electrodes or a predetermined potential, and the drain of the topmost transistor of this MOS transistor group is connected to the power supply terminal, and the source of the bottommost transistor is connected to the bit. A semiconductor memory device characterized in that each line is connected to the gates of load transistors.