JPS599116B2 - Memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF APPLICATION OF THE INVENTION The present invention relates to the refresh operation control of a memory device whose memory element is a dynamic memory element (eg, MOS dynamic memory) that requires a refresh operation of stored information at a constant cycle.

PRIOR ART In the past, various methods have been devised to use memory efficiently, but the interleaf method, which is widely used today, aims to use memory more efficiently and uses multiple storage units. This is a control method that divides into independent functional units and controls each of them independently.
Depending on the ambient conditions, 2-way, 4-way, and 8-way interleaf control systems are generally widely used.

FIG. 1 shows an example of a CPU configured using a 4-way interleaf system, and the configuration will be explained below.

The main storage device 1 is B. - It is composed of 4 banks of B3, and the addressing is horizontally 0 to T, 8 to 15, etc.
...They are numbered 24-31. Each bank is composed of a control section 4 and a storage section 5, and is connected to and controlled by a bank control section 6 of the main memory control device 2. The control unit 4 controls read/write etc. for the storage unit 5 and controls access acceptance from the bank control unit 6. FIG. 2 shows a detailed block diagram of the bank controller and bank set shown in FIG.

The storage section to which the present invention is applied is a dynamic memory, which is composed of elements that require refresh operations of stored contents at regular intervals.

For this reason, a refresh counter 8 is provided in FIG. 2, and a carry signal periodically generated in the most significant bit of the counter activates the refresh control function of the storage control section T to perform a refresh operation. At this time, the memory element to be refreshed is indicated by the address counter 9 that counts the carry signal of the most significant bit of the refresh counter 8, and is selected by the address bus and address switching circuit 11 used in normal memory reference operations. and is supplied to the storage section 5. A normal memory reference operation starts when an operation request signal 100 is issued from the bank control section 6 in the main memory control device 2 to the storage control section 7. Operation request signal 1
When 00 is turned on, the storage control unit T accepts the operation request signal 100 when the refresh operation is not in progress or when the refresh start request signal 103 is not activated at the same time as the operation request, and at the same time receives the request signal. A request acceptance signal 101 indicating that preparations for starting the requested operation are completed is returned to the bank control unit 6. Since the subsequent operations are outside the scope of the present invention, the details will be omitted, but in general, reading the memory contents,
Or a write operation is performed.

Problems with the prior art Since the prior art uses an immediate response method that proceeds after checking that the operation request has been accepted by the storage device, the request acceptance signal may not turn on due to a failure of the storage control unit 7, etc. Otherwise, if the control system malfunction cannot be detected, the process may stop without being able to detect the control system malfunction.

For this reason, a time monitoring function, etc. between issuing a request and turning on the acceptance signal is required, which leads to an increase in hardware, and requires refresh counter address switching for each bank of the storage device. This requires a refresh priority circuit, a reception prohibition circuit during refresh operation, a request reception response circuit, etc., and a large amount of hardware is required in a storage device using the multi-way interleaf method.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a storage system that allows refresh operations with less hardware in a storage device and a storage control device that are constructed of memory elements that require refresh operations.

Summary of the Invention The present invention is characterized in that at least a refresh counter is provided commonly to each bank of the storage device, and a refresh operation is performed independently for each bank.

Embodiment of the Invention FIG. 3 shows an embodiment of a bank constituting a main memory device to which the system of the present invention is applied.

The storage control unit 7' does not include a refresh priority circuit, a request acceptance response circuit, a busy acceptance prohibition circuit, a request waiting circuit, and the like.

First, the refresh operation will be explained.

Along with the operation request signal 100 (EXC), a refresh mode signal M is generated. , the refresh address is sent to the bank, the storage control unit 7' sends the EXC signal 100.
The refresh address is set in the memory address register 10. In the storage control unit 7', the operation request is a refresh mode signal M. Knowing that this is a refresh operation, the memory unit control signal C is activated. -Cn, only the signal necessary for the refresh operation is turned on and supplied to the storage unit 5 together with the address 105, the refresh operation is performed, and after a certain period of time, the storage unit control signal C is output. - Turn off Cn and end the refresh operation. Next, when the read mode signal M-read address is sent to the bank in conjunction with the EXC signal 100, the writing control unit 7' controls the EXC signal 100.
It is activated by the C signal 100 and sets the read address in the memory address register 10.

In the storage control unit 7/, the operation request is read mode signal M,
Knowing that it is a read operation, the memory unit control signal C is activated.
- Only the signal necessary for the internal read operation of Cn is turned on and supplied to the storage unit 5 together with the address 105, a read operation is performed, and after a certain period of time, the read data from the storage unit 5 is placed on the read data path D and the memory The memory control signal C is set in the register 12. -Cn is turned off. As explained above, in the storage device, refresh operations are processed in the same way as normal access operations. FIG. 4 shows an embodiment of a main storage control device to which the method of the present invention is applied, which connects and controls the main storage device shown in FIG.

In FIG. 4, reference numerals 8, 9, and 11 function in the same manner as the refresh counter, address counter, and address switching circuit provided in each bank in the prior art. The refresh request latch 13 is set by the refresh request signal 103 and the access acceptance end signal 10
8. The reception priority circuit 14 determines the priority of memory access request reception from each CPU, and always gives the refresh request the highest priority.

The request control circuit 15 decodes the received memory access request, activates the bank control unit, reports the completion of reception to each BPU, etc.

The refresh operation according to the present invention is performed as follows. When a carry occurs in the address counter 9 from the highest point of the refresh counter 8, the refresh request signal 103 is turned on (occurs every fixed period), and the refresh request latch 13 is set. When the refresh request latch 13 is set, the refresh access signal 106 is turned on and applied to the reception priority circuit 14. Reception priority circuit 1
4 is the bank control busy signal B for each bank. −
If either Bn is off, the refresh select signal 107, which indicates that a refresh request has been accepted, is turned on and the address switching circuit output is switched to the address counter 9, and at the same time, the request control circuit 15 is instructed to start the refresh operation. do. The request control circuit 15 instructs a refresh operation using a refresh mode command signal 109, and sends a bank control activation signal H.-Hn to a bank in an empty state (BO to Bn are off) to the bank control unit 6' of each bank. When all banks have been started, the access acceptance end signal 108 is turned on and the refresh request latch 1 is activated.
3, complete the series of refresh operations, and press C.
The state becomes possible for PU memory reference operation. In the storage device controlled as described above, since the refresh control state can be grasped within the storage control device, it is possible to determine whether the refresh control is possible or not between the bank control unit 6' and the storage control unit 7' in response to a reference request from the CPU. Further, since the refresh control of each bank is controlled by one set of control circuits, control becomes simple and the amount of hardware can be reduced.

Effects of the Invention Since the configuration is as described above, in the present invention, processing can be performed sequentially without a temporary stop in the storage device and the storage control device. By providing one set of refresh operation circuits, all of the storage devices can be refreshed. Therefore, with a small amount of hardware, it is possible to realize a storage device and a storage control device that can perform refresh operations. Refresh operations can also be processed without any difference.

[Brief explanation of drawings]

FIG. 1 shows a system configuration including a storage device employing a 4-way interleaf system.FIG. 2 is a block diagram of a prior art example related to the present invention. 3 and 4 show block diagrams of one embodiment of the present invention. 13 is a refresh request latch, 14 is an acceptance priority circuit, 15 is a request control circuit, 106 is a refresh access signal, 107 is a refresh select signal, 108 is an access acceptance end signal, and 109 is a refresh Mode command signals, AO, an are operation mode command signals, BO, bn are pack control busy signals, HO-Hn are bank control activation signals, RO
-Rn is a BPU memory request signal, SO-Sn is a BPU select signal, and 6' is a bank control unit.

Claims (1)

[Claims] 1. In a storage control method for controlling a storage device that uses a dynamic storage element that requires a refresh operation of stored information at a constant cycle, and divides a storage section into a plurality of banks so that each bank can operate independently, at least A refresh counter and a control means for determining a bank to be activated based on a refresh request signal from the counter, a busy signal of each bank, and a request signal for the storage device are provided in common for each bank of the storage device, and an empty bank is A storage control method characterized by performing refresh operations independently for each bank.