JPS599118B2 - Charge level detection method for charge transport type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer type semiconductor device (hereinafter simply referred to as a charge transfer type semiconductor device) which stores N bits of information at charge levels of 2N=M stages in one unit of an MIS capacitor for storing and transferring charge. C
The present invention relates to a detection method for detecting charge levels in 2N=M stages in a CD memory (CD memory).

Generally, the problem with CCD memory is how many bits can be integrated per unit area, and one way to achieve high integration is to use the multilevel storage method (hereinafter simply referred to as simply (It's called MLS method)
is proposed.

As an example, FIG. 1 shows 2 bits of information in 4 stages. This figure shows the charge accumulation state of a CCD memory using a 2-bit MLS method that stores charge levels. In this case, lst, 2nd
When (1, 1), the signal charge is Q, and when (1, O), the signal charge is 2/3Q, and (O, 1 ), the signal charge is 1/3
Q, and the signal charge is O when (O20). Note that 1 is a potential well and 2 is a signal charge. However, conventionally, there has been no method for detecting the charge level of a CCD memory using the MLS method, which has the disadvantage that it cannot be put to practical use.

Therefore, the object of the present invention is to develop a CCD using the MLS method.
The present invention provides a detection method capable of detecting the level of signal charges in a memory.

In order to achieve such an object, the present invention, as a first step, compares the read signal charge with a reference charge QR (1) = 1/2Q accumulated in a dummy cell, and when the signal charge is larger than the reference charge, ' When it is small, it is set to ``0'', and in the second step, the signal charge determined to be ``1'' in the first step is again converted to the reference charge QR(2) by 1/2Q+2N-2/
Compare and judge as M-1Q, ``'1〃 or '0''
Then, the signal charge determined to be 'O' in the first step is determined as '1' or '0' by comparing the reference charge QR(2) with 1/2Q-2N-2/M-1Q again. , when the comparison judgment result of the previous stage is '1', the reference charge QR of the nth stage
(n) is QR(n-1)+2N-n/M-1Q, and when the comparison judgment result of the previous stage is '0'', the reference charge QB(n) of the nth stage is set as QR(n-1)- 2N-n/M-1Q is detected as a binary code by repeating it while changing n to 2, 3...N, and will be explained in detail below using an example.Second The figure is a block diagram showing an embodiment of the charge level detection method for a charge transfer type semiconductor device according to the present invention.

In the same figure, 3 is a CCD memory shift register, 4
is a sense amplifier, 5 is a multiplexer, 6a is a first dummy cell that stores reference charge 5/6Q, and 6b is reference charge 1
The second dummy cell 6c stores the reference charge 1/2Q.
The third dummy cell stores 6Q, 7 is the output node of the sense amplifier 4, and 8 is the reference node of the sense amplifier 4. Next, the operation of the charge level detection method for the charge transfer type semiconductor device according to the above configuration will be explained with reference to FIG.

First, the signal charge output from the shift register 3 of the CCD memory is output to the output node 7 of the sense amplifier 4, and at the same time, the reference charge 1/2Q accumulated in the second dummy cell 6b is read out and sent to the sense via the multiplexer 5. Output to reference node 8 of amplifier 4.

Therefore, the sense amplifier 4 has a signal charge and a reference charge 1/
Determine the magnitude relationship with 2Q, signal charge>reference charge 1/2
When Q, it outputs '1'' and the signal charge becomes the reference charge 1/
When it is 2Q, it outputs '0''. This comparison and judgment operation is the first stage. After this judgment by the sense amplifier 4, the reference charge 1/2Q of the reference lens note 8 is set. Based on the determination result of ゝ1'' output from the sense amplifier 4, the multiplexer 5 outputs the reference charge 5/6Q of the first dummy cell 6a to the reference node 8 of the sense amplifier 4. Therefore, the sense amplifier 4 determines the magnitude relationship between the reference charge 5/6Q and the signal charge, and outputs ``1'' when the signal charge>reference charge 5/6Q, and the signal charge minus the reference charge 5/6Q. When , '0'' is output.
Also, in the first stage, the 0 output from the sense amplifier 4 is
'', the reference charge 1 of the third dummy cell 6c
/6Q is input to the reference node 8 of the sense amplifier 4 via the multiplexer 5. Therefore, the sense amplifier 4 determines the magnitude relationship between the signal charge and this reference charge 1/6Q, and outputs a signal when the signal charge>reference charge 1/6Q, and the signal charge is smaller than the reference charge 1/6Q. Sometimes '0
" is output. This comparison and judgment operation is the second step. FIG. 4 is a block diagram showing another embodiment of the charge level detection method for a charge transfer type semiconductor device according to the present invention. In the same figure, 6d is a fourth dummy cell that stores a reference charge 1/2Q, and 6e is a fifth dummy cell that stores a reference charge 1/3Q.Next, regarding the operation of the charge level detection method of the charge transfer type semiconductor device according to the above configuration. An explanation will be given with reference to Fig. 5.First, the signal charge output from the shift register 3 of the CCD memory is output to the output node 7 of the sense amplifier 4, and at the same time, the signal charge is output to the output node 7 of the sense amplifier 4, and at the same time, the signal charge is output to the reference charge 1/2Q accumulated in the fourth dummy cell 6d. is read out.

Therefore, the sense amplifier 4 has a signal charge and a reference charge 1/
Determine the magnitude relationship with 2Q, signal charge>reference charge 1/2
When Q, S1/' is output and the signal charge becomes the reference charge 1/
When it is 2Q, it outputs '0''. This comparison judgment operation is the first stage. After this first stage judgment, the signal charge at the output node 7 of the sense amplifier 4 and the reference charge 1 at the reference node 8 are output. /2Q are both held as they are without being reset. Then, when the judgment result of the sense amplifier 4 is input to the multiplexer 5, the fifth dummy cell 6e is driven to transfer the reference charge 1/3Q to the output node 7. to signal charge or reference node 8
is selectively added to the reference charge 1/2Q. That is, when the determination result of the sense amplifier 4 is '11', the reference charge 1/3Q of the fifth dummy cell 6e is added to the reference charge 1/2Q of the reference node 8. On the other hand, when the judgment result of the sense amplifier 4 is '0'', the reference charge 1/3Q of the fifth dummy cell 6e is added to the signal charge of the output node 7. Therefore, the judgment result of 'B' output from the sense amplifier 4 is Based on the result, the sense amplifier 4 compares and determines the magnitude relationship between the signal charge and the charge (1/2Q+1/3Q) of the reference node 8, and determines the signal charge>charge (1/2Q+1/3Q).
When , it outputs ゞbi, and the signal charge〈charge (1/2Q+
1/3Q), it outputs 'O''. Also, based on the determination result of 'O'' output from the sense amplifier 4, the sense amplifier 4 outputs the signal charge + reference charge 1/3Q and the reference charge 1 of the reference node 8. /2Q is determined, and when signal charge + reference charge 1/3Q>reference charge 1/2Q, S1'' is output, and when signal charge + reference charge 1/3Q<reference charge 1/2Q, ゞO ” is output. This comparison and determination operation is the second stage. Note that the above is a 2-bit ML
Although the S method has been explained, for the MLS method with 3 bits or more, 1/2Q+2N- is used as the reference charge in the second stage.
1/M-1Q and 1/2Q-22/M-1Q (however,
Of course, it is possible to perform a similar comparative judgment and detect it as a binary code by using (N and M indicate the number of bits and the number of charge level stages in the second stage).

As described above in detail, according to the charge level detection method for a charge transport type semiconductor device according to the present invention, an MLS type CCD memory can be easily realized, and a CCD memory can be easily realized.
This has the effect of increasing the density of CD memory.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the charge accumulation state of a CCD memory using a 2-bit MLS method that stores 2-bit information at four charge levels, and FIG. 2 shows the charge levels of a charge-transfer type semiconductor device according to the present invention. A block diagram showing an embodiment of the detection method, FIG. 3 is a diagram for explaining the operation of the charge level detection method shown in FIG. 2, and FIG. 4 shows a charge level detection method for a charge transport type semiconductor device according to the present invention. FIG. 5 is a block diagram showing another embodiment of the present invention, and is a diagram for explaining the operation of the charge level detection method shown in FIG. 1... Potential well, 2... Signal charge, 3... CCD memory shift register, 4... Sense amplifier, 5... Multiplexer, 6a...First dummy cell, 6b...
...Second dummy cell, 6c...Third dummy cell, 6d...Fourth dummy cell, 6e...
...5th dummy cell.

Claims (1)

[Claims] 1 MIS capacitor for storing and transferring charge
In a charge level detection method for a charge transfer type semiconductor device in which N bits of information are stored in a unit at charge levels in 2^N=M stages, as a first step, the read signal charge is stored in a dummy cell as a reference. Charge Q_R(1)=1/2Q
When the signal charge is larger than the reference charge, "1"
'', when it is small, set it to ``0'', and as the second stage, the first
The signal charge determined to be “1” in the step is again the reference charge Q_
Compare and judge R(2) as 1/2Q+2^N^-^2/M-1Q and set it as "1" or "0", and in the first step "
The signal charge determined to be 0'' is again the reference charge Q_R(2)
is compared and determined as 1/2Q-2^N^-^2/M-1Q and determined as "1" or "0", and when the comparison determination result of the previous stage is "1", the reference charge Q_R of the nth stage (n) to Q
_R(n-1)+2^N^-^n/M-1Q, and when the comparison judgment result of the previous stage is "0", the reference charge Q_R(n) of the nth stage is Q(n-1)- 2^N^-^n/M-1
A charge level detection method for a charge transfer type semiconductor device, characterized in that detection is performed as a binary code by repeating the process while changing n as Q to 2, 3, . . . N. 2. The charge level detection method for a charge transport type semiconductor device according to claim 1, wherein the reference charges in the second stage are respectively stored in dummy cells. 3 The reference charge 2^N^-^n/M-1Q for the reference charge Q_R(n) in the n-th stage is stored in the dummy cell,
The charge transfer type according to claim 1, wherein the charge transfer type is selectively added to the signal charge or the reference charge Q_R(n-1) of the previous stage according to the comparison and determination result of the previous stage for comparison and determination. A charge level detection method for semiconductor devices.